1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ALPHA_LCA__H__
3 #define __ALPHA_LCA__H__
4
5 #include <asm/compiler.h>
6 #include <asm/mce.h>
7
8 /*
9 * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,
10 * for example).
11 *
12 * This file is based on:
13 *
14 * DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors
15 * Hardware Reference Manual; Digital Equipment Corp.; May 1994;
16 * Maynard, MA; Order Number: EC-N2681-71.
17 */
18
19 /*
20 * NOTE: The LCA uses a Host Address Extension (HAE) register to access
21 * PCI addresses that are beyond the first 27 bits of address
22 * space. Updating the HAE requires an external cycle (and
23 * a memory barrier), which tends to be slow. Instead of updating
24 * it on each sparse memory access, we keep the current HAE value
25 * cached in variable cache_hae. Only if the cached HAE differs
26 * from the desired HAE value do we actually updated HAE register.
27 * The HAE register is preserved by the interrupt handler entry/exit
28 * code, so this scheme works even in the presence of interrupts.
29 *
30 * Dense memory space doesn't require the HAE, but is restricted to
31 * aligned 32 and 64 bit accesses. Special Cycle and Interrupt
32 * Acknowledge cycles may also require the use of the HAE. The LCA
33 * limits I/O address space to the bottom 24 bits of address space,
34 * but this easily covers the 16 bit ISA I/O address space.
35 */
36
37 /*
38 * NOTE 2! The memory operations do not set any memory barriers, as
39 * it's not needed for cases like a frame buffer that is essentially
40 * memory-like. You need to do them by hand if the operations depend
41 * on ordering.
42 *
43 * Similarly, the port I/O operations do a "mb" only after a write
44 * operation: if an mb is needed before (as in the case of doing
45 * memory mapped I/O first, and then a port I/O operation to the same
46 * device), it needs to be done by hand.
47 *
48 * After the above has bitten me 100 times, I'll give up and just do
49 * the mb all the time, but right now I'm hoping this will work out.
50 * Avoiding mb's may potentially be a noticeable speed improvement,
51 * but I can't honestly say I've tested it.
52 *
53 * Handling interrupts that need to do mb's to synchronize to
54 * non-interrupts is another fun race area. Don't do it (because if
55 * you do, I'll have to do *everything* with interrupts disabled,
56 * ugh).
57 */
58
59 /*
60 * Memory Controller registers:
61 */
62 #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
63 #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
64 #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
65 #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
66 #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
67 #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
68 #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
69 #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
70 #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
71 #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
72 #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
73 #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
74 #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
75 #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
76 #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
77 #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
78 #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
79 #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
80 #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
81
82 /*
83 * I/O Controller registers:
84 */
85 #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
86 #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
87 #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
88 #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
89 #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
90 #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
91 #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
92 #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
93 #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
94 #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
95 #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
96 #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
97 #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
98 #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
99 #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
100 #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
101 #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
102 #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
103 #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
104 #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
105 #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
106 #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
107
108 /*
109 * Memory spaces:
110 */
111 #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
112 #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
113 #define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
114 #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
115 #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
116
117 /*
118 * Bit definitions for I/O Controller status register 0:
119 */
120 #define LCA_IOC_STAT0_CMD 0xf
121 #define LCA_IOC_STAT0_ERR (1<<4)
122 #define LCA_IOC_STAT0_LOST (1<<5)
123 #define LCA_IOC_STAT0_THIT (1<<6)
124 #define LCA_IOC_STAT0_TREF (1<<7)
125 #define LCA_IOC_STAT0_CODE_SHIFT 8
126 #define LCA_IOC_STAT0_CODE_MASK 0x7
127 #define LCA_IOC_STAT0_P_NBR_SHIFT 13
128 #define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
129
130 #define LCA_HAE_ADDRESS LCA_IOC_HAE
131
132 /* LCA PMR Power Management register defines */
133 #define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL)
134 #define LCA_PMR_PDIV 0x7 /* Primary clock divisor */
135 #define LCA_PMR_ODIV 0x38 /* Override clock divisor */
136 #define LCA_PMR_INTO 0x40 /* Interrupt override */
137 #define LCA_PMR_DMAO 0x80 /* DMA override */
138 #define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */
139 #define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */
140 #define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L
141
142 /* LCA PMR Macros */
143
144 #define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR)
145 #define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d))
146
147 #define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV)
148 #define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV)
149 #define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c)))
150
151 /* LCA PMR Divisor values */
152 #define LCA_PMR_DIV_1 0x0
153 #define LCA_PMR_DIV_1_5 0x1
154 #define LCA_PMR_DIV_2 0x2
155 #define LCA_PMR_DIV_4 0x3
156 #define LCA_PMR_DIV_8 0x4
157 #define LCA_PMR_DIV_16 0x5
158 #define LCA_PMR_DIV_MIN DIV_1
159 #define LCA_PMR_DIV_MAX DIV_16
160
161
162 /*
163 * Data structure for handling LCA machine checks. Correctable errors
164 * result in a short logout frame, uncorrectable ones in a long one.
165 */
166 struct el_lca_mcheck_short {
167 struct el_common h; /* common logout header */
168 unsigned long esr; /* error-status register */
169 unsigned long ear; /* error-address register */
170 unsigned long dc_stat; /* dcache status register */
171 unsigned long ioc_stat0; /* I/O controller status register 0 */
172 unsigned long ioc_stat1; /* I/O controller status register 1 */
173 };
174
175 struct el_lca_mcheck_long {
176 struct el_common h; /* common logout header */
177 unsigned long pt[31]; /* PAL temps */
178 unsigned long exc_addr; /* exception address */
179 unsigned long pad1[3];
180 unsigned long pal_base; /* PALcode base address */
181 unsigned long hier; /* hw interrupt enable */
182 unsigned long hirr; /* hw interrupt request */
183 unsigned long mm_csr; /* MMU control & status */
184 unsigned long dc_stat; /* data cache status */
185 unsigned long dc_addr; /* data cache addr register */
186 unsigned long abox_ctl; /* address box control register */
187 unsigned long esr; /* error status register */
188 unsigned long ear; /* error address register */
189 unsigned long car; /* cache control register */
190 unsigned long ioc_stat0; /* I/O controller status register 0 */
191 unsigned long ioc_stat1; /* I/O controller status register 1 */
192 unsigned long va; /* virtual address register */
193 };
194
195 union el_lca {
196 struct el_common * c;
197 struct el_lca_mcheck_long * l;
198 struct el_lca_mcheck_short * s;
199 };
200
201 #ifdef __KERNEL__
202
203 #ifndef __EXTERN_INLINE
204 #define __EXTERN_INLINE extern inline
205 #define __IO_EXTERN_INLINE
206 #endif
207
208 /*
209 * I/O functions:
210 *
211 * Unlike Jensen, the Noname machines have no concept of local
212 * I/O---everything goes over the PCI bus.
213 *
214 * There is plenty room for optimization here. In particular,
215 * the Alpha's insb/insw/extb/extw should be useful in moving
216 * data to/from the right byte-lanes.
217 */
218
219 #define vip volatile int __force *
220 #define vuip volatile unsigned int __force *
221 #define vulp volatile unsigned long __force *
222
223 #define LCA_SET_HAE \
224 do { \
225 if (addr >= (1UL << 24)) { \
226 unsigned long msb = addr & 0xf8000000; \
227 addr -= msb; \
228 set_hae(msb); \
229 } \
230 } while (0)
231
232
lca_ioread8(void __iomem * xaddr)233 __EXTERN_INLINE unsigned int lca_ioread8(void __iomem *xaddr)
234 {
235 unsigned long addr = (unsigned long) xaddr;
236 unsigned long result, base_and_type;
237
238 if (addr >= LCA_DENSE_MEM) {
239 addr -= LCA_DENSE_MEM;
240 LCA_SET_HAE;
241 base_and_type = LCA_SPARSE_MEM + 0x00;
242 } else {
243 addr -= LCA_IO;
244 base_and_type = LCA_IO + 0x00;
245 }
246
247 result = *(vip) ((addr << 5) + base_and_type);
248 return __kernel_extbl(result, addr & 3);
249 }
250
lca_iowrite8(u8 b,void __iomem * xaddr)251 __EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
252 {
253 unsigned long addr = (unsigned long) xaddr;
254 unsigned long w, base_and_type;
255
256 if (addr >= LCA_DENSE_MEM) {
257 addr -= LCA_DENSE_MEM;
258 LCA_SET_HAE;
259 base_and_type = LCA_SPARSE_MEM + 0x00;
260 } else {
261 addr -= LCA_IO;
262 base_and_type = LCA_IO + 0x00;
263 }
264
265 w = __kernel_insbl(b, addr & 3);
266 *(vuip) ((addr << 5) + base_and_type) = w;
267 }
268
lca_ioread16(void __iomem * xaddr)269 __EXTERN_INLINE unsigned int lca_ioread16(void __iomem *xaddr)
270 {
271 unsigned long addr = (unsigned long) xaddr;
272 unsigned long result, base_and_type;
273
274 if (addr >= LCA_DENSE_MEM) {
275 addr -= LCA_DENSE_MEM;
276 LCA_SET_HAE;
277 base_and_type = LCA_SPARSE_MEM + 0x08;
278 } else {
279 addr -= LCA_IO;
280 base_and_type = LCA_IO + 0x08;
281 }
282
283 result = *(vip) ((addr << 5) + base_and_type);
284 return __kernel_extwl(result, addr & 3);
285 }
286
lca_iowrite16(u16 b,void __iomem * xaddr)287 __EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
288 {
289 unsigned long addr = (unsigned long) xaddr;
290 unsigned long w, base_and_type;
291
292 if (addr >= LCA_DENSE_MEM) {
293 addr -= LCA_DENSE_MEM;
294 LCA_SET_HAE;
295 base_and_type = LCA_SPARSE_MEM + 0x08;
296 } else {
297 addr -= LCA_IO;
298 base_and_type = LCA_IO + 0x08;
299 }
300
301 w = __kernel_inswl(b, addr & 3);
302 *(vuip) ((addr << 5) + base_and_type) = w;
303 }
304
lca_ioread32(void __iomem * xaddr)305 __EXTERN_INLINE unsigned int lca_ioread32(void __iomem *xaddr)
306 {
307 unsigned long addr = (unsigned long) xaddr;
308 if (addr < LCA_DENSE_MEM)
309 addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
310 return *(vuip)addr;
311 }
312
lca_iowrite32(u32 b,void __iomem * xaddr)313 __EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
314 {
315 unsigned long addr = (unsigned long) xaddr;
316 if (addr < LCA_DENSE_MEM)
317 addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
318 *(vuip)addr = b;
319 }
320
lca_ioportmap(unsigned long addr)321 __EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
322 {
323 return (void __iomem *)(addr + LCA_IO);
324 }
325
lca_ioremap(unsigned long addr,unsigned long size)326 __EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr,
327 unsigned long size)
328 {
329 return (void __iomem *)(addr + LCA_DENSE_MEM);
330 }
331
lca_is_ioaddr(unsigned long addr)332 __EXTERN_INLINE int lca_is_ioaddr(unsigned long addr)
333 {
334 return addr >= IDENT_ADDR + 0x120000000UL;
335 }
336
lca_is_mmio(const volatile void __iomem * addr)337 __EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr)
338 {
339 return (unsigned long)addr >= LCA_DENSE_MEM;
340 }
341
342 #undef vip
343 #undef vuip
344 #undef vulp
345
346 #undef __IO_PREFIX
347 #define __IO_PREFIX lca
348 #define lca_trivial_rw_bw 2
349 #define lca_trivial_rw_lq 1
350 #define lca_trivial_io_bw 0
351 #define lca_trivial_io_lq 0
352 #define lca_trivial_iounmap 1
353 #include <asm/io_trivial.h>
354
355 #ifdef __IO_EXTERN_INLINE
356 #undef __EXTERN_INLINE
357 #undef __IO_EXTERN_INLINE
358 #endif
359
360 #endif /* __KERNEL__ */
361
362 #endif /* __ALPHA_LCA__H__ */
363