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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#include "am33xx.dtsi"
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	model = "Phytec AM335x phyCORE";
12	compatible = "phytec,am335x-phycore-som", "ti,am33xx";
13
14	aliases {
15		rtc0 = &i2c_rtc;
16		rtc1 = &rtc;
17	};
18
19	cpus {
20		cpu@0 {
21			cpu0-supply = <&vdd1_reg>;
22		};
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x80000000 0x10000000>; /* 256 MB */
28	};
29
30	vcc5v: fixedregulator0 {
31		compatible = "regulator-fixed";
32		regulator-name = "vcc5v";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35		regulator-boot-on;
36		regulator-always-on;
37	};
38};
39
40/* Crypto Module */
41&aes {
42	status = "okay";
43};
44
45&sham {
46	status = "okay";
47};
48
49/* EMMC */
50&am33xx_pinmux {
51	emmc_pins: pinmux_emmc_pins {
52		pinctrl-single,pins = <
53			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
54			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
55			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
56			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
57			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
58			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
59			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad4.mmc1_dat4 */
60			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad5.mmc1_dat5 */
61			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad6.mmc1_dat6 */
62			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad7.mmc1_dat7 */
63		>;
64	};
65};
66
67&mmc2 {
68	pinctrl-names = "default";
69	pinctrl-0 = <&emmc_pins>;
70	vmmc-supply = <&vmmc_reg>;
71	bus-width = <8>;
72	ti,non-removable;
73	status = "disabled";
74};
75
76/* Ethernet */
77&am33xx_pinmux {
78	ethernet0_pins: pinmux_ethernet0 {
79		pinctrl-single,pins = <
80			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
81			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
82			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
83			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
84			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
85			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
86			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
87			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
88		>;
89	};
90
91	mdio_pins: pinmux_mdio {
92		pinctrl-single,pins = <
93			/* MDIO */
94			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
95			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
96		>;
97	};
98};
99
100&cpsw_emac0 {
101	phy-handle = <&phy0>;
102	phy-mode = "rmii";
103	dual_emac_res_vlan = <1>;
104};
105
106&davinci_mdio {
107	pinctrl-names = "default";
108	pinctrl-0 = <&mdio_pins>;
109	status = "okay";
110
111	phy0: ethernet-phy@0 {
112		reg = <0>;
113	};
114};
115
116&mac {
117	slaves = <1>;
118	pinctrl-names = "default";
119	pinctrl-0 = <&ethernet0_pins>;
120	status = "okay";
121};
122
123/* I2C Busses */
124&am33xx_pinmux {
125	i2c0_pins: pinmux_i2c0 {
126		pinctrl-single,pins = <
127			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
128			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
129		>;
130	};
131};
132
133&i2c0 {
134	pinctrl-names = "default";
135	pinctrl-0 = <&i2c0_pins>;
136	clock-frequency = <400000>;
137	status = "okay";
138
139	tps: pmic@2d {
140		reg = <0x2d>;
141	};
142
143	i2c_tmp102: temp@4b {
144		compatible = "ti,tmp102";
145		reg = <0x4b>;
146		status = "disabled";
147	};
148
149	i2c_eeprom: eeprom@52 {
150		compatible = "atmel,24c32";
151		pagesize = <32>;
152		reg = <0x52>;
153		status = "disabled";
154	};
155
156	i2c_rtc: rtc@68 {
157		compatible = "microcrystal,rv4162";
158		reg = <0x68>;
159		status = "disabled";
160	};
161};
162
163/* NAND memory */
164&am33xx_pinmux {
165		nandflash_pins: pinmux_nandflash {
166			pinctrl-single,pins = <
167			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
168			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
169			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
170			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
171			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
172			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
173			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
174			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
175			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
176			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
177			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
178			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
179			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
180			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
181		>;
182	};
183};
184
185&elm {
186	status = "okay";
187};
188
189&gpmc {
190	status = "disabled";
191	pinctrl-names = "default";
192	pinctrl-0 = <&nandflash_pins>;
193	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
194	nandflash: nand@0,0 {
195		compatible = "ti,omap2-nand";
196		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
197		interrupt-parent = <&gpmc>;
198		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
199			     <1 IRQ_TYPE_NONE>;	/* termcount */
200		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
201		nand-bus-width = <8>;
202		ti,nand-ecc-opt = "bch8";
203		gpmc,device-nand = "true";
204		gpmc,device-width = <1>;
205		gpmc,sync-clk-ps = <0>;
206		gpmc,cs-on-ns = <0>;
207		gpmc,cs-rd-off-ns = <30>;
208		gpmc,cs-wr-off-ns = <30>;
209		gpmc,adv-on-ns = <0>;
210		gpmc,adv-rd-off-ns = <30>;
211		gpmc,adv-wr-off-ns = <30>;
212		gpmc,we-on-ns = <0>;
213		gpmc,we-off-ns = <20>;
214		gpmc,oe-on-ns = <10>;
215		gpmc,oe-off-ns = <30>;
216		gpmc,access-ns = <30>;
217		gpmc,rd-cycle-ns = <30>;
218		gpmc,wr-cycle-ns = <30>;
219		gpmc,bus-turnaround-ns = <0>;
220		gpmc,cycle2cycle-delay-ns = <50>;
221		gpmc,cycle2cycle-diffcsen;
222		gpmc,clk-activation-ns = <0>;
223		gpmc,wr-access-ns = <30>;
224		gpmc,wr-data-mux-bus-ns = <0>;
225
226		ti,elm-id = <&elm>;
227
228		#address-cells = <1>;
229		#size-cells = <1>;
230	};
231};
232
233/* Power */
234#include "tps65910.dtsi"
235
236&tps {
237	vcc1-supply = <&vcc5v>;
238	vcc2-supply = <&vcc5v>;
239	vcc3-supply = <&vcc5v>;
240	vcc4-supply = <&vcc5v>;
241	vcc5-supply = <&vcc5v>;
242	vcc6-supply = <&vcc5v>;
243	vcc7-supply = <&vcc5v>;
244	vccio-supply = <&vcc5v>;
245
246	regulators {
247		vrtc_reg: regulator@0 {
248			regulator-always-on;
249		};
250
251		vio_reg: regulator@1 {
252			regulator-always-on;
253		};
254
255		vdd1_reg: regulator@2 {
256			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
257			regulator-name = "vdd_mpu";
258			regulator-min-microvolt = <912500>;
259			regulator-max-microvolt = <1378000>;
260			regulator-boot-on;
261			regulator-always-on;
262		};
263
264		vdd2_reg: regulator@3 {
265			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
266			regulator-name = "vdd_core";
267			regulator-min-microvolt = <912500>;
268			regulator-max-microvolt = <1150000>;
269			regulator-boot-on;
270			regulator-always-on;
271		};
272
273		vdd3_reg: regulator@4 {
274			regulator-always-on;
275		};
276
277		vdig1_reg: regulator@5 {
278			regulator-name = "vdig1_1p8v";
279			regulator-min-microvolt = <1800000>;
280			regulator-max-microvolt = <1800000>;
281		};
282
283		vdig2_reg: regulator@6 {
284			regulator-always-on;
285		};
286
287		vpll_reg: regulator@7 {
288			regulator-always-on;
289		};
290
291		vdac_reg: regulator@8 {
292			regulator-always-on;
293		};
294
295		vaux1_reg: regulator@9 {
296			regulator-always-on;
297		};
298
299		vaux2_reg: regulator@10 {
300			regulator-always-on;
301		};
302
303		vaux33_reg: regulator@11 {
304			regulator-always-on;
305		};
306
307		vmmc_reg: regulator@12 {
308			regulator-min-microvolt = <3300000>;
309			regulator-max-microvolt = <3300000>;
310			regulator-always-on;
311		};
312	};
313};
314
315/* SPI Busses */
316&am33xx_pinmux {
317	spi0_pins: pinmux_spi0 {
318		pinctrl-single,pins = <
319			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
320			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
321			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
322			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
323		>;
324	};
325};
326
327&spi0 {
328	pinctrl-names = "default";
329	pinctrl-0 = <&spi0_pins>;
330	status = "okay";
331
332	serial_flash: m25p80@0 {
333		compatible = "jedec,spi-nor";
334		spi-max-frequency = <48000000>;
335		reg = <0x0>;
336		m25p,fast-read;
337		status = "disabled";
338		#address-cells = <1>;
339		#size-cells = <1>;
340	};
341};
342