1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2500"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm1176jzf-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 memory@80000000 { 46 device_type = "memory"; 47 reg = <0x80000000 0>; 48 }; 49 50 edac: sdram@1e6e0000 { 51 compatible = "aspeed,ast2500-sdram-edac"; 52 reg = <0x1e6e0000 0x174>; 53 interrupts = <0>; 54 status = "disabled"; 55 }; 56 57 ahb { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 fmc: spi@1e620000 { 64 reg = < 0x1e620000 0xc4 65 0x20000000 0x10000000 >; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 compatible = "aspeed,ast2500-fmc"; 69 clocks = <&syscon ASPEED_CLK_AHB>; 70 status = "disabled"; 71 interrupts = <19>; 72 flash@0 { 73 reg = < 0 >; 74 compatible = "jedec,spi-nor"; 75 status = "disabled"; 76 }; 77 flash@1 { 78 reg = < 1 >; 79 compatible = "jedec,spi-nor"; 80 status = "disabled"; 81 }; 82 flash@2 { 83 reg = < 2 >; 84 compatible = "jedec,spi-nor"; 85 status = "disabled"; 86 }; 87 }; 88 89 spi1: spi@1e630000 { 90 reg = < 0x1e630000 0xc4 91 0x30000000 0x08000000 >; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 compatible = "aspeed,ast2500-spi"; 95 clocks = <&syscon ASPEED_CLK_AHB>; 96 status = "disabled"; 97 flash@0 { 98 reg = < 0 >; 99 compatible = "jedec,spi-nor"; 100 status = "disabled"; 101 }; 102 flash@1 { 103 reg = < 1 >; 104 compatible = "jedec,spi-nor"; 105 status = "disabled"; 106 }; 107 }; 108 109 spi2: spi@1e631000 { 110 reg = < 0x1e631000 0xc4 111 0x38000000 0x08000000 >; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 compatible = "aspeed,ast2500-spi"; 115 clocks = <&syscon ASPEED_CLK_AHB>; 116 status = "disabled"; 117 flash@0 { 118 reg = < 0 >; 119 compatible = "jedec,spi-nor"; 120 status = "disabled"; 121 }; 122 flash@1 { 123 reg = < 1 >; 124 compatible = "jedec,spi-nor"; 125 status = "disabled"; 126 }; 127 }; 128 129 vic: interrupt-controller@1e6c0080 { 130 compatible = "aspeed,ast2400-vic"; 131 interrupt-controller; 132 #interrupt-cells = <1>; 133 valid-sources = <0xfefff7ff 0x0807ffff>; 134 reg = <0x1e6c0080 0x80>; 135 }; 136 137 cvic: copro-interrupt-controller@1e6c2000 { 138 compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; 139 valid-sources = <0xffffffff>; 140 copro-sw-interrupts = <1>; 141 reg = <0x1e6c2000 0x80>; 142 }; 143 144 mac0: ethernet@1e660000 { 145 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 146 reg = <0x1e660000 0x180>; 147 interrupts = <2>; 148 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 149 status = "disabled"; 150 }; 151 152 mac1: ethernet@1e680000 { 153 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 154 reg = <0x1e680000 0x180>; 155 interrupts = <3>; 156 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 157 status = "disabled"; 158 }; 159 160 ehci0: usb@1e6a1000 { 161 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 162 reg = <0x1e6a1000 0x100>; 163 interrupts = <5>; 164 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_usb2ah_default>; 167 status = "disabled"; 168 }; 169 170 ehci1: usb@1e6a3000 { 171 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 172 reg = <0x1e6a3000 0x100>; 173 interrupts = <13>; 174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_usb2bh_default>; 177 status = "disabled"; 178 }; 179 180 uhci: usb@1e6b0000 { 181 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 182 reg = <0x1e6b0000 0x100>; 183 interrupts = <14>; 184 #ports = <2>; 185 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 186 status = "disabled"; 187 /* 188 * No default pinmux, it will follow EHCI, use an explicit pinmux 189 * override if you don't enable EHCI 190 */ 191 }; 192 193 vhub: usb-vhub@1e6a0000 { 194 compatible = "aspeed,ast2500-usb-vhub"; 195 reg = <0x1e6a0000 0x300>; 196 interrupts = <5>; 197 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_usb2ad_default>; 200 status = "disabled"; 201 }; 202 203 apb { 204 compatible = "simple-bus"; 205 #address-cells = <1>; 206 #size-cells = <1>; 207 ranges; 208 209 syscon: syscon@1e6e2000 { 210 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 211 reg = <0x1e6e2000 0x1a8>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 #clock-cells = <1>; 215 #reset-cells = <1>; 216 217 pinctrl: pinctrl { 218 compatible = "aspeed,g5-pinctrl"; 219 aspeed,external-nodes = <&gfx &lhc>; 220 221 }; 222 223 p2a: p2a-control { 224 compatible = "aspeed,ast2500-p2a-ctrl"; 225 status = "disabled"; 226 }; 227 }; 228 229 rng: hwrng@1e6e2078 { 230 compatible = "timeriomem_rng"; 231 reg = <0x1e6e2078 0x4>; 232 period = <1>; 233 quality = <100>; 234 }; 235 236 gfx: display@1e6e6000 { 237 compatible = "aspeed,ast2500-gfx", "syscon"; 238 reg = <0x1e6e6000 0x1000>; 239 reg-io-width = <4>; 240 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 241 resets = <&syscon ASPEED_RESET_CRT1>; 242 status = "disabled"; 243 interrupts = <0x19>; 244 }; 245 246 adc: adc@1e6e9000 { 247 compatible = "aspeed,ast2500-adc"; 248 reg = <0x1e6e9000 0xb0>; 249 clocks = <&syscon ASPEED_CLK_APB>; 250 resets = <&syscon ASPEED_RESET_ADC>; 251 #io-channel-cells = <1>; 252 status = "disabled"; 253 }; 254 255 video: video@1e700000 { 256 compatible = "aspeed,ast2500-video-engine"; 257 reg = <0x1e700000 0x1000>; 258 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 259 <&syscon ASPEED_CLK_GATE_ECLK>; 260 clock-names = "vclk", "eclk"; 261 interrupts = <7>; 262 status = "disabled"; 263 }; 264 265 sram: sram@1e720000 { 266 compatible = "mmio-sram"; 267 reg = <0x1e720000 0x9000>; // 36K 268 }; 269 270 sdmmc: sd-controller@1e740000 { 271 compatible = "aspeed,ast2500-sd-controller"; 272 reg = <0x1e740000 0x100>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 ranges = <0 0x1e740000 0x10000>; 276 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 277 status = "disabled"; 278 279 sdhci0: sdhci@100 { 280 compatible = "aspeed,ast2500-sdhci"; 281 reg = <0x100 0x100>; 282 interrupts = <26>; 283 sdhci,auto-cmd12; 284 clocks = <&syscon ASPEED_CLK_SDIO>; 285 status = "disabled"; 286 }; 287 288 sdhci1: sdhci@200 { 289 compatible = "aspeed,ast2500-sdhci"; 290 reg = <0x200 0x100>; 291 interrupts = <26>; 292 sdhci,auto-cmd12; 293 clocks = <&syscon ASPEED_CLK_SDIO>; 294 status = "disabled"; 295 }; 296 }; 297 298 gpio: gpio@1e780000 { 299 #gpio-cells = <2>; 300 gpio-controller; 301 compatible = "aspeed,ast2500-gpio"; 302 reg = <0x1e780000 0x1000>; 303 interrupts = <20>; 304 gpio-ranges = <&pinctrl 0 0 232>; 305 clocks = <&syscon ASPEED_CLK_APB>; 306 interrupt-controller; 307 #interrupt-cells = <2>; 308 }; 309 310 rtc: rtc@1e781000 { 311 compatible = "aspeed,ast2500-rtc"; 312 reg = <0x1e781000 0x18>; 313 status = "disabled"; 314 }; 315 316 timer: timer@1e782000 { 317 /* This timer is a Faraday FTTMR010 derivative */ 318 compatible = "aspeed,ast2400-timer"; 319 reg = <0x1e782000 0x90>; 320 interrupts = <16 17 18 35 36 37 38 39>; 321 clocks = <&syscon ASPEED_CLK_APB>; 322 clock-names = "PCLK"; 323 }; 324 325 uart1: serial@1e783000 { 326 compatible = "ns16550a"; 327 reg = <0x1e783000 0x20>; 328 reg-shift = <2>; 329 interrupts = <9>; 330 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 331 resets = <&lpc_reset 4>; 332 no-loopback-test; 333 status = "disabled"; 334 }; 335 336 uart5: serial@1e784000 { 337 compatible = "ns16550a"; 338 reg = <0x1e784000 0x20>; 339 reg-shift = <2>; 340 interrupts = <10>; 341 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 342 no-loopback-test; 343 status = "disabled"; 344 }; 345 346 wdt1: watchdog@1e785000 { 347 compatible = "aspeed,ast2500-wdt"; 348 reg = <0x1e785000 0x20>; 349 clocks = <&syscon ASPEED_CLK_APB>; 350 }; 351 352 wdt2: watchdog@1e785020 { 353 compatible = "aspeed,ast2500-wdt"; 354 reg = <0x1e785020 0x20>; 355 clocks = <&syscon ASPEED_CLK_APB>; 356 }; 357 358 wdt3: watchdog@1e785040 { 359 compatible = "aspeed,ast2500-wdt"; 360 reg = <0x1e785040 0x20>; 361 clocks = <&syscon ASPEED_CLK_APB>; 362 status = "disabled"; 363 }; 364 365 pwm_tacho: pwm-tacho-controller@1e786000 { 366 compatible = "aspeed,ast2500-pwm-tacho"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0x1e786000 0x1000>; 370 clocks = <&syscon ASPEED_CLK_24M>; 371 resets = <&syscon ASPEED_RESET_PWM>; 372 status = "disabled"; 373 }; 374 375 vuart: serial@1e787000 { 376 compatible = "aspeed,ast2500-vuart"; 377 reg = <0x1e787000 0x40>; 378 reg-shift = <2>; 379 interrupts = <8>; 380 clocks = <&syscon ASPEED_CLK_APB>; 381 no-loopback-test; 382 status = "disabled"; 383 }; 384 385 lpc: lpc@1e789000 { 386 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 387 reg = <0x1e789000 0x1000>; 388 389 #address-cells = <1>; 390 #size-cells = <1>; 391 ranges = <0x0 0x1e789000 0x1000>; 392 393 lpc_bmc: lpc-bmc@0 { 394 compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; 395 reg = <0x0 0x80>; 396 reg-io-width = <4>; 397 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0x0 0x0 0x80>; 401 402 kcs1: kcs1@0 { 403 compatible = "aspeed,ast2500-kcs-bmc"; 404 interrupts = <8>; 405 kcs_chan = <1>; 406 status = "disabled"; 407 }; 408 kcs2: kcs2@0 { 409 compatible = "aspeed,ast2500-kcs-bmc"; 410 interrupts = <8>; 411 kcs_chan = <2>; 412 status = "disabled"; 413 }; 414 kcs3: kcs3@0 { 415 compatible = "aspeed,ast2500-kcs-bmc"; 416 interrupts = <8>; 417 kcs_chan = <3>; 418 status = "disabled"; 419 }; 420 }; 421 422 lpc_host: lpc-host@80 { 423 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 424 reg = <0x80 0x1e0>; 425 reg-io-width = <4>; 426 427 #address-cells = <1>; 428 #size-cells = <1>; 429 ranges = <0x0 0x80 0x1e0>; 430 431 kcs4: kcs4@0 { 432 compatible = "aspeed,ast2500-kcs-bmc"; 433 interrupts = <8>; 434 kcs_chan = <4>; 435 status = "disabled"; 436 }; 437 438 lpc_ctrl: lpc-ctrl@0 { 439 compatible = "aspeed,ast2500-lpc-ctrl"; 440 reg = <0x0 0x80>; 441 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 442 status = "disabled"; 443 }; 444 445 lpc_snoop: lpc-snoop@0 { 446 compatible = "aspeed,ast2500-lpc-snoop"; 447 reg = <0x0 0x80>; 448 interrupts = <8>; 449 status = "disabled"; 450 }; 451 452 lhc: lhc@20 { 453 compatible = "aspeed,ast2500-lhc"; 454 reg = <0x20 0x24 0x48 0x8>; 455 }; 456 457 lpc_reset: reset-controller@18 { 458 compatible = "aspeed,ast2500-lpc-reset"; 459 reg = <0x18 0x4>; 460 #reset-cells = <1>; 461 }; 462 463 ibt: ibt@c0 { 464 compatible = "aspeed,ast2500-ibt-bmc"; 465 reg = <0xc0 0x18>; 466 interrupts = <8>; 467 status = "disabled"; 468 }; 469 }; 470 }; 471 472 uart2: serial@1e78d000 { 473 compatible = "ns16550a"; 474 reg = <0x1e78d000 0x20>; 475 reg-shift = <2>; 476 interrupts = <32>; 477 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 478 resets = <&lpc_reset 5>; 479 no-loopback-test; 480 status = "disabled"; 481 }; 482 483 uart3: serial@1e78e000 { 484 compatible = "ns16550a"; 485 reg = <0x1e78e000 0x20>; 486 reg-shift = <2>; 487 interrupts = <33>; 488 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 489 resets = <&lpc_reset 6>; 490 no-loopback-test; 491 status = "disabled"; 492 }; 493 494 uart4: serial@1e78f000 { 495 compatible = "ns16550a"; 496 reg = <0x1e78f000 0x20>; 497 reg-shift = <2>; 498 interrupts = <34>; 499 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 500 resets = <&lpc_reset 7>; 501 no-loopback-test; 502 status = "disabled"; 503 }; 504 505 i2c: bus@1e78a000 { 506 compatible = "simple-bus"; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 ranges = <0 0x1e78a000 0x1000>; 510 }; 511 }; 512 }; 513}; 514 515&i2c { 516 i2c_ic: interrupt-controller@0 { 517 #interrupt-cells = <1>; 518 compatible = "aspeed,ast2500-i2c-ic"; 519 reg = <0x0 0x40>; 520 interrupts = <12>; 521 interrupt-controller; 522 }; 523 524 i2c0: i2c-bus@40 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 #interrupt-cells = <1>; 528 529 reg = <0x40 0x40>; 530 compatible = "aspeed,ast2500-i2c-bus"; 531 clocks = <&syscon ASPEED_CLK_APB>; 532 resets = <&syscon ASPEED_RESET_I2C>; 533 bus-frequency = <100000>; 534 interrupts = <0>; 535 interrupt-parent = <&i2c_ic>; 536 status = "disabled"; 537 /* Does not need pinctrl properties */ 538 }; 539 540 i2c1: i2c-bus@80 { 541 #address-cells = <1>; 542 #size-cells = <0>; 543 #interrupt-cells = <1>; 544 545 reg = <0x80 0x40>; 546 compatible = "aspeed,ast2500-i2c-bus"; 547 clocks = <&syscon ASPEED_CLK_APB>; 548 resets = <&syscon ASPEED_RESET_I2C>; 549 bus-frequency = <100000>; 550 interrupts = <1>; 551 interrupt-parent = <&i2c_ic>; 552 status = "disabled"; 553 /* Does not need pinctrl properties */ 554 }; 555 556 i2c2: i2c-bus@c0 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 #interrupt-cells = <1>; 560 561 reg = <0xc0 0x40>; 562 compatible = "aspeed,ast2500-i2c-bus"; 563 clocks = <&syscon ASPEED_CLK_APB>; 564 resets = <&syscon ASPEED_RESET_I2C>; 565 bus-frequency = <100000>; 566 interrupts = <2>; 567 interrupt-parent = <&i2c_ic>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_i2c3_default>; 570 status = "disabled"; 571 }; 572 573 i2c3: i2c-bus@100 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 #interrupt-cells = <1>; 577 578 reg = <0x100 0x40>; 579 compatible = "aspeed,ast2500-i2c-bus"; 580 clocks = <&syscon ASPEED_CLK_APB>; 581 resets = <&syscon ASPEED_RESET_I2C>; 582 bus-frequency = <100000>; 583 interrupts = <3>; 584 interrupt-parent = <&i2c_ic>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_i2c4_default>; 587 status = "disabled"; 588 }; 589 590 i2c4: i2c-bus@140 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 #interrupt-cells = <1>; 594 595 reg = <0x140 0x40>; 596 compatible = "aspeed,ast2500-i2c-bus"; 597 clocks = <&syscon ASPEED_CLK_APB>; 598 resets = <&syscon ASPEED_RESET_I2C>; 599 bus-frequency = <100000>; 600 interrupts = <4>; 601 interrupt-parent = <&i2c_ic>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_i2c5_default>; 604 status = "disabled"; 605 }; 606 607 i2c5: i2c-bus@180 { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 #interrupt-cells = <1>; 611 612 reg = <0x180 0x40>; 613 compatible = "aspeed,ast2500-i2c-bus"; 614 clocks = <&syscon ASPEED_CLK_APB>; 615 resets = <&syscon ASPEED_RESET_I2C>; 616 bus-frequency = <100000>; 617 interrupts = <5>; 618 interrupt-parent = <&i2c_ic>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_i2c6_default>; 621 status = "disabled"; 622 }; 623 624 i2c6: i2c-bus@1c0 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 #interrupt-cells = <1>; 628 629 reg = <0x1c0 0x40>; 630 compatible = "aspeed,ast2500-i2c-bus"; 631 clocks = <&syscon ASPEED_CLK_APB>; 632 resets = <&syscon ASPEED_RESET_I2C>; 633 bus-frequency = <100000>; 634 interrupts = <6>; 635 interrupt-parent = <&i2c_ic>; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_i2c7_default>; 638 status = "disabled"; 639 }; 640 641 i2c7: i2c-bus@300 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 #interrupt-cells = <1>; 645 646 reg = <0x300 0x40>; 647 compatible = "aspeed,ast2500-i2c-bus"; 648 clocks = <&syscon ASPEED_CLK_APB>; 649 resets = <&syscon ASPEED_RESET_I2C>; 650 bus-frequency = <100000>; 651 interrupts = <7>; 652 interrupt-parent = <&i2c_ic>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_i2c8_default>; 655 status = "disabled"; 656 }; 657 658 i2c8: i2c-bus@340 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 #interrupt-cells = <1>; 662 663 reg = <0x340 0x40>; 664 compatible = "aspeed,ast2500-i2c-bus"; 665 clocks = <&syscon ASPEED_CLK_APB>; 666 resets = <&syscon ASPEED_RESET_I2C>; 667 bus-frequency = <100000>; 668 interrupts = <8>; 669 interrupt-parent = <&i2c_ic>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pinctrl_i2c9_default>; 672 status = "disabled"; 673 }; 674 675 i2c9: i2c-bus@380 { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 #interrupt-cells = <1>; 679 680 reg = <0x380 0x40>; 681 compatible = "aspeed,ast2500-i2c-bus"; 682 clocks = <&syscon ASPEED_CLK_APB>; 683 resets = <&syscon ASPEED_RESET_I2C>; 684 bus-frequency = <100000>; 685 interrupts = <9>; 686 interrupt-parent = <&i2c_ic>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&pinctrl_i2c10_default>; 689 status = "disabled"; 690 }; 691 692 i2c10: i2c-bus@3c0 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 #interrupt-cells = <1>; 696 697 reg = <0x3c0 0x40>; 698 compatible = "aspeed,ast2500-i2c-bus"; 699 clocks = <&syscon ASPEED_CLK_APB>; 700 resets = <&syscon ASPEED_RESET_I2C>; 701 bus-frequency = <100000>; 702 interrupts = <10>; 703 interrupt-parent = <&i2c_ic>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&pinctrl_i2c11_default>; 706 status = "disabled"; 707 }; 708 709 i2c11: i2c-bus@400 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 #interrupt-cells = <1>; 713 714 reg = <0x400 0x40>; 715 compatible = "aspeed,ast2500-i2c-bus"; 716 clocks = <&syscon ASPEED_CLK_APB>; 717 resets = <&syscon ASPEED_RESET_I2C>; 718 bus-frequency = <100000>; 719 interrupts = <11>; 720 interrupt-parent = <&i2c_ic>; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pinctrl_i2c12_default>; 723 status = "disabled"; 724 }; 725 726 i2c12: i2c-bus@440 { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 #interrupt-cells = <1>; 730 731 reg = <0x440 0x40>; 732 compatible = "aspeed,ast2500-i2c-bus"; 733 clocks = <&syscon ASPEED_CLK_APB>; 734 resets = <&syscon ASPEED_RESET_I2C>; 735 bus-frequency = <100000>; 736 interrupts = <12>; 737 interrupt-parent = <&i2c_ic>; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pinctrl_i2c13_default>; 740 status = "disabled"; 741 }; 742 743 i2c13: i2c-bus@480 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 #interrupt-cells = <1>; 747 748 reg = <0x480 0x40>; 749 compatible = "aspeed,ast2500-i2c-bus"; 750 clocks = <&syscon ASPEED_CLK_APB>; 751 resets = <&syscon ASPEED_RESET_I2C>; 752 bus-frequency = <100000>; 753 interrupts = <13>; 754 interrupt-parent = <&i2c_ic>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&pinctrl_i2c14_default>; 757 status = "disabled"; 758 }; 759}; 760 761&pinctrl { 762 pinctrl_acpi_default: acpi_default { 763 function = "ACPI"; 764 groups = "ACPI"; 765 }; 766 767 pinctrl_adc0_default: adc0_default { 768 function = "ADC0"; 769 groups = "ADC0"; 770 }; 771 772 pinctrl_adc1_default: adc1_default { 773 function = "ADC1"; 774 groups = "ADC1"; 775 }; 776 777 pinctrl_adc10_default: adc10_default { 778 function = "ADC10"; 779 groups = "ADC10"; 780 }; 781 782 pinctrl_adc11_default: adc11_default { 783 function = "ADC11"; 784 groups = "ADC11"; 785 }; 786 787 pinctrl_adc12_default: adc12_default { 788 function = "ADC12"; 789 groups = "ADC12"; 790 }; 791 792 pinctrl_adc13_default: adc13_default { 793 function = "ADC13"; 794 groups = "ADC13"; 795 }; 796 797 pinctrl_adc14_default: adc14_default { 798 function = "ADC14"; 799 groups = "ADC14"; 800 }; 801 802 pinctrl_adc15_default: adc15_default { 803 function = "ADC15"; 804 groups = "ADC15"; 805 }; 806 807 pinctrl_adc2_default: adc2_default { 808 function = "ADC2"; 809 groups = "ADC2"; 810 }; 811 812 pinctrl_adc3_default: adc3_default { 813 function = "ADC3"; 814 groups = "ADC3"; 815 }; 816 817 pinctrl_adc4_default: adc4_default { 818 function = "ADC4"; 819 groups = "ADC4"; 820 }; 821 822 pinctrl_adc5_default: adc5_default { 823 function = "ADC5"; 824 groups = "ADC5"; 825 }; 826 827 pinctrl_adc6_default: adc6_default { 828 function = "ADC6"; 829 groups = "ADC6"; 830 }; 831 832 pinctrl_adc7_default: adc7_default { 833 function = "ADC7"; 834 groups = "ADC7"; 835 }; 836 837 pinctrl_adc8_default: adc8_default { 838 function = "ADC8"; 839 groups = "ADC8"; 840 }; 841 842 pinctrl_adc9_default: adc9_default { 843 function = "ADC9"; 844 groups = "ADC9"; 845 }; 846 847 pinctrl_bmcint_default: bmcint_default { 848 function = "BMCINT"; 849 groups = "BMCINT"; 850 }; 851 852 pinctrl_ddcclk_default: ddcclk_default { 853 function = "DDCCLK"; 854 groups = "DDCCLK"; 855 }; 856 857 pinctrl_ddcdat_default: ddcdat_default { 858 function = "DDCDAT"; 859 groups = "DDCDAT"; 860 }; 861 862 pinctrl_espi_default: espi_default { 863 function = "ESPI"; 864 groups = "ESPI"; 865 }; 866 867 pinctrl_fwspics1_default: fwspics1_default { 868 function = "FWSPICS1"; 869 groups = "FWSPICS1"; 870 }; 871 872 pinctrl_fwspics2_default: fwspics2_default { 873 function = "FWSPICS2"; 874 groups = "FWSPICS2"; 875 }; 876 877 pinctrl_gpid0_default: gpid0_default { 878 function = "GPID0"; 879 groups = "GPID0"; 880 }; 881 882 pinctrl_gpid2_default: gpid2_default { 883 function = "GPID2"; 884 groups = "GPID2"; 885 }; 886 887 pinctrl_gpid4_default: gpid4_default { 888 function = "GPID4"; 889 groups = "GPID4"; 890 }; 891 892 pinctrl_gpid6_default: gpid6_default { 893 function = "GPID6"; 894 groups = "GPID6"; 895 }; 896 897 pinctrl_gpie0_default: gpie0_default { 898 function = "GPIE0"; 899 groups = "GPIE0"; 900 }; 901 902 pinctrl_gpie2_default: gpie2_default { 903 function = "GPIE2"; 904 groups = "GPIE2"; 905 }; 906 907 pinctrl_gpie4_default: gpie4_default { 908 function = "GPIE4"; 909 groups = "GPIE4"; 910 }; 911 912 pinctrl_gpie6_default: gpie6_default { 913 function = "GPIE6"; 914 groups = "GPIE6"; 915 }; 916 917 pinctrl_i2c10_default: i2c10_default { 918 function = "I2C10"; 919 groups = "I2C10"; 920 }; 921 922 pinctrl_i2c11_default: i2c11_default { 923 function = "I2C11"; 924 groups = "I2C11"; 925 }; 926 927 pinctrl_i2c12_default: i2c12_default { 928 function = "I2C12"; 929 groups = "I2C12"; 930 }; 931 932 pinctrl_i2c13_default: i2c13_default { 933 function = "I2C13"; 934 groups = "I2C13"; 935 }; 936 937 pinctrl_i2c14_default: i2c14_default { 938 function = "I2C14"; 939 groups = "I2C14"; 940 }; 941 942 pinctrl_i2c3_default: i2c3_default { 943 function = "I2C3"; 944 groups = "I2C3"; 945 }; 946 947 pinctrl_i2c4_default: i2c4_default { 948 function = "I2C4"; 949 groups = "I2C4"; 950 }; 951 952 pinctrl_i2c5_default: i2c5_default { 953 function = "I2C5"; 954 groups = "I2C5"; 955 }; 956 957 pinctrl_i2c6_default: i2c6_default { 958 function = "I2C6"; 959 groups = "I2C6"; 960 }; 961 962 pinctrl_i2c7_default: i2c7_default { 963 function = "I2C7"; 964 groups = "I2C7"; 965 }; 966 967 pinctrl_i2c8_default: i2c8_default { 968 function = "I2C8"; 969 groups = "I2C8"; 970 }; 971 972 pinctrl_i2c9_default: i2c9_default { 973 function = "I2C9"; 974 groups = "I2C9"; 975 }; 976 977 pinctrl_lad0_default: lad0_default { 978 function = "LAD0"; 979 groups = "LAD0"; 980 }; 981 982 pinctrl_lad1_default: lad1_default { 983 function = "LAD1"; 984 groups = "LAD1"; 985 }; 986 987 pinctrl_lad2_default: lad2_default { 988 function = "LAD2"; 989 groups = "LAD2"; 990 }; 991 992 pinctrl_lad3_default: lad3_default { 993 function = "LAD3"; 994 groups = "LAD3"; 995 }; 996 997 pinctrl_lclk_default: lclk_default { 998 function = "LCLK"; 999 groups = "LCLK"; 1000 }; 1001 1002 pinctrl_lframe_default: lframe_default { 1003 function = "LFRAME"; 1004 groups = "LFRAME"; 1005 }; 1006 1007 pinctrl_lpchc_default: lpchc_default { 1008 function = "LPCHC"; 1009 groups = "LPCHC"; 1010 }; 1011 1012 pinctrl_lpcpd_default: lpcpd_default { 1013 function = "LPCPD"; 1014 groups = "LPCPD"; 1015 }; 1016 1017 pinctrl_lpcplus_default: lpcplus_default { 1018 function = "LPCPLUS"; 1019 groups = "LPCPLUS"; 1020 }; 1021 1022 pinctrl_lpcpme_default: lpcpme_default { 1023 function = "LPCPME"; 1024 groups = "LPCPME"; 1025 }; 1026 1027 pinctrl_lpcrst_default: lpcrst_default { 1028 function = "LPCRST"; 1029 groups = "LPCRST"; 1030 }; 1031 1032 pinctrl_lpcsmi_default: lpcsmi_default { 1033 function = "LPCSMI"; 1034 groups = "LPCSMI"; 1035 }; 1036 1037 pinctrl_lsirq_default: lsirq_default { 1038 function = "LSIRQ"; 1039 groups = "LSIRQ"; 1040 }; 1041 1042 pinctrl_mac1link_default: mac1link_default { 1043 function = "MAC1LINK"; 1044 groups = "MAC1LINK"; 1045 }; 1046 1047 pinctrl_mac2link_default: mac2link_default { 1048 function = "MAC2LINK"; 1049 groups = "MAC2LINK"; 1050 }; 1051 1052 pinctrl_mdio1_default: mdio1_default { 1053 function = "MDIO1"; 1054 groups = "MDIO1"; 1055 }; 1056 1057 pinctrl_mdio2_default: mdio2_default { 1058 function = "MDIO2"; 1059 groups = "MDIO2"; 1060 }; 1061 1062 pinctrl_ncts1_default: ncts1_default { 1063 function = "NCTS1"; 1064 groups = "NCTS1"; 1065 }; 1066 1067 pinctrl_ncts2_default: ncts2_default { 1068 function = "NCTS2"; 1069 groups = "NCTS2"; 1070 }; 1071 1072 pinctrl_ncts3_default: ncts3_default { 1073 function = "NCTS3"; 1074 groups = "NCTS3"; 1075 }; 1076 1077 pinctrl_ncts4_default: ncts4_default { 1078 function = "NCTS4"; 1079 groups = "NCTS4"; 1080 }; 1081 1082 pinctrl_ndcd1_default: ndcd1_default { 1083 function = "NDCD1"; 1084 groups = "NDCD1"; 1085 }; 1086 1087 pinctrl_ndcd2_default: ndcd2_default { 1088 function = "NDCD2"; 1089 groups = "NDCD2"; 1090 }; 1091 1092 pinctrl_ndcd3_default: ndcd3_default { 1093 function = "NDCD3"; 1094 groups = "NDCD3"; 1095 }; 1096 1097 pinctrl_ndcd4_default: ndcd4_default { 1098 function = "NDCD4"; 1099 groups = "NDCD4"; 1100 }; 1101 1102 pinctrl_ndsr1_default: ndsr1_default { 1103 function = "NDSR1"; 1104 groups = "NDSR1"; 1105 }; 1106 1107 pinctrl_ndsr2_default: ndsr2_default { 1108 function = "NDSR2"; 1109 groups = "NDSR2"; 1110 }; 1111 1112 pinctrl_ndsr3_default: ndsr3_default { 1113 function = "NDSR3"; 1114 groups = "NDSR3"; 1115 }; 1116 1117 pinctrl_ndsr4_default: ndsr4_default { 1118 function = "NDSR4"; 1119 groups = "NDSR4"; 1120 }; 1121 1122 pinctrl_ndtr1_default: ndtr1_default { 1123 function = "NDTR1"; 1124 groups = "NDTR1"; 1125 }; 1126 1127 pinctrl_ndtr2_default: ndtr2_default { 1128 function = "NDTR2"; 1129 groups = "NDTR2"; 1130 }; 1131 1132 pinctrl_ndtr3_default: ndtr3_default { 1133 function = "NDTR3"; 1134 groups = "NDTR3"; 1135 }; 1136 1137 pinctrl_ndtr4_default: ndtr4_default { 1138 function = "NDTR4"; 1139 groups = "NDTR4"; 1140 }; 1141 1142 pinctrl_nri1_default: nri1_default { 1143 function = "NRI1"; 1144 groups = "NRI1"; 1145 }; 1146 1147 pinctrl_nri2_default: nri2_default { 1148 function = "NRI2"; 1149 groups = "NRI2"; 1150 }; 1151 1152 pinctrl_nri3_default: nri3_default { 1153 function = "NRI3"; 1154 groups = "NRI3"; 1155 }; 1156 1157 pinctrl_nri4_default: nri4_default { 1158 function = "NRI4"; 1159 groups = "NRI4"; 1160 }; 1161 1162 pinctrl_nrts1_default: nrts1_default { 1163 function = "NRTS1"; 1164 groups = "NRTS1"; 1165 }; 1166 1167 pinctrl_nrts2_default: nrts2_default { 1168 function = "NRTS2"; 1169 groups = "NRTS2"; 1170 }; 1171 1172 pinctrl_nrts3_default: nrts3_default { 1173 function = "NRTS3"; 1174 groups = "NRTS3"; 1175 }; 1176 1177 pinctrl_nrts4_default: nrts4_default { 1178 function = "NRTS4"; 1179 groups = "NRTS4"; 1180 }; 1181 1182 pinctrl_oscclk_default: oscclk_default { 1183 function = "OSCCLK"; 1184 groups = "OSCCLK"; 1185 }; 1186 1187 pinctrl_pewake_default: pewake_default { 1188 function = "PEWAKE"; 1189 groups = "PEWAKE"; 1190 }; 1191 1192 pinctrl_pnor_default: pnor_default { 1193 function = "PNOR"; 1194 groups = "PNOR"; 1195 }; 1196 1197 pinctrl_pwm0_default: pwm0_default { 1198 function = "PWM0"; 1199 groups = "PWM0"; 1200 }; 1201 1202 pinctrl_pwm1_default: pwm1_default { 1203 function = "PWM1"; 1204 groups = "PWM1"; 1205 }; 1206 1207 pinctrl_pwm2_default: pwm2_default { 1208 function = "PWM2"; 1209 groups = "PWM2"; 1210 }; 1211 1212 pinctrl_pwm3_default: pwm3_default { 1213 function = "PWM3"; 1214 groups = "PWM3"; 1215 }; 1216 1217 pinctrl_pwm4_default: pwm4_default { 1218 function = "PWM4"; 1219 groups = "PWM4"; 1220 }; 1221 1222 pinctrl_pwm5_default: pwm5_default { 1223 function = "PWM5"; 1224 groups = "PWM5"; 1225 }; 1226 1227 pinctrl_pwm6_default: pwm6_default { 1228 function = "PWM6"; 1229 groups = "PWM6"; 1230 }; 1231 1232 pinctrl_pwm7_default: pwm7_default { 1233 function = "PWM7"; 1234 groups = "PWM7"; 1235 }; 1236 1237 pinctrl_rgmii1_default: rgmii1_default { 1238 function = "RGMII1"; 1239 groups = "RGMII1"; 1240 }; 1241 1242 pinctrl_rgmii2_default: rgmii2_default { 1243 function = "RGMII2"; 1244 groups = "RGMII2"; 1245 }; 1246 1247 pinctrl_rmii1_default: rmii1_default { 1248 function = "RMII1"; 1249 groups = "RMII1"; 1250 }; 1251 1252 pinctrl_rmii2_default: rmii2_default { 1253 function = "RMII2"; 1254 groups = "RMII2"; 1255 }; 1256 1257 pinctrl_rxd1_default: rxd1_default { 1258 function = "RXD1"; 1259 groups = "RXD1"; 1260 }; 1261 1262 pinctrl_rxd2_default: rxd2_default { 1263 function = "RXD2"; 1264 groups = "RXD2"; 1265 }; 1266 1267 pinctrl_rxd3_default: rxd3_default { 1268 function = "RXD3"; 1269 groups = "RXD3"; 1270 }; 1271 1272 pinctrl_rxd4_default: rxd4_default { 1273 function = "RXD4"; 1274 groups = "RXD4"; 1275 }; 1276 1277 pinctrl_salt1_default: salt1_default { 1278 function = "SALT1"; 1279 groups = "SALT1"; 1280 }; 1281 1282 pinctrl_salt10_default: salt10_default { 1283 function = "SALT10"; 1284 groups = "SALT10"; 1285 }; 1286 1287 pinctrl_salt11_default: salt11_default { 1288 function = "SALT11"; 1289 groups = "SALT11"; 1290 }; 1291 1292 pinctrl_salt12_default: salt12_default { 1293 function = "SALT12"; 1294 groups = "SALT12"; 1295 }; 1296 1297 pinctrl_salt13_default: salt13_default { 1298 function = "SALT13"; 1299 groups = "SALT13"; 1300 }; 1301 1302 pinctrl_salt14_default: salt14_default { 1303 function = "SALT14"; 1304 groups = "SALT14"; 1305 }; 1306 1307 pinctrl_salt2_default: salt2_default { 1308 function = "SALT2"; 1309 groups = "SALT2"; 1310 }; 1311 1312 pinctrl_salt3_default: salt3_default { 1313 function = "SALT3"; 1314 groups = "SALT3"; 1315 }; 1316 1317 pinctrl_salt4_default: salt4_default { 1318 function = "SALT4"; 1319 groups = "SALT4"; 1320 }; 1321 1322 pinctrl_salt5_default: salt5_default { 1323 function = "SALT5"; 1324 groups = "SALT5"; 1325 }; 1326 1327 pinctrl_salt6_default: salt6_default { 1328 function = "SALT6"; 1329 groups = "SALT6"; 1330 }; 1331 1332 pinctrl_salt7_default: salt7_default { 1333 function = "SALT7"; 1334 groups = "SALT7"; 1335 }; 1336 1337 pinctrl_salt8_default: salt8_default { 1338 function = "SALT8"; 1339 groups = "SALT8"; 1340 }; 1341 1342 pinctrl_salt9_default: salt9_default { 1343 function = "SALT9"; 1344 groups = "SALT9"; 1345 }; 1346 1347 pinctrl_scl1_default: scl1_default { 1348 function = "SCL1"; 1349 groups = "SCL1"; 1350 }; 1351 1352 pinctrl_scl2_default: scl2_default { 1353 function = "SCL2"; 1354 groups = "SCL2"; 1355 }; 1356 1357 pinctrl_sd1_default: sd1_default { 1358 function = "SD1"; 1359 groups = "SD1"; 1360 }; 1361 1362 pinctrl_sd2_default: sd2_default { 1363 function = "SD2"; 1364 groups = "SD2"; 1365 }; 1366 1367 pinctrl_sda1_default: sda1_default { 1368 function = "SDA1"; 1369 groups = "SDA1"; 1370 }; 1371 1372 pinctrl_sda2_default: sda2_default { 1373 function = "SDA2"; 1374 groups = "SDA2"; 1375 }; 1376 1377 pinctrl_sgpm_default: sgpm_default { 1378 function = "SGPM"; 1379 groups = "SGPM"; 1380 }; 1381 1382 pinctrl_sgps1_default: sgps1_default { 1383 function = "SGPS1"; 1384 groups = "SGPS1"; 1385 }; 1386 1387 pinctrl_sgps2_default: sgps2_default { 1388 function = "SGPS2"; 1389 groups = "SGPS2"; 1390 }; 1391 1392 pinctrl_sioonctrl_default: sioonctrl_default { 1393 function = "SIOONCTRL"; 1394 groups = "SIOONCTRL"; 1395 }; 1396 1397 pinctrl_siopbi_default: siopbi_default { 1398 function = "SIOPBI"; 1399 groups = "SIOPBI"; 1400 }; 1401 1402 pinctrl_siopbo_default: siopbo_default { 1403 function = "SIOPBO"; 1404 groups = "SIOPBO"; 1405 }; 1406 1407 pinctrl_siopwreq_default: siopwreq_default { 1408 function = "SIOPWREQ"; 1409 groups = "SIOPWREQ"; 1410 }; 1411 1412 pinctrl_siopwrgd_default: siopwrgd_default { 1413 function = "SIOPWRGD"; 1414 groups = "SIOPWRGD"; 1415 }; 1416 1417 pinctrl_sios3_default: sios3_default { 1418 function = "SIOS3"; 1419 groups = "SIOS3"; 1420 }; 1421 1422 pinctrl_sios5_default: sios5_default { 1423 function = "SIOS5"; 1424 groups = "SIOS5"; 1425 }; 1426 1427 pinctrl_siosci_default: siosci_default { 1428 function = "SIOSCI"; 1429 groups = "SIOSCI"; 1430 }; 1431 1432 pinctrl_spi1_default: spi1_default { 1433 function = "SPI1"; 1434 groups = "SPI1"; 1435 }; 1436 1437 pinctrl_spi1cs1_default: spi1cs1_default { 1438 function = "SPI1CS1"; 1439 groups = "SPI1CS1"; 1440 }; 1441 1442 pinctrl_spi1debug_default: spi1debug_default { 1443 function = "SPI1DEBUG"; 1444 groups = "SPI1DEBUG"; 1445 }; 1446 1447 pinctrl_spi1passthru_default: spi1passthru_default { 1448 function = "SPI1PASSTHRU"; 1449 groups = "SPI1PASSTHRU"; 1450 }; 1451 1452 pinctrl_spi2ck_default: spi2ck_default { 1453 function = "SPI2CK"; 1454 groups = "SPI2CK"; 1455 }; 1456 1457 pinctrl_spi2cs0_default: spi2cs0_default { 1458 function = "SPI2CS0"; 1459 groups = "SPI2CS0"; 1460 }; 1461 1462 pinctrl_spi2cs1_default: spi2cs1_default { 1463 function = "SPI2CS1"; 1464 groups = "SPI2CS1"; 1465 }; 1466 1467 pinctrl_spi2miso_default: spi2miso_default { 1468 function = "SPI2MISO"; 1469 groups = "SPI2MISO"; 1470 }; 1471 1472 pinctrl_spi2mosi_default: spi2mosi_default { 1473 function = "SPI2MOSI"; 1474 groups = "SPI2MOSI"; 1475 }; 1476 1477 pinctrl_timer3_default: timer3_default { 1478 function = "TIMER3"; 1479 groups = "TIMER3"; 1480 }; 1481 1482 pinctrl_timer4_default: timer4_default { 1483 function = "TIMER4"; 1484 groups = "TIMER4"; 1485 }; 1486 1487 pinctrl_timer5_default: timer5_default { 1488 function = "TIMER5"; 1489 groups = "TIMER5"; 1490 }; 1491 1492 pinctrl_timer6_default: timer6_default { 1493 function = "TIMER6"; 1494 groups = "TIMER6"; 1495 }; 1496 1497 pinctrl_timer7_default: timer7_default { 1498 function = "TIMER7"; 1499 groups = "TIMER7"; 1500 }; 1501 1502 pinctrl_timer8_default: timer8_default { 1503 function = "TIMER8"; 1504 groups = "TIMER8"; 1505 }; 1506 1507 pinctrl_txd1_default: txd1_default { 1508 function = "TXD1"; 1509 groups = "TXD1"; 1510 }; 1511 1512 pinctrl_txd2_default: txd2_default { 1513 function = "TXD2"; 1514 groups = "TXD2"; 1515 }; 1516 1517 pinctrl_txd3_default: txd3_default { 1518 function = "TXD3"; 1519 groups = "TXD3"; 1520 }; 1521 1522 pinctrl_txd4_default: txd4_default { 1523 function = "TXD4"; 1524 groups = "TXD4"; 1525 }; 1526 1527 pinctrl_uart6_default: uart6_default { 1528 function = "UART6"; 1529 groups = "UART6"; 1530 }; 1531 1532 pinctrl_usbcki_default: usbcki_default { 1533 function = "USBCKI"; 1534 groups = "USBCKI"; 1535 }; 1536 1537 pinctrl_usb2ah_default: usb2ah_default { 1538 function = "USB2AH"; 1539 groups = "USB2AH"; 1540 }; 1541 1542 pinctrl_usb2ad_default: usb2ad_default { 1543 function = "USB2AD"; 1544 groups = "USB2AD"; 1545 }; 1546 1547 pinctrl_usb11bhid_default: usb11bhid_default { 1548 function = "USB11BHID"; 1549 groups = "USB11BHID"; 1550 }; 1551 1552 pinctrl_usb2bh_default: usb2bh_default { 1553 function = "USB2BH"; 1554 groups = "USB2BH"; 1555 }; 1556 1557 pinctrl_vgabiosrom_default: vgabiosrom_default { 1558 function = "VGABIOSROM"; 1559 groups = "VGABIOSROM"; 1560 }; 1561 1562 pinctrl_vgahs_default: vgahs_default { 1563 function = "VGAHS"; 1564 groups = "VGAHS"; 1565 }; 1566 1567 pinctrl_vgavs_default: vgavs_default { 1568 function = "VGAVS"; 1569 groups = "VGAVS"; 1570 }; 1571 1572 pinctrl_vpi24_default: vpi24_default { 1573 function = "VPI24"; 1574 groups = "VPI24"; 1575 }; 1576 1577 pinctrl_vpo_default: vpo_default { 1578 function = "VPO"; 1579 groups = "VPO"; 1580 }; 1581 1582 pinctrl_wdtrst1_default: wdtrst1_default { 1583 function = "WDTRST1"; 1584 groups = "WDTRST1"; 1585 }; 1586 1587 pinctrl_wdtrst2_default: wdtrst2_default { 1588 function = "WDTRST2"; 1589 groups = "WDTRST2"; 1590 }; 1591}; 1592