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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2014 FEDEVEL, Inc.
4 *
5 * Author: Robert Nelson <robertcnelson@gmail.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12	chosen {
13		stdout-path = &uart1;
14	};
15
16	regulators {
17		compatible = "simple-bus";
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		reg_3p3v: regulator@0 {
22			compatible = "regulator-fixed";
23			reg = <0>;
24			regulator-name = "3P3V";
25			regulator-min-microvolt = <3300000>;
26			regulator-max-microvolt = <3300000>;
27			regulator-always-on;
28		};
29
30		reg_usbh1_vbus: regulator@1 {
31			compatible = "regulator-fixed";
32			reg = <1>;
33			pinctrl-names = "default";
34			regulator-name = "usbh1_vbus";
35			regulator-min-microvolt = <5000000>;
36			regulator-max-microvolt = <5000000>;
37			gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
38			enable-active-high;
39		};
40
41		reg_usb_otg_vbus: regulator@2 {
42			compatible = "regulator-fixed";
43			reg = <2>;
44			pinctrl-names = "default";
45			regulator-name = "usb_otg_vbus";
46			regulator-min-microvolt = <5000000>;
47			regulator-max-microvolt = <5000000>;
48			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
49			enable-active-high;
50		};
51	};
52
53	leds {
54		compatible = "gpio-leds";
55		pinctrl-names = "default";
56		pinctrl-0 = <&pinctrl_led>;
57
58		led0: usr {
59			label = "usr";
60			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
61			default-state = "off";
62			linux,default-trigger = "heartbeat";
63		};
64	};
65
66	sound {
67		compatible = "fsl,imx6-rex-sgtl5000",
68			     "fsl,imx-audio-sgtl5000";
69		model = "imx6-rex-sgtl5000";
70		ssi-controller = <&ssi1>;
71		audio-codec = <&codec>;
72		audio-routing =
73			"MIC_IN", "Mic Jack",
74			"Mic Jack", "Mic Bias",
75			"Headphone Jack", "HP_OUT";
76		mux-int-port = <1>;
77		mux-ext-port = <3>;
78	};
79};
80
81&audmux {
82	pinctrl-names = "default";
83	pinctrl-0 = <&pinctrl_audmux>;
84	status = "okay";
85};
86
87&ecspi2 {
88	cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_ecspi2>;
91	status = "okay";
92};
93
94&ecspi3 {
95	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
96	pinctrl-names = "default";
97	pinctrl-0 = <&pinctrl_ecspi3>;
98	status = "okay";
99};
100
101&fec {
102	pinctrl-names = "default";
103	pinctrl-0 = <&pinctrl_enet>;
104	phy-mode = "rgmii";
105	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
106	status = "okay";
107};
108
109&hdmi {
110	ddc-i2c-bus = <&i2c2>;
111	status = "okay";
112};
113
114&i2c1 {
115	clock-frequency = <100000>;
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_i2c1>;
118	status = "okay";
119
120	codec: sgtl5000@a {
121		compatible = "fsl,sgtl5000";
122		reg = <0x0a>;
123		clocks = <&clks IMX6QDL_CLK_CKO>;
124		VDDA-supply = <&reg_3p3v>;
125		VDDIO-supply = <&reg_3p3v>;
126	};
127};
128
129&i2c2 {
130	clock-frequency = <100000>;
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_i2c2>;
133	status = "okay";
134
135	eeprom@57 {
136		compatible = "atmel,24c02";
137		reg = <0x57>;
138	};
139};
140
141&i2c3 {
142	clock-frequency = <100000>;
143	pinctrl-names = "default";
144	pinctrl-0 = <&pinctrl_i2c3>;
145	status = "okay";
146};
147
148&iomuxc {
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_hog>;
151
152	imx6qdl-rex {
153		pinctrl_hog: hoggrp {
154			fsl,pins = <
155				/* SGTL5000 sys_mclk */
156				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x030b0
157			>;
158		};
159
160		pinctrl_audmux: audmuxgrp {
161			fsl,pins = <
162				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
163				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
164				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
165				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
166			>;
167		};
168
169		pinctrl_ecspi2: ecspi2grp {
170			fsl,pins = <
171				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
172				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
173				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
174				/* CS */
175				MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26	0x000b1
176			>;
177		};
178
179		pinctrl_ecspi3: ecspi3grp {
180			fsl,pins = <
181				MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO	0x100b1
182				MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI	0x100b1
183				MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK	0x100b1
184				/* CS */
185				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x000b1
186			>;
187		};
188
189		pinctrl_enet: enetgrp {
190			fsl,pins = <
191				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
192				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
193				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
194				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
195				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
196				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
197				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
198				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
199				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
200				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
201				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
202				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
203				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
204				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
205				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
206				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
207				/* Phy reset */
208				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
209			>;
210		};
211
212		pinctrl_i2c1: i2c1grp {
213			fsl,pins = <
214				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
215				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
216			>;
217		};
218
219		pinctrl_i2c2: i2c2grp {
220			fsl,pins = <
221				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
222				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
223			>;
224		};
225
226		pinctrl_i2c3: i2c3grp {
227			fsl,pins = <
228				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
229				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
230			>;
231		};
232
233		pinctrl_led: ledgrp {
234			fsl,pins = <
235				/* user led */
236				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000
237			>;
238		};
239
240		pinctrl_uart1: uart1grp {
241			fsl,pins = <
242				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
243				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
244			>;
245		};
246
247		pinctrl_uart2: uart2grp {
248			fsl,pins = <
249				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
250				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
251			>;
252		};
253
254		pinctrl_usbh1: usbh1grp {
255			fsl,pins = <
256				/* power enable, high active */
257				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x10b0
258			>;
259		};
260
261		pinctrl_usbotg: usbotggrp {
262			fsl,pins = <
263				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
264				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
265				/* power enable, high active */
266				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x10b0
267			>;
268		};
269
270		pinctrl_usdhc2: usdhc2grp {
271			fsl,pins = <
272				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
273				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
274				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
275				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
276				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
277				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
278				/* CD */
279				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
280				/* WP */
281				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1f0b0
282			>;
283		};
284
285		pinctrl_usdhc3: usdhc3grp {
286			fsl,pins = <
287				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
288				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
289				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
290				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
291				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
292				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
293				/* CD */
294				MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
295				/* WP */
296				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1f0b0
297			>;
298		};
299	};
300};
301
302&ssi1 {
303	status = "okay";
304};
305
306&uart1 {
307	pinctrl-names = "default";
308	pinctrl-0 = <&pinctrl_uart1>;
309	status = "okay";
310};
311
312&uart2 {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_uart2>;
315	status = "okay";
316};
317
318&usbh1 {
319	vbus-supply = <&reg_usbh1_vbus>;
320	pinctrl-names = "default";
321	pinctrl-0 = <&pinctrl_usbh1>;
322	status = "okay";
323};
324
325&usbotg {
326	vbus-supply = <&reg_usb_otg_vbus>;
327	pinctrl-names = "default";
328	pinctrl-0 = <&pinctrl_usbotg>;
329	status = "okay";
330};
331
332&usdhc2 {
333	pinctrl-names = "default";
334	pinctrl-0 = <&pinctrl_usdhc2>;
335	bus-width = <4>;
336	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
337	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
338	status = "okay";
339};
340
341&usdhc3 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_usdhc3>;
344	bus-width = <4>;
345	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
346	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
347	status = "okay";
348};
349