1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2016-2017 Zodiac Inflight Innovations 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/sound/fsl-imx-audmux.h> 8 9/ { 10 chosen { 11 stdout-path = &uart1; 12 }; 13 14 aliases { 15 mdio-gpio0 = &mdio1; 16 rtc0 = &ds1341; 17 }; 18 19 mdio1: mdio { 20 compatible = "virtual,mdio-gpio"; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_mdio1>; 25 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH 26 &gpio6 4 GPIO_ACTIVE_HIGH>; 27 28 phy: ethernet-phy@0 { 29 pinctrl-0 = <&pinctrl_rmii_phy_irq>; 30 pinctrl-names = "default"; 31 reg = <0>; 32 interrupt-parent = <&gpio3>; 33 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 34 }; 35 }; 36 37 reg_28p0v: regulator-28p0v { 38 compatible = "regulator-fixed"; 39 regulator-name = "28V_IN"; 40 regulator-min-microvolt = <28000000>; 41 regulator-max-microvolt = <28000000>; 42 regulator-always-on; 43 }; 44 45 reg_12p0v: regulator-12p0v { 46 compatible = "regulator-fixed"; 47 vin-supply = <®_28p0v>; 48 regulator-name = "12V_MAIN"; 49 regulator-min-microvolt = <12000000>; 50 regulator-max-microvolt = <12000000>; 51 regulator-always-on; 52 }; 53 54 reg_5p0v_main: regulator-5p0v-main { 55 compatible = "regulator-fixed"; 56 vin-supply = <®_12p0v>; 57 regulator-name = "5V_MAIN"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 regulator-always-on; 61 }; 62 63 reg_5p0v_user_usb: regulator-5p0v-user-usb { 64 compatible = "regulator-fixed"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_reg_user_usb>; 67 vin-supply = <®_5p0v_main>; 68 regulator-name = "5V_USER_USB"; 69 regulator-min-microvolt = <5000000>; 70 regulator-max-microvolt = <5000000>; 71 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 72 startup-delay-us = <1000>; 73 }; 74 75 reg_3p3v_pmic: regulator-3p3v-pmic { 76 compatible = "regulator-fixed"; 77 vin-supply = <®_12p0v>; 78 regulator-name = "PMIC_3V3"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 regulator-always-on; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 vin-supply = <®_3p3v_pmic>; 87 regulator-name = "GEN_3V3"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 regulator-always-on; 91 }; 92 93 reg_3p3v_sd: regulator-3p3v-sd { 94 compatible = "regulator-fixed"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_reg_3p3v_sd>; 97 vin-supply = <®_3p3v>; 98 regulator-name = "3V3_SD"; 99 regulator-min-microvolt = <3300000>; 100 regulator-max-microvolt = <3300000>; 101 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; 102 startup-delay-us = <1000>; 103 enable-active-high; 104 regulator-always-on; 105 }; 106 107 reg_3p3v_display: regulator-3p3v-display { 108 compatible = "regulator-fixed"; 109 vin-supply = <®_12p0v>; 110 regulator-name = "3V3_DISPLAY"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 regulator-always-on; 114 }; 115 116 reg_3p3v_ssd: regulator-3p3v-ssd { 117 compatible = "regulator-fixed"; 118 vin-supply = <®_12p0v>; 119 regulator-name = "3V3_SSD"; 120 regulator-min-microvolt = <3300000>; 121 regulator-max-microvolt = <3300000>; 122 regulator-always-on; 123 }; 124 125 sound1 { 126 compatible = "simple-audio-card"; 127 simple-audio-card,name = "Front"; 128 simple-audio-card,format = "i2s"; 129 simple-audio-card,bitclock-master = <&sound1_codec>; 130 simple-audio-card,frame-master = <&sound1_codec>; 131 simple-audio-card,widgets = 132 "Headphone", "Headphone Jack"; 133 simple-audio-card,routing = 134 "Headphone Jack", "HPLEFT", 135 "Headphone Jack", "HPRIGHT", 136 "LEFTIN", "HPL", 137 "RIGHTIN", "HPR"; 138 simple-audio-card,aux-devs = <&hpa1>; 139 140 sound1_cpu: simple-audio-card,cpu { 141 sound-dai = <&ssi2>; 142 }; 143 144 sound1_codec: simple-audio-card,codec { 145 sound-dai = <&codec1>; 146 clocks = <&cs2000>; 147 }; 148 }; 149 150 sound2 { 151 compatible = "simple-audio-card"; 152 simple-audio-card,name = "Back"; 153 simple-audio-card,format = "i2s"; 154 simple-audio-card,bitclock-master = <&sound2_codec>; 155 simple-audio-card,frame-master = <&sound2_codec>; 156 simple-audio-card,widgets = 157 "Headphone", "Headphone Jack"; 158 simple-audio-card,routing = 159 "Headphone Jack", "HPLEFT", 160 "Headphone Jack", "HPRIGHT", 161 "LEFTIN", "HPL", 162 "RIGHTIN", "HPR"; 163 simple-audio-card,aux-devs = <&hpa2>; 164 165 sound2_cpu: simple-audio-card,cpu { 166 sound-dai = <&ssi1>; 167 }; 168 169 sound2_codec: simple-audio-card,codec { 170 sound-dai = <&codec2>; 171 clocks = <&cs2000>; 172 }; 173 }; 174 175 panel { 176 power-supply = <®_3p3v_display>; 177 backlight = <&sp_backlight>; 178 status = "disabled"; 179 180 port { 181 panel_in: endpoint { 182 remote-endpoint = <&lvds0_out>; 183 }; 184 }; 185 }; 186 187 disp0: disp0 { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 compatible = "fsl,imx-parallel-display"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_disp0>; 193 status = "disabled"; 194 195 port@0 { 196 reg = <0>; 197 198 disp0_in_0: endpoint { 199 remote-endpoint = <&ipu1_di0_disp0>; 200 }; 201 }; 202 203 port@1 { 204 reg = <1>; 205 206 disp0_out: endpoint { 207 remote-endpoint = <&tc358767_in>; 208 }; 209 }; 210 }; 211 212 cs2000_ref: cs2000-ref { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <24576000>; 216 }; 217 218 cs2000_in_dummy: cs2000-in-dummy { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <0>; 222 }; 223 224 edp_refclk: edp-refclk { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <19200000>; 228 }; 229}; 230 231&cpu0 { 232 fsl,soc-operating-points = < 233 /* ARM kHz SOC-PU uV */ 234 1200000 1300000 235 996000 1275000 236 852000 1275000 237 792000 1200000 238 396000 1200000 239 >; 240}; 241 242®_arm { 243 vin-supply = <&sw1a_reg>; 244}; 245 246®_pu { 247 vin-supply = <&sw1c_reg>; 248}; 249 250®_soc { 251 vin-supply = <&sw1c_reg>; 252}; 253 254&ldb { 255 lvds-channel@0 { 256 port@4 { 257 reg = <4>; 258 259 lvds0_out: endpoint { 260 remote-endpoint = <&panel_in>; 261 }; 262 }; 263 }; 264}; 265 266&uart1 { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_uart1>; 269 status = "okay"; 270}; 271 272&uart3 { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_uart3>; 275 uart-has-rtscts; 276 linux,rs485-enabled-at-boot-time; 277 status = "okay"; 278}; 279 280&uart4 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_uart4>; 283 status = "okay"; 284 285 rave-sp { 286 compatible = "zii,rave-sp-rdu2"; 287 current-speed = <1000000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 291 watchdog { 292 compatible = "zii,rave-sp-watchdog"; 293 }; 294 295 sp_backlight: backlight { 296 compatible = "zii,rave-sp-backlight"; 297 }; 298 299 pwrbutton { 300 compatible = "zii,rave-sp-pwrbutton"; 301 }; 302 303 eeprom@a3 { 304 compatible = "zii,rave-sp-eeprom"; 305 reg = <0xa3 0x4000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 zii,eeprom-name = "dds-eeprom"; 309 }; 310 311 eeprom@a4 { 312 compatible = "zii,rave-sp-eeprom"; 313 reg = <0xa4 0x4000>; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 zii,eeprom-name = "main-eeprom"; 317 }; 318 }; 319}; 320 321&ecspi1 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_ecspi1>; 324 cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; 325 status = "okay"; 326 327 flash@0 { 328 compatible = "st,m25p128", "jedec,spi-nor"; 329 spi-max-frequency = <20000000>; 330 reg = <0>; 331 }; 332}; 333 334&i2c1 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_i2c1>; 337 clock-frequency = <100000>; 338 status = "okay"; 339 340 codec2: codec@18 { 341 compatible = "ti,tlv320dac3100"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_codec2>; 344 reg = <0x18>; 345 #sound-dai-cells = <0>; 346 HPVDD-supply = <®_3p3v>; 347 SPRVDD-supply = <®_3p3v>; 348 SPLVDD-supply = <®_3p3v>; 349 AVDD-supply = <®_3p3v>; 350 IOVDD-supply = <®_3p3v>; 351 DVDD-supply = <&vgen4_reg>; 352 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 353 }; 354 355 accel@1c { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_accel>; 358 compatible = "fsl,mma8451"; 359 reg = <0x1c>; 360 interrupt-parent = <&gpio1>; 361 interrupt-names = "int1", "int2"; 362 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 hpa2: amp@60 { 366 compatible = "ti,tpa6130a2"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_tpa2>; 369 reg = <0x60>; 370 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 371 Vdd-supply = <®_5p0v_main>; 372 }; 373 374 edp-bridge@68 { 375 compatible = "toshiba,tc358767"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_tc358767>; 378 reg = <0x68>; 379 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 380 clock-names = "ref"; 381 clocks = <&edp_refclk>; 382 status = "disabled"; 383 384 ports { 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 port@1 { 389 reg = <1>; 390 391 tc358767_in: endpoint { 392 remote-endpoint = <&disp0_out>; 393 }; 394 }; 395 }; 396 }; 397}; 398 399&i2c2 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_i2c2>; 402 clock-frequency = <100000>; 403 status = "okay"; 404 405 pmic@8 { 406 compatible = "fsl,pfuze100"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_pfuze100_irq>; 409 reg = <0x08>; 410 interrupt-parent = <&gpio7>; 411 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 412 413 regulators { 414 sw1a_reg: sw1ab { 415 regulator-min-microvolt = <300000>; 416 regulator-max-microvolt = <1875000>; 417 regulator-boot-on; 418 regulator-always-on; 419 regulator-ramp-delay = <6250>; 420 }; 421 422 sw1c_reg: sw1c { 423 regulator-min-microvolt = <300000>; 424 regulator-max-microvolt = <1875000>; 425 regulator-boot-on; 426 regulator-always-on; 427 regulator-ramp-delay = <6250>; 428 }; 429 430 sw2_reg: sw2 { 431 regulator-min-microvolt = <800000>; 432 regulator-max-microvolt = <3000000>; 433 regulator-boot-on; 434 regulator-always-on; 435 }; 436 437 sw3a_reg: sw3a { 438 regulator-min-microvolt = <400000>; 439 regulator-max-microvolt = <1500000>; 440 regulator-boot-on; 441 regulator-always-on; 442 }; 443 444 sw3b_reg: sw3b { 445 regulator-min-microvolt = <400000>; 446 regulator-max-microvolt = <1500000>; 447 regulator-boot-on; 448 regulator-always-on; 449 }; 450 451 sw4_reg: sw4 { 452 regulator-min-microvolt = <800000>; 453 regulator-max-microvolt = <1800000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 snvs_reg: vsnvs { 459 regulator-min-microvolt = <1000000>; 460 regulator-max-microvolt = <3000000>; 461 regulator-boot-on; 462 regulator-always-on; 463 }; 464 465 vref_reg: vrefddr { 466 regulator-boot-on; 467 regulator-always-on; 468 }; 469 470 vgen2_reg: vgen2 { 471 regulator-min-microvolt = <1000000>; 472 regulator-max-microvolt = <1500000>; 473 regulator-always-on; 474 }; 475 476 vgen4_reg: vgen4 { 477 regulator-min-microvolt = <1200000>; 478 regulator-max-microvolt = <1800000>; 479 regulator-always-on; 480 }; 481 482 vgen5_reg: vgen5 { 483 regulator-min-microvolt = <1800000>; 484 regulator-max-microvolt = <2500000>; 485 regulator-always-on; 486 }; 487 488 vgen6_reg: vgen6 { 489 regulator-min-microvolt = <1800000>; 490 regulator-max-microvolt = <2800000>; 491 regulator-always-on; 492 }; 493 }; 494 }; 495 496 watchdog@38 { 497 compatible = "zii,rave-wdt"; 498 reg = <0x38>; 499 }; 500 501 temp-sense@48 { 502 compatible = "national,lm75"; 503 reg = <0x48>; 504 }; 505 506 cs2000: clkgen@4e { 507 compatible = "cirrus,cs2000-cp"; 508 reg = <0x4e>; 509 #clock-cells = <0>; 510 clock-names = "clk_in", "ref_clk"; 511 clocks = <&cs2000_in_dummy>, <&cs2000_ref>; 512 assigned-clocks = <&cs2000>; 513 assigned-clock-rates = <24000000>; 514 }; 515 516 eeprom@54 { 517 compatible = "atmel,24c128"; 518 reg = <0x54>; 519 }; 520 521 ds1341: rtc@68 { 522 compatible = "dallas,ds1341"; 523 reg = <0x68>; 524 }; 525}; 526 527&i2c3 { 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pinctrl_i2c3>; 530 clock-frequency = <400000>; 531 status = "okay"; 532 533 codec1: codec@18 { 534 compatible = "ti,tlv320dac3100"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_codec1>; 537 reg = <0x18>; 538 #sound-dai-cells = <0>; 539 HPVDD-supply = <®_3p3v>; 540 SPRVDD-supply = <®_3p3v>; 541 SPLVDD-supply = <®_3p3v>; 542 AVDD-supply = <®_3p3v>; 543 IOVDD-supply = <®_3p3v>; 544 DVDD-supply = <&vgen4_reg>; 545 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 546 }; 547 548 touchscreen@20 { 549 compatible = "syna,rmi4-i2c"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_ts>; 552 reg = <0x20>; 553 interrupt-parent = <&gpio1>; 554 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 555 vdd-supply = <®_5p0v_main>; 556 vio-supply = <®_3p3v>; 557 558 #address-cells = <1>; 559 #size-cells = <0>; 560 561 rmi4-f01@1 { 562 reg = <0x1>; 563 syna,nosleep-mode = <2>; 564 }; 565 566 rmi4-f11@11 { 567 reg = <0x11>; 568 touchscreen-inverted-x; 569 touchscreen-swapped-x-y; 570 syna,sensor-type = <1>; 571 }; 572 573 rmi4-f12@12 { 574 reg = <0x12>; 575 touchscreen-inverted-x; 576 touchscreen-swapped-x-y; 577 syna,sensor-type = <1>; 578 }; 579 }; 580 581 touchscreen@2a { 582 compatible = "eeti,exc3000"; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pinctrl_ts>; 585 reg = <0x2a>; 586 interrupt-parent = <&gpio1>; 587 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 588 touchscreen-inverted-x; 589 touchscreen-swapped-x-y; 590 status = "disabled"; 591 }; 592 593 hpa1: amp@60 { 594 compatible = "ti,tpa6130a2"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_tpa1>; 597 reg = <0x60>; 598 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 599 Vdd-supply = <®_5p0v_main>; 600 }; 601}; 602 603&ipu1_di0_disp0 { 604 remote-endpoint = <&disp0_in_0>; 605}; 606 607&pcie { 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pinctrl_pcie>; 610 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 611 status = "okay"; 612 613 host@0 { 614 reg = <0 0 0 0 0>; 615 616 #address-cells = <3>; 617 #size-cells = <2>; 618 619 i210: i210@0 { 620 reg = <0 0 0 0 0>; 621 }; 622 }; 623}; 624 625&usdhc2 { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_usdhc2>; 628 bus-width = <4>; 629 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 630 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 631 vmmc-supply = <®_3p3v_sd>; 632 vqmmc-supply = <®_3p3v>; 633 no-1-8-v; 634 no-sdio; 635 status = "okay"; 636}; 637 638&usdhc3 { 639 pinctrl-names = "default"; 640 pinctrl-0 = <&pinctrl_usdhc3>; 641 bus-width = <4>; 642 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 643 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 644 vmmc-supply = <®_3p3v_sd>; 645 vqmmc-supply = <®_3p3v>; 646 no-1-8-v; 647 no-sdio; 648 status = "okay"; 649}; 650 651&usdhc4 { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_usdhc4>; 654 bus-width = <8>; 655 vmmc-supply = <®_3p3v>; 656 vqmmc-supply = <®_3p3v>; 657 no-1-8-v; 658 non-removable; 659 no-sdio; 660 no-sd; 661 status = "okay"; 662}; 663 664&sata { 665 target-supply = <®_3p3v_ssd>; 666 status = "okay"; 667}; 668 669&fec { 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pinctrl_enet>; 672 phy-mode = "rmii"; 673 phy-handle = <&phy>; 674 phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 675 phy-reset-duration = <100>; 676 phy-supply = <®_3p3v>; 677 status = "okay"; 678 679 mdio { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "okay"; 683 684 switch: switch@0 { 685 compatible = "marvell,mv88e6085"; 686 pinctrl-0 = <&pinctrl_switch_irq>; 687 pinctrl-names = "default"; 688 reg = <0>; 689 dsa,member = <0 0>; 690 eeprom-length = <512>; 691 interrupt-parent = <&gpio6>; 692 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 696 ports { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 port@0 { 701 reg = <0>; 702 label = "gigabit_proc"; 703 phy-handle = <&switchphy0>; 704 }; 705 706 port@1 { 707 reg = <1>; 708 label = "netaux"; 709 phy-handle = <&switchphy1>; 710 }; 711 712 port@2 { 713 reg = <2>; 714 label = "cpu"; 715 ethernet = <&fec>; 716 717 fixed-link { 718 speed = <100>; 719 full-duplex; 720 }; 721 }; 722 723 port@3 { 724 reg = <3>; 725 label = "netright"; 726 phy-handle = <&switchphy3>; 727 }; 728 729 port@4 { 730 reg = <4>; 731 label = "netleft"; 732 phy-handle = <&switchphy4>; 733 }; 734 }; 735 736 mdio { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 740 switchphy0: switchphy@0 { 741 reg = <0>; 742 interrupt-parent = <&switch>; 743 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 744 }; 745 746 switchphy1: switchphy@1 { 747 reg = <1>; 748 interrupt-parent = <&switch>; 749 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 switchphy2: switchphy@2 { 753 reg = <2>; 754 interrupt-parent = <&switch>; 755 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 756 }; 757 758 switchphy3: switchphy@3 { 759 reg = <3>; 760 interrupt-parent = <&switch>; 761 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 762 }; 763 764 switchphy4: switchphy@4 { 765 reg = <4>; 766 interrupt-parent = <&switch>; 767 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 768 }; 769 }; 770 }; 771 }; 772}; 773 774&usbh1 { 775 vbus-supply = <®_5p0v_main>; 776 disable-over-current; 777 status = "okay"; 778}; 779 780&usbotg { 781 vbus-supply = <®_5p0v_user_usb>; 782 disable-over-current; 783 dr_mode = "host"; 784 status = "okay"; 785}; 786 787&snvs_rtc { 788 status = "disabled"; 789}; 790 791&ssi1 { 792 status = "okay"; 793}; 794 795&ssi2 { 796 status = "okay"; 797}; 798 799&audmux { 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_audmux>; 802 status = "okay"; 803 804 ssi1 { 805 fsl,audmux-port = <0>; 806 fsl,port-config = < 807 (IMX_AUDMUX_V2_PTCR_SYN | 808 IMX_AUDMUX_V2_PTCR_TFSEL(2) | 809 IMX_AUDMUX_V2_PTCR_TCSEL(2) | 810 IMX_AUDMUX_V2_PTCR_TFSDIR | 811 IMX_AUDMUX_V2_PTCR_TCLKDIR) 812 IMX_AUDMUX_V2_PDCR_RXDSEL(2) 813 >; 814 }; 815 816 aud3 { 817 fsl,audmux-port = <2>; 818 fsl,port-config = < 819 IMX_AUDMUX_V2_PTCR_SYN 820 IMX_AUDMUX_V2_PDCR_RXDSEL(0) 821 >; 822 }; 823 824 ssi2 { 825 fsl,audmux-port = <1>; 826 fsl,port-config = < 827 (IMX_AUDMUX_V2_PTCR_SYN | 828 IMX_AUDMUX_V2_PTCR_TFSEL(4) | 829 IMX_AUDMUX_V2_PTCR_TCSEL(4) | 830 IMX_AUDMUX_V2_PTCR_TFSDIR | 831 IMX_AUDMUX_V2_PTCR_TCLKDIR) 832 IMX_AUDMUX_V2_PDCR_RXDSEL(4) 833 >; 834 }; 835 836 aud5 { 837 fsl,audmux-port = <4>; 838 fsl,port-config = < 839 IMX_AUDMUX_V2_PTCR_SYN 840 IMX_AUDMUX_V2_PDCR_RXDSEL(1) 841 >; 842 }; 843}; 844 845&wdog1 { 846 status = "disabled"; 847}; 848 849&iomuxc { 850 pinctrl_accel: accelgrp { 851 fsl,pins = < 852 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x4001b000 853 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000 854 >; 855 }; 856 857 pinctrl_audmux: audmuxgrp { 858 fsl,pins = < 859 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 860 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 861 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 862 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 863 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 864 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 865 >; 866 }; 867 868 pinctrl_codec1: dac1grp { 869 fsl,pins = < 870 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038 871 >; 872 }; 873 874 pinctrl_codec2: dac2grp { 875 fsl,pins = < 876 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038 877 >; 878 }; 879 880 pinctrl_disp0: disp0grp { 881 fsl,pins = < 882 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9 883 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9 884 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9 885 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9 886 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9 887 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9 888 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9 889 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9 890 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9 891 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9 892 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9 893 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9 894 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9 895 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9 896 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9 897 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9 898 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9 899 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9 900 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9 901 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9 902 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9 903 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9 904 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9 905 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9 906 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9 907 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9 908 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9 909 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9 910 >; 911 }; 912 913 pinctrl_ecspi1: ecspi1grp { 914 fsl,pins = < 915 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 916 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 917 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 918 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 919 >; 920 }; 921 922 pinctrl_enet: enetgrp { 923 fsl,pins = < 924 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1 925 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1 926 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 927 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 928 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 929 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 930 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 931 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 932 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040 933 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0 934 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 935 >; 936 }; 937 938 pinctrl_i2c1: i2c1grp { 939 fsl,pins = < 940 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 941 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 942 >; 943 }; 944 945 pinctrl_i2c2: i2c2grp { 946 fsl,pins = < 947 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 948 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 949 >; 950 }; 951 952 pinctrl_i2c3: i2c3grp { 953 fsl,pins = < 954 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 955 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 956 >; 957 }; 958 959 pinctrl_mdio1: bitbangmdiogrp { 960 fsl,pins = < 961 /* Bitbang MDIO for DEB Switch */ 962 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030 963 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830 964 >; 965 }; 966 967 pinctrl_pcie: pciegrp { 968 fsl,pins = < 969 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038 970 >; 971 }; 972 973 pinctrl_pfuze100_irq: pfuze100grp { 974 fsl,pins = < 975 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000 976 >; 977 }; 978 979 pinctrl_reg_3p3v_sd: mmcsupply1grp { 980 fsl,pins = < 981 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858 982 >; 983 }; 984 985 pinctrl_reg_user_usb: usbotggrp { 986 fsl,pins = < 987 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x40000038 988 >; 989 }; 990 991 pinctrl_rmii_phy_irq: phygrp { 992 fsl,pins = < 993 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 994 >; 995 }; 996 997 pinctrl_switch_irq: switchgrp { 998 fsl,pins = < 999 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 1000 >; 1001 }; 1002 1003 pinctrl_tc358767: tc358767grp { 1004 fsl,pins = < 1005 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 1006 >; 1007 }; 1008 1009 pinctrl_tpa1: tpa6130-1grp { 1010 fsl,pins = < 1011 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038 1012 >; 1013 }; 1014 1015 pinctrl_tpa2: tpa6130-2grp { 1016 fsl,pins = < 1017 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038 1018 >; 1019 }; 1020 1021 pinctrl_ts: tsgrp { 1022 fsl,pins = < 1023 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 1024 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 1025 >; 1026 }; 1027 1028 pinctrl_uart1: uart1grp { 1029 fsl,pins = < 1030 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1031 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1032 >; 1033 }; 1034 1035 pinctrl_uart3: uart3grp { 1036 fsl,pins = < 1037 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 1038 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 1039 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 1040 >; 1041 }; 1042 1043 pinctrl_uart4: uart4grp { 1044 fsl,pins = < 1045 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 1046 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 1047 >; 1048 }; 1049 1050 pinctrl_usdhc2: usdhc2grp { 1051 fsl,pins = < 1052 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059 1053 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 1054 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 1055 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 1056 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 1057 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 1058 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x40010040 1059 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 1060 >; 1061 }; 1062 1063 pinctrl_usdhc3: usdhc3grp { 1064 fsl,pins = < 1065 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059 1066 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 1067 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1068 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1069 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1070 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1071 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x40010040 1072 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 1073 1074 >; 1075 }; 1076 1077 pinctrl_usdhc4: usdhc4grp { 1078 fsl,pins = < 1079 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 1080 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 1081 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 1082 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 1083 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 1084 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 1085 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 1086 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 1087 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 1088 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 1089 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 1090 >; 1091 }; 1092}; 1093