1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014 Carlo Caione <carlo@caione.org> 4 */ 5 6#include <dt-bindings/clock/meson8b-clkc.h> 7#include <dt-bindings/gpio/meson8-gpio.h> 8#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 9#include <dt-bindings/reset/amlogic,meson8b-reset.h> 10#include "meson.dtsi" 11 12/ { 13 model = "Amlogic Meson8 SoC"; 14 compatible = "amlogic,meson8"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@200 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 next-level-cache = <&L2>; 24 reg = <0x200>; 25 enable-method = "amlogic,meson8-smp"; 26 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 27 operating-points-v2 = <&cpu_opp_table>; 28 clocks = <&clkc CLKID_CPUCLK>; 29 }; 30 31 cpu1: cpu@201 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 next-level-cache = <&L2>; 35 reg = <0x201>; 36 enable-method = "amlogic,meson8-smp"; 37 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 38 operating-points-v2 = <&cpu_opp_table>; 39 clocks = <&clkc CLKID_CPUCLK>; 40 }; 41 42 cpu2: cpu@202 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a9"; 45 next-level-cache = <&L2>; 46 reg = <0x202>; 47 enable-method = "amlogic,meson8-smp"; 48 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 49 operating-points-v2 = <&cpu_opp_table>; 50 clocks = <&clkc CLKID_CPUCLK>; 51 }; 52 53 cpu3: cpu@203 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 next-level-cache = <&L2>; 57 reg = <0x203>; 58 enable-method = "amlogic,meson8-smp"; 59 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 60 operating-points-v2 = <&cpu_opp_table>; 61 clocks = <&clkc CLKID_CPUCLK>; 62 }; 63 }; 64 65 cpu_opp_table: opp-table { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-96000000 { 70 opp-hz = /bits/ 64 <96000000>; 71 opp-microvolt = <825000>; 72 }; 73 opp-192000000 { 74 opp-hz = /bits/ 64 <192000000>; 75 opp-microvolt = <825000>; 76 }; 77 opp-312000000 { 78 opp-hz = /bits/ 64 <312000000>; 79 opp-microvolt = <825000>; 80 }; 81 opp-408000000 { 82 opp-hz = /bits/ 64 <408000000>; 83 opp-microvolt = <825000>; 84 }; 85 opp-504000000 { 86 opp-hz = /bits/ 64 <504000000>; 87 opp-microvolt = <825000>; 88 }; 89 opp-600000000 { 90 opp-hz = /bits/ 64 <600000000>; 91 opp-microvolt = <850000>; 92 }; 93 opp-720000000 { 94 opp-hz = /bits/ 64 <720000000>; 95 opp-microvolt = <850000>; 96 }; 97 opp-816000000 { 98 opp-hz = /bits/ 64 <816000000>; 99 opp-microvolt = <875000>; 100 }; 101 opp-1008000000 { 102 opp-hz = /bits/ 64 <1008000000>; 103 opp-microvolt = <925000>; 104 }; 105 opp-1200000000 { 106 opp-hz = /bits/ 64 <1200000000>; 107 opp-microvolt = <975000>; 108 }; 109 opp-1416000000 { 110 opp-hz = /bits/ 64 <1416000000>; 111 opp-microvolt = <1025000>; 112 }; 113 opp-1608000000 { 114 opp-hz = /bits/ 64 <1608000000>; 115 opp-microvolt = <1100000>; 116 }; 117 opp-1800000000 { 118 status = "disabled"; 119 opp-hz = /bits/ 64 <1800000000>; 120 opp-microvolt = <1125000>; 121 }; 122 opp-1992000000 { 123 status = "disabled"; 124 opp-hz = /bits/ 64 <1992000000>; 125 opp-microvolt = <1150000>; 126 }; 127 }; 128 129 gpu_opp_table: gpu-opp-table { 130 compatible = "operating-points-v2"; 131 132 opp-182150000 { 133 opp-hz = /bits/ 64 <182150000>; 134 opp-microvolt = <1150000>; 135 }; 136 opp-318750000 { 137 opp-hz = /bits/ 64 <318750000>; 138 opp-microvolt = <1150000>; 139 }; 140 opp-425000000 { 141 opp-hz = /bits/ 64 <425000000>; 142 opp-microvolt = <1150000>; 143 }; 144 opp-510000000 { 145 opp-hz = /bits/ 64 <510000000>; 146 opp-microvolt = <1150000>; 147 }; 148 opp-637500000 { 149 opp-hz = /bits/ 64 <637500000>; 150 opp-microvolt = <1150000>; 151 turbo-mode; 152 }; 153 }; 154 155 pmu { 156 compatible = "arm,cortex-a9-pmu"; 157 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 162 }; 163 164 reserved-memory { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges; 168 169 /* 2 MiB reserved for Hardware ROM Firmware? */ 170 hwrom@0 { 171 reg = <0x0 0x200000>; 172 no-map; 173 }; 174 175 /* 176 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 177 * code which is responsible for system suspend. It loads a 178 * piece of ARC code ("arc_power" in the vendor u-boot tree) 179 * into SRAM, executes that and shuts down the (last) ARM core. 180 * The arc_power firmware then checks various wakeup sources 181 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 182 * simply the power key) and re-starts the ARM core once it 183 * detects a wakeup request. 184 */ 185 power-firmware@4f00000 { 186 reg = <0x4f00000 0x100000>; 187 no-map; 188 }; 189 }; 190 191 mmcbus: bus@c8000000 { 192 compatible = "simple-bus"; 193 reg = <0xc8000000 0x8000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges = <0x0 0xc8000000 0x8000>; 197 198 dmcbus: bus@6000 { 199 compatible = "simple-bus"; 200 reg = <0x6000 0x400>; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges = <0x0 0x6000 0x400>; 204 205 canvas: video-lut@20 { 206 compatible = "amlogic,meson8-canvas", 207 "amlogic,canvas"; 208 reg = <0x20 0x14>; 209 }; 210 }; 211 }; 212 213 apb: bus@d0000000 { 214 compatible = "simple-bus"; 215 reg = <0xd0000000 0x200000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0x0 0xd0000000 0x200000>; 219 220 mali: gpu@c0000 { 221 compatible = "amlogic,meson8-mali", "arm,mali-450"; 222 reg = <0xc0000 0x40000>; 223 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-names = "gp", "gpmmu", "pp", "pmu", 242 "pp0", "ppmmu0", "pp1", "ppmmu1", 243 "pp2", "ppmmu2", "pp4", "ppmmu4", 244 "pp5", "ppmmu5", "pp6", "ppmmu6"; 245 resets = <&reset RESET_MALI>; 246 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 247 clock-names = "bus", "core"; 248 operating-points-v2 = <&gpu_opp_table>; 249 }; 250 }; 251}; /* end of / */ 252 253&aobus { 254 pmu: pmu@e0 { 255 compatible = "amlogic,meson8-pmu", "syscon"; 256 reg = <0xe0 0x18>; 257 }; 258 259 pinctrl_aobus: pinctrl@84 { 260 compatible = "amlogic,meson8-aobus-pinctrl"; 261 reg = <0x84 0xc>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 gpio_ao: ao-bank@14 { 267 reg = <0x14 0x4>, 268 <0x2c 0x4>, 269 <0x24 0x8>; 270 reg-names = "mux", "pull", "gpio"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 gpio-ranges = <&pinctrl_aobus 0 0 16>; 274 }; 275 276 uart_ao_a_pins: uart_ao_a { 277 mux { 278 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 279 function = "uart_ao"; 280 bias-disable; 281 }; 282 }; 283 284 i2c_ao_pins: i2c_mst_ao { 285 mux { 286 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 287 function = "i2c_mst_ao"; 288 bias-disable; 289 }; 290 }; 291 292 ir_recv_pins: remote { 293 mux { 294 groups = "remote_input"; 295 function = "remote"; 296 bias-disable; 297 }; 298 }; 299 300 pwm_f_ao_pins: pwm-f-ao { 301 mux { 302 groups = "pwm_f_ao"; 303 function = "pwm_f_ao"; 304 bias-disable; 305 }; 306 }; 307 }; 308}; 309 310&cbus { 311 reset: reset-controller@4404 { 312 compatible = "amlogic,meson8b-reset"; 313 reg = <0x4404 0x9c>; 314 #reset-cells = <1>; 315 }; 316 317 analog_top: analog-top@81a8 { 318 compatible = "amlogic,meson8-analog-top", "syscon"; 319 reg = <0x81a8 0x14>; 320 }; 321 322 pwm_ef: pwm@86c0 { 323 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 324 reg = <0x86c0 0x10>; 325 #pwm-cells = <3>; 326 status = "disabled"; 327 }; 328 329 clock-measure@8758 { 330 compatible = "amlogic,meson8-clk-measure"; 331 reg = <0x8758 0x1c>; 332 }; 333 334 pinctrl_cbus: pinctrl@9880 { 335 compatible = "amlogic,meson8-cbus-pinctrl"; 336 reg = <0x9880 0x10>; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges; 340 341 gpio: banks@80b0 { 342 reg = <0x80b0 0x28>, 343 <0x80e8 0x18>, 344 <0x8120 0x18>, 345 <0x8030 0x30>; 346 reg-names = "mux", "pull", "pull-enable", "gpio"; 347 gpio-controller; 348 #gpio-cells = <2>; 349 gpio-ranges = <&pinctrl_cbus 0 0 120>; 350 }; 351 352 sd_a_pins: sd-a { 353 mux { 354 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 355 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 356 function = "sd_a"; 357 bias-disable; 358 }; 359 }; 360 361 sd_b_pins: sd-b { 362 mux { 363 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 364 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 365 function = "sd_b"; 366 bias-disable; 367 }; 368 }; 369 370 sd_c_pins: sd-c { 371 mux { 372 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 373 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 374 function = "sd_c"; 375 bias-disable; 376 }; 377 }; 378 379 spi_nor_pins: nor { 380 mux { 381 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 382 function = "nor"; 383 bias-disable; 384 }; 385 }; 386 387 eth_pins: ethernet { 388 mux { 389 groups = "eth_tx_clk_50m", "eth_tx_en", 390 "eth_txd1", "eth_txd0", 391 "eth_rx_clk_in", "eth_rx_dv", 392 "eth_rxd1", "eth_rxd0", "eth_mdio", 393 "eth_mdc"; 394 function = "ethernet"; 395 bias-disable; 396 }; 397 }; 398 399 pwm_e_pins: pwm-e { 400 mux { 401 groups = "pwm_e"; 402 function = "pwm_e"; 403 bias-disable; 404 }; 405 }; 406 407 uart_a1_pins: uart-a1 { 408 mux { 409 groups = "uart_tx_a1", 410 "uart_rx_a1"; 411 function = "uart_a"; 412 bias-disable; 413 }; 414 }; 415 416 uart_a1_cts_rts_pins: uart-a1-cts-rts { 417 mux { 418 groups = "uart_cts_a1", 419 "uart_rts_a1"; 420 function = "uart_a"; 421 bias-disable; 422 }; 423 }; 424 }; 425}; 426 427&ahb_sram { 428 smp-sram@1ff80 { 429 compatible = "amlogic,meson8-smp-sram"; 430 reg = <0x1ff80 0x8>; 431 }; 432}; 433 434&efuse { 435 compatible = "amlogic,meson8-efuse"; 436 clocks = <&clkc CLKID_EFUSE>; 437 clock-names = "core"; 438 439 temperature_calib: calib@1f4 { 440 /* only the upper two bytes are relevant */ 441 reg = <0x1f4 0x4>; 442 }; 443}; 444 445ðmac { 446 clocks = <&clkc CLKID_ETH>; 447 clock-names = "stmmaceth"; 448}; 449 450&gpio_intc { 451 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 452 status = "okay"; 453}; 454 455&hhi { 456 clkc: clock-controller { 457 compatible = "amlogic,meson8-clkc"; 458 #clock-cells = <1>; 459 #reset-cells = <1>; 460 }; 461}; 462 463&hwrng { 464 compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; 465 clocks = <&clkc CLKID_RNG0>; 466 clock-names = "core"; 467}; 468 469&i2c_AO { 470 clocks = <&clkc CLKID_CLK81>; 471}; 472 473&i2c_A { 474 clocks = <&clkc CLKID_CLK81>; 475}; 476 477&i2c_B { 478 clocks = <&clkc CLKID_CLK81>; 479}; 480 481&L2 { 482 arm,data-latency = <3 3 3>; 483 arm,tag-latency = <2 2 2>; 484 arm,filter-ranges = <0x100000 0xc0000000>; 485 prefetch-data = <1>; 486 prefetch-instr = <1>; 487 arm,shared-override; 488}; 489 490&periph { 491 scu@0 { 492 compatible = "arm,cortex-a9-scu"; 493 reg = <0x0 0x100>; 494 }; 495 496 timer@200 { 497 compatible = "arm,cortex-a9-global-timer"; 498 reg = <0x200 0x20>; 499 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 500 clocks = <&clkc CLKID_PERIPH>; 501 502 /* 503 * the arm_global_timer driver currently does not handle clock 504 * rate changes. Keep it disabled for now. 505 */ 506 status = "disabled"; 507 }; 508 509 timer@600 { 510 compatible = "arm,cortex-a9-twd-timer"; 511 reg = <0x600 0x20>; 512 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 513 clocks = <&clkc CLKID_PERIPH>; 514 }; 515}; 516 517&pwm_ab { 518 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 519}; 520 521&pwm_cd { 522 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 523}; 524 525&rtc { 526 compatible = "amlogic,meson8-rtc"; 527 resets = <&reset RESET_RTC>; 528}; 529 530&saradc { 531 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 532 clocks = <&clkc CLKID_XTAL>, 533 <&clkc CLKID_SAR_ADC>; 534 clock-names = "clkin", "core"; 535 amlogic,hhi-sysctrl = <&hhi>; 536 nvmem-cells = <&temperature_calib>; 537 nvmem-cell-names = "temperature_calib"; 538}; 539 540&sdio { 541 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 542 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 543 clock-names = "core", "clkin"; 544}; 545 546&spifc { 547 clocks = <&clkc CLKID_CLK81>; 548}; 549 550&timer_abcde { 551 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; 552 clock-names = "xtal", "pclk"; 553}; 554 555&uart_AO { 556 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 557 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; 558 clock-names = "baud", "xtal", "pclk"; 559}; 560 561&uart_A { 562 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 563 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; 564 clock-names = "baud", "xtal", "pclk"; 565}; 566 567&uart_B { 568 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 569 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; 570 clock-names = "baud", "xtal", "pclk"; 571}; 572 573&uart_C { 574 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 575 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; 576 clock-names = "baud", "xtal", "pclk"; 577}; 578 579&usb0 { 580 compatible = "amlogic,meson8-usb", "snps,dwc2"; 581 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 582 clock-names = "otg"; 583}; 584 585&usb1 { 586 compatible = "amlogic,meson8-usb", "snps,dwc2"; 587 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 588 clock-names = "otg"; 589}; 590 591&usb0_phy { 592 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 593 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 594 clock-names = "usb_general", "usb"; 595 resets = <&reset RESET_USB_OTG>; 596}; 597 598&usb1_phy { 599 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 600 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 601 clock-names = "usb_general", "usb"; 602 resets = <&reset RESET_USB_OTG>; 603}; 604