1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Erin Lo <erin.lo@mediatek.com> 5 * 6 */ 7 8/dts-v1/; 9#include "mt2701.dtsi" 10 11/ { 12 model = "MediaTek MT2701 evaluation board"; 13 compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; 14 15 memory { 16 device_type = "memory"; 17 reg = <0 0x80000000 0 0x40000000>; 18 }; 19 20 sound:sound { 21 compatible = "mediatek,mt2701-cs42448-machine"; 22 mediatek,platform = <&afe>; 23 /* CS42448 Machine name */ 24 audio-routing = 25 "Line Out Jack", "AOUT1L", 26 "Line Out Jack", "AOUT1R", 27 "Line Out Jack", "AOUT2L", 28 "Line Out Jack", "AOUT2R", 29 "Line Out Jack", "AOUT3L", 30 "Line Out Jack", "AOUT3R", 31 "Line Out Jack", "AOUT4L", 32 "Line Out Jack", "AOUT4R", 33 "AIN1L", "AMIC", 34 "AIN1R", "AMIC", 35 "AIN2L", "Tuner In", 36 "AIN2R", "Tuner In", 37 "AIN3L", "Satellite Tuner In", 38 "AIN3R", "Satellite Tuner In", 39 "AIN3L", "AUX In", 40 "AIN3R", "AUX In"; 41 mediatek,audio-codec = <&cs42448>; 42 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&aud_pins_default>; 45 i2s1-in-sel-gpio1 = <&pio 53 0>; 46 i2s1-in-sel-gpio2 = <&pio 54 0>; 47 status = "okay"; 48 }; 49 50 bt_sco_codec:bt_sco_codec { 51 compatible = "linux,bt-sco"; 52 }; 53 54 backlight_lcd: backlight_lcd { 55 compatible = "pwm-backlight"; 56 pwms = <&bls 0 100000>; 57 brightness-levels = < 58 0 16 32 48 64 80 96 112 59 128 144 160 176 192 208 224 240 60 255 61 >; 62 default-brightness-level = <9>; 63 }; 64}; 65 66&auxadc { 67 status = "okay"; 68}; 69 70&bls { 71 status = "okay"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pwm_bls_gpio>; 74}; 75 76&i2c0 { 77 pinctrl-names = "default"; 78 pinctrl-0 = <&i2c0_pins_a>; 79 status = "okay"; 80}; 81 82&i2c1 { 83 pinctrl-names = "default"; 84 pinctrl-0 = <&i2c1_pins_a>; 85 status = "okay"; 86}; 87 88&i2c2 { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&i2c2_pins_a>; 91 status = "okay"; 92 cs42448: cs42448@48 { 93 compatible = "cirrus,cs42448"; 94 reg = <0x48>; 95 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; 96 clock-names = "mclk"; 97 }; 98}; 99 100&pio { 101 i2c0_pins_a: i2c0@0 { 102 pins1 { 103 pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>, 104 <MT2701_PIN_76_SCL0__FUNC_SCL0>; 105 bias-disable; 106 }; 107 }; 108 109 i2c1_pins_a: i2c1@0 { 110 pins1 { 111 pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>, 112 <MT2701_PIN_58_SCL1__FUNC_SCL1>; 113 bias-disable; 114 }; 115 }; 116 117 i2c2_pins_a: i2c2@0 { 118 pins1 { 119 pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>, 120 <MT2701_PIN_78_SCL2__FUNC_SCL2>; 121 bias-disable; 122 }; 123 }; 124 125 pwm_bls_gpio: pwm_bls_gpio { 126 pins_cmd_dat { 127 pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>; 128 }; 129 }; 130 131 spi_pins_a: spi0@0 { 132 pins_spi { 133 pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>, 134 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>, 135 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>, 136 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>; 137 bias-disable; 138 }; 139 }; 140 141 aud_pins_default: audiodefault { 142 pins_cmd_dat { 143 pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>, 144 <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>, 145 <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>, 146 <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>, 147 <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>, 148 <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>, 149 <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>, 150 <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>, 151 <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>, 152 <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>, 153 <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>, 154 <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>, 155 <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>, 156 <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>, 157 <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>, 158 <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>, 159 <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>, 160 <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>; 161 drive-strength = <MTK_DRIVE_12mA>; 162 bias-pull-down; 163 }; 164 }; 165 166 spi_pins_b: spi1@0 { 167 pins_spi { 168 pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>, 169 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>, 170 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>, 171 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>; 172 bias-disable; 173 }; 174 }; 175 176 spi_pins_c: spi2@0 { 177 pins_spi { 178 pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>, 179 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>, 180 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>, 181 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>; 182 bias-disable; 183 }; 184 }; 185}; 186 187&spi0 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&spi_pins_a>; 190 status = "disabled"; 191}; 192 193&spi1 { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&spi_pins_b>; 196 status = "disabled"; 197}; 198 199&spi2 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&spi_pins_c>; 202 status = "disabled"; 203}; 204 205&nor_flash { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&nor_pins_default>; 208 status = "okay"; 209 flash@0 { 210 compatible = "jedec,spi-nor"; 211 reg = <0>; 212 }; 213}; 214 215&pio { 216 nor_pins_default: nor { 217 pins1 { 218 pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>, 219 <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>, 220 <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>, 221 <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>, 222 <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>, 223 <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>; 224 drive-strength = <MTK_DRIVE_4mA>; 225 bias-pull-up; 226 }; 227 }; 228}; 229 230&uart0 { 231 status = "okay"; 232}; 233