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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-apq8084.h>
5#include <dt-bindings/gpio/gpio.h>
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	model = "Qualcomm APQ 8084";
11	compatible = "qcom,apq8084";
12	interrupt-parent = <&intc>;
13
14	reserved-memory {
15		#address-cells = <1>;
16		#size-cells = <1>;
17		ranges;
18
19		smem_mem: smem_region@fa00000 {
20			reg = <0xfa00000 0x200000>;
21			no-map;
22		};
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			device_type = "cpu";
31			compatible = "qcom,krait";
32			reg = <0>;
33			enable-method = "qcom,kpss-acc-v2";
34			next-level-cache = <&L2>;
35			qcom,acc = <&acc0>;
36			qcom,saw = <&saw0>;
37			cpu-idle-states = <&CPU_SPC>;
38		};
39
40		cpu@1 {
41			device_type = "cpu";
42			compatible = "qcom,krait";
43			reg = <1>;
44			enable-method = "qcom,kpss-acc-v2";
45			next-level-cache = <&L2>;
46			qcom,acc = <&acc1>;
47			qcom,saw = <&saw1>;
48			cpu-idle-states = <&CPU_SPC>;
49		};
50
51		cpu@2 {
52			device_type = "cpu";
53			compatible = "qcom,krait";
54			reg = <2>;
55			enable-method = "qcom,kpss-acc-v2";
56			next-level-cache = <&L2>;
57			qcom,acc = <&acc2>;
58			qcom,saw = <&saw2>;
59			cpu-idle-states = <&CPU_SPC>;
60		};
61
62		cpu@3 {
63			device_type = "cpu";
64			compatible = "qcom,krait";
65			reg = <3>;
66			enable-method = "qcom,kpss-acc-v2";
67			next-level-cache = <&L2>;
68			qcom,acc = <&acc3>;
69			qcom,saw = <&saw3>;
70			cpu-idle-states = <&CPU_SPC>;
71		};
72
73		L2: l2-cache {
74			compatible = "qcom,arch-cache";
75			cache-level = <2>;
76			qcom,saw = <&saw_l2>;
77		};
78
79		idle-states {
80			CPU_SPC: spc {
81				compatible = "qcom,idle-state-spc",
82						"arm,idle-state";
83				entry-latency-us = <150>;
84				exit-latency-us = <200>;
85				min-residency-us = <2000>;
86			};
87		};
88	};
89
90	memory {
91		device_type = "memory";
92		reg = <0x0 0x0>;
93	};
94
95	firmware {
96		scm {
97			compatible = "qcom,scm";
98			clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
99			clock-names = "core", "bus", "iface";
100		};
101	};
102
103	thermal-zones {
104		cpu-thermal0 {
105			polling-delay-passive = <250>;
106			polling-delay = <1000>;
107
108			thermal-sensors = <&tsens 5>;
109
110			trips {
111				cpu_alert0: trip0 {
112					temperature = <75000>;
113					hysteresis = <2000>;
114					type = "passive";
115				};
116				cpu_crit0: trip1 {
117					temperature = <110000>;
118					hysteresis = <2000>;
119					type = "critical";
120				};
121			};
122		};
123
124		cpu-thermal1 {
125			polling-delay-passive = <250>;
126			polling-delay = <1000>;
127
128			thermal-sensors = <&tsens 6>;
129
130			trips {
131				cpu_alert1: trip0 {
132					temperature = <75000>;
133					hysteresis = <2000>;
134					type = "passive";
135				};
136				cpu_crit1: trip1 {
137					temperature = <110000>;
138					hysteresis = <2000>;
139					type = "critical";
140				};
141			};
142		};
143
144		cpu-thermal2 {
145			polling-delay-passive = <250>;
146			polling-delay = <1000>;
147
148			thermal-sensors = <&tsens 7>;
149
150			trips {
151				cpu_alert2: trip0 {
152					temperature = <75000>;
153					hysteresis = <2000>;
154					type = "passive";
155				};
156				cpu_crit2: trip1 {
157					temperature = <110000>;
158					hysteresis = <2000>;
159					type = "critical";
160				};
161			};
162		};
163
164		cpu-thermal3 {
165			polling-delay-passive = <250>;
166			polling-delay = <1000>;
167
168			thermal-sensors = <&tsens 8>;
169
170			trips {
171				cpu_alert3: trip0 {
172					temperature = <75000>;
173					hysteresis = <2000>;
174					type = "passive";
175				};
176				cpu_crit3: trip1 {
177					temperature = <110000>;
178					hysteresis = <2000>;
179					type = "critical";
180				};
181			};
182		};
183	};
184
185	cpu-pmu {
186		compatible = "qcom,krait-pmu";
187		interrupts = <1 7 0xf04>;
188	};
189
190	clocks {
191		xo_board: xo_board {
192			compatible = "fixed-clock";
193			#clock-cells = <0>;
194			clock-frequency = <19200000>;
195		};
196
197		sleep_clk: sleep_clk {
198			compatible = "fixed-clock";
199			#clock-cells = <0>;
200			clock-frequency = <32768>;
201		};
202	};
203
204	timer {
205		compatible = "arm,armv7-timer";
206		interrupts = <1 2 0xf08>,
207			     <1 3 0xf08>,
208			     <1 4 0xf08>,
209			     <1 1 0xf08>;
210		clock-frequency = <19200000>;
211	};
212
213	smem {
214		compatible = "qcom,smem";
215
216		qcom,rpm-msg-ram = <&rpm_msg_ram>;
217		memory-region = <&smem_mem>;
218
219		hwlocks = <&tcsr_mutex 3>;
220	};
221
222	soc: soc {
223		#address-cells = <1>;
224		#size-cells = <1>;
225		ranges;
226		compatible = "simple-bus";
227
228		intc: interrupt-controller@f9000000 {
229			compatible = "qcom,msm-qgic2";
230			interrupt-controller;
231			#interrupt-cells = <3>;
232			reg = <0xf9000000 0x1000>,
233			      <0xf9002000 0x1000>;
234		};
235
236		apcs: syscon@f9011000 {
237			compatible = "syscon";
238			reg = <0xf9011000 0x1000>;
239		};
240
241		qfprom: qfprom@fc4bc000 {
242			#address-cells = <1>;
243			#size-cells = <1>;
244			compatible = "qcom,qfprom";
245			reg = <0xfc4bc000 0x1000>;
246			tsens_calib: calib@d0 {
247				reg = <0xd0 0x18>;
248			};
249			tsens_backup: backup@440 {
250				reg = <0x440 0x10>;
251			};
252		};
253
254		tsens: thermal-sensor@fc4a8000 {
255			compatible = "qcom,msm8974-tsens";
256			reg = <0xfc4a8000 0x2000>;
257			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
258			nvmem-cell-names = "calib", "calib_backup";
259			#thermal-sensor-cells = <1>;
260		};
261
262		timer@f9020000 {
263			#address-cells = <1>;
264			#size-cells = <1>;
265			ranges;
266			compatible = "arm,armv7-timer-mem";
267			reg = <0xf9020000 0x1000>;
268			clock-frequency = <19200000>;
269
270			frame@f9021000 {
271				frame-number = <0>;
272				interrupts = <0 8 0x4>,
273					     <0 7 0x4>;
274				reg = <0xf9021000 0x1000>,
275				      <0xf9022000 0x1000>;
276			};
277
278			frame@f9023000 {
279				frame-number = <1>;
280				interrupts = <0 9 0x4>;
281				reg = <0xf9023000 0x1000>;
282				status = "disabled";
283			};
284
285			frame@f9024000 {
286				frame-number = <2>;
287				interrupts = <0 10 0x4>;
288				reg = <0xf9024000 0x1000>;
289				status = "disabled";
290			};
291
292			frame@f9025000 {
293				frame-number = <3>;
294				interrupts = <0 11 0x4>;
295				reg = <0xf9025000 0x1000>;
296				status = "disabled";
297			};
298
299			frame@f9026000 {
300				frame-number = <4>;
301				interrupts = <0 12 0x4>;
302				reg = <0xf9026000 0x1000>;
303				status = "disabled";
304			};
305
306			frame@f9027000 {
307				frame-number = <5>;
308				interrupts = <0 13 0x4>;
309				reg = <0xf9027000 0x1000>;
310				status = "disabled";
311			};
312
313			frame@f9028000 {
314				frame-number = <6>;
315				interrupts = <0 14 0x4>;
316				reg = <0xf9028000 0x1000>;
317				status = "disabled";
318			};
319		};
320
321		saw0: power-controller@f9089000 {
322			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
323			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
324		};
325
326		saw1: power-controller@f9099000 {
327			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
328			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
329		};
330
331		saw2: power-controller@f90a9000 {
332			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
333			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
334		};
335
336		saw3: power-controller@f90b9000 {
337			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
338			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
339		};
340
341		saw_l2: power-controller@f9012000 {
342			compatible = "qcom,saw2";
343			reg = <0xf9012000 0x1000>;
344			regulator;
345		};
346
347		acc0: clock-controller@f9088000 {
348			compatible = "qcom,kpss-acc-v2";
349			reg = <0xf9088000 0x1000>,
350			      <0xf9008000 0x1000>;
351		};
352
353		acc1: clock-controller@f9098000 {
354			compatible = "qcom,kpss-acc-v2";
355			reg = <0xf9098000 0x1000>,
356			      <0xf9008000 0x1000>;
357		};
358
359		acc2: clock-controller@f90a8000 {
360			compatible = "qcom,kpss-acc-v2";
361			reg = <0xf90a8000 0x1000>,
362			      <0xf9008000 0x1000>;
363		};
364
365		acc3: clock-controller@f90b8000 {
366			compatible = "qcom,kpss-acc-v2";
367			reg = <0xf90b8000 0x1000>,
368			      <0xf9008000 0x1000>;
369		};
370
371		restart@fc4ab000 {
372			compatible = "qcom,pshold";
373			reg = <0xfc4ab000 0x4>;
374		};
375
376		gcc: clock-controller@fc400000 {
377			compatible = "qcom,gcc-apq8084";
378			#clock-cells = <1>;
379			#reset-cells = <1>;
380			#power-domain-cells = <1>;
381			reg = <0xfc400000 0x4000>;
382		};
383
384		tcsr_mutex_regs: syscon@fd484000 {
385			compatible = "syscon";
386			reg = <0xfd484000 0x2000>;
387		};
388
389		tcsr_mutex: hwlock {
390			compatible = "qcom,tcsr-mutex";
391			syscon = <&tcsr_mutex_regs 0 0x80>;
392			#hwlock-cells = <1>;
393		};
394
395		rpm_msg_ram: memory@fc428000 {
396			compatible = "qcom,rpm-msg-ram";
397			reg = <0xfc428000 0x4000>;
398		};
399
400		tlmm: pinctrl@fd510000 {
401			compatible = "qcom,apq8084-pinctrl";
402			reg = <0xfd510000 0x4000>;
403			gpio-controller;
404			#gpio-cells = <2>;
405			interrupt-controller;
406			#interrupt-cells = <2>;
407			interrupts = <0 208 0>;
408		};
409
410		blsp2_uart2: serial@f995e000 {
411			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
412			reg = <0xf995e000 0x1000>;
413			interrupts = <0 114 0x0>;
414			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
415			clock-names = "core", "iface";
416			status = "disabled";
417		};
418
419		sdhci@f9824900 {
420			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
421			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
422			reg-names = "hc_mem", "core_mem";
423			interrupts = <0 123 0>, <0 138 0>;
424			interrupt-names = "hc_irq", "pwr_irq";
425			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
426				 <&gcc GCC_SDCC1_AHB_CLK>,
427				 <&xo_board>;
428			clock-names = "core", "iface", "xo";
429			status = "disabled";
430		};
431
432		sdhci@f98a4900 {
433			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
434			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
435			reg-names = "hc_mem", "core_mem";
436			interrupts = <0 125 0>, <0 221 0>;
437			interrupt-names = "hc_irq", "pwr_irq";
438			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
439				 <&gcc GCC_SDCC2_AHB_CLK>,
440				 <&xo_board>;
441			clock-names = "core", "iface", "xo";
442			status = "disabled";
443		};
444
445		spmi_bus: spmi@fc4cf000 {
446			compatible = "qcom,spmi-pmic-arb";
447			reg-names = "core", "intr", "cnfg";
448			reg = <0xfc4cf000 0x1000>,
449			      <0xfc4cb000 0x1000>,
450			      <0xfc4ca000 0x1000>;
451			interrupt-names = "periph_irq";
452			interrupts = <0 190 0>;
453			qcom,ee = <0>;
454			qcom,channel = <0>;
455			#address-cells = <2>;
456			#size-cells = <0>;
457			interrupt-controller;
458			#interrupt-cells = <4>;
459		};
460	};
461
462	smd {
463		compatible = "qcom,smd";
464
465		rpm {
466			interrupts = <0 168 1>;
467			qcom,ipc = <&apcs 8 0>;
468			qcom,smd-edge = <15>;
469
470			rpm_requests {
471				compatible = "qcom,rpm-apq8084";
472				qcom,smd-channels = "rpm_requests";
473
474				pma8084-regulators {
475					compatible = "qcom,rpm-pma8084-regulators";
476
477					pma8084_s1: s1 {};
478					pma8084_s2: s2 {};
479					pma8084_s3: s3 {};
480					pma8084_s4: s4 {};
481					pma8084_s5: s5 {};
482					pma8084_s6: s6 {};
483					pma8084_s7: s7 {};
484					pma8084_s8: s8 {};
485					pma8084_s9: s9 {};
486					pma8084_s10: s10 {};
487					pma8084_s11: s11 {};
488					pma8084_s12: s12 {};
489
490					pma8084_l1: l1 {};
491					pma8084_l2: l2 {};
492					pma8084_l3: l3 {};
493					pma8084_l4: l4 {};
494					pma8084_l5: l5 {};
495					pma8084_l6: l6 {};
496					pma8084_l7: l7 {};
497					pma8084_l8: l8 {};
498					pma8084_l9: l9 {};
499					pma8084_l10: l10 {};
500					pma8084_l11: l11 {};
501					pma8084_l12: l12 {};
502					pma8084_l13: l13 {};
503					pma8084_l14: l14 {};
504					pma8084_l15: l15 {};
505					pma8084_l16: l16 {};
506					pma8084_l17: l17 {};
507					pma8084_l18: l18 {};
508					pma8084_l19: l19 {};
509					pma8084_l20: l20 {};
510					pma8084_l21: l21 {};
511					pma8084_l22: l22 {};
512					pma8084_l23: l23 {};
513					pma8084_l24: l24 {};
514					pma8084_l25: l25 {};
515					pma8084_l26: l26 {};
516					pma8084_l27: l27 {};
517
518					pma8084_lvs1: lvs1 {};
519					pma8084_lvs2: lvs2 {};
520					pma8084_lvs3: lvs3 {};
521					pma8084_lvs4: lvs4 {};
522
523					pma8084_5vs1: 5vs1 {};
524				};
525			};
526		};
527	};
528};
529