1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mach-pxa/cm-x255.c
4 *
5 * Copyright (C) 2007, 2008 CompuLab, Ltd.
6 * Mike Rapoport <mike@compulab.co.il>
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/irq.h>
11 #include <linux/mtd/partitions.h>
12 #include <linux/mtd/physmap.h>
13 #include <linux/mtd/nand-gpio.h>
14 #include <linux/gpio/machine.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/pxa2xx_spi.h>
17
18 #include <asm/mach/arch.h>
19 #include <asm/mach-types.h>
20 #include <asm/mach/map.h>
21
22 #include "pxa25x.h"
23
24 #include "generic.h"
25
26 #define GPIO_NAND_CS (5)
27 #define GPIO_NAND_ALE (4)
28 #define GPIO_NAND_CLE (3)
29 #define GPIO_NAND_RB (10)
30
31 static unsigned long cmx255_pin_config[] = {
32 /* AC'97 */
33 GPIO28_AC97_BITCLK,
34 GPIO29_AC97_SDATA_IN_0,
35 GPIO30_AC97_SDATA_OUT,
36 GPIO31_AC97_SYNC,
37
38 /* BTUART */
39 GPIO42_BTUART_RXD,
40 GPIO43_BTUART_TXD,
41 GPIO44_BTUART_CTS,
42 GPIO45_BTUART_RTS,
43
44 /* STUART */
45 GPIO46_STUART_RXD,
46 GPIO47_STUART_TXD,
47
48 /* LCD */
49 GPIOxx_LCD_TFT_16BPP,
50
51 /* SSP1 */
52 GPIO23_SSP1_SCLK,
53 GPIO24_SSP1_SFRM,
54 GPIO25_SSP1_TXD,
55 GPIO26_SSP1_RXD,
56
57 /* SSP2 */
58 GPIO81_SSP2_CLK_OUT,
59 GPIO82_SSP2_FRM_OUT,
60 GPIO83_SSP2_TXD,
61 GPIO84_SSP2_RXD,
62
63 /* PC Card */
64 GPIO48_nPOE,
65 GPIO49_nPWE,
66 GPIO50_nPIOR,
67 GPIO51_nPIOW,
68 GPIO52_nPCE_1,
69 GPIO53_nPCE_2,
70 GPIO54_nPSKTSEL,
71 GPIO55_nPREG,
72 GPIO56_nPWAIT,
73 GPIO57_nIOIS16,
74
75 /* SDRAM and local bus */
76 GPIO15_nCS_1,
77 GPIO78_nCS_2,
78 GPIO79_nCS_3,
79 GPIO80_nCS_4,
80 GPIO33_nCS_5,
81 GPIO18_RDY,
82
83 /* GPIO */
84 GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
85 GPIO9_GPIO, /* PC card reset */
86
87 /* NAND controls */
88 GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
89 GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */
90 GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */
91 GPIO10_GPIO, /* NAND Ready/Busy */
92
93 /* interrupts */
94 GPIO22_GPIO, /* DM9000 interrupt */
95 };
96
97 #if defined(CONFIG_SPI_PXA2XX)
98 static struct pxa2xx_spi_controller pxa_ssp_master_info = {
99 .num_chipselect = 1,
100 };
101
102 static struct spi_board_info spi_board_info[] __initdata = {
103 [0] = {
104 .modalias = "rtc-max6902",
105 .max_speed_hz = 1000000,
106 .bus_num = 1,
107 .chip_select = 0,
108 },
109 };
110
cmx255_init_rtc(void)111 static void __init cmx255_init_rtc(void)
112 {
113 pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
114 spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
115 }
116 #else
cmx255_init_rtc(void)117 static inline void cmx255_init_rtc(void) {}
118 #endif
119
120 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
121 static struct mtd_partition cmx255_nor_partitions[] = {
122 {
123 .name = "ARMmon",
124 .size = 0x00030000,
125 .offset = 0,
126 .mask_flags = MTD_WRITEABLE /* force read-only */
127 } , {
128 .name = "ARMmon setup block",
129 .size = 0x00010000,
130 .offset = MTDPART_OFS_APPEND,
131 .mask_flags = MTD_WRITEABLE /* force read-only */
132 } , {
133 .name = "kernel",
134 .size = 0x00160000,
135 .offset = MTDPART_OFS_APPEND,
136 } , {
137 .name = "ramdisk",
138 .size = MTDPART_SIZ_FULL,
139 .offset = MTDPART_OFS_APPEND
140 }
141 };
142
143 static struct physmap_flash_data cmx255_nor_flash_data[] = {
144 {
145 .width = 2, /* bankwidth in bytes */
146 .parts = cmx255_nor_partitions,
147 .nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
148 }
149 };
150
151 static struct resource cmx255_nor_resource = {
152 .start = PXA_CS0_PHYS,
153 .end = PXA_CS0_PHYS + SZ_8M - 1,
154 .flags = IORESOURCE_MEM,
155 };
156
157 static struct platform_device cmx255_nor = {
158 .name = "physmap-flash",
159 .id = -1,
160 .dev = {
161 .platform_data = cmx255_nor_flash_data,
162 },
163 .resource = &cmx255_nor_resource,
164 .num_resources = 1,
165 };
166
cmx255_init_nor(void)167 static void __init cmx255_init_nor(void)
168 {
169 platform_device_register(&cmx255_nor);
170 }
171 #else
cmx255_init_nor(void)172 static inline void cmx255_init_nor(void) {}
173 #endif
174
175 #if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
176
177 static struct gpiod_lookup_table cmx255_nand_gpiod_table = {
178 .dev_id = "gpio-nand",
179 .table = {
180 GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CS, "nce", GPIO_ACTIVE_HIGH),
181 GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CLE, "cle", GPIO_ACTIVE_HIGH),
182 GPIO_LOOKUP("gpio-pxa", GPIO_NAND_ALE, "ale", GPIO_ACTIVE_HIGH),
183 GPIO_LOOKUP("gpio-pxa", GPIO_NAND_RB, "rdy", GPIO_ACTIVE_HIGH),
184 },
185 };
186
187 static struct resource cmx255_nand_resource[] = {
188 [0] = {
189 .start = PXA_CS1_PHYS,
190 .end = PXA_CS1_PHYS + 11,
191 .flags = IORESOURCE_MEM,
192 },
193 [1] = {
194 .start = PXA_CS5_PHYS,
195 .end = PXA_CS5_PHYS + 3,
196 .flags = IORESOURCE_MEM,
197 },
198 };
199
200 static struct mtd_partition cmx255_nand_parts[] = {
201 [0] = {
202 .name = "cmx255-nand",
203 .size = MTDPART_SIZ_FULL,
204 .offset = 0,
205 },
206 };
207
208 static struct gpio_nand_platdata cmx255_nand_platdata = {
209 .parts = cmx255_nand_parts,
210 .num_parts = ARRAY_SIZE(cmx255_nand_parts),
211 .chip_delay = 25,
212 };
213
214 static struct platform_device cmx255_nand = {
215 .name = "gpio-nand",
216 .num_resources = ARRAY_SIZE(cmx255_nand_resource),
217 .resource = cmx255_nand_resource,
218 .id = -1,
219 .dev = {
220 .platform_data = &cmx255_nand_platdata,
221 }
222 };
223
cmx255_init_nand(void)224 static void __init cmx255_init_nand(void)
225 {
226 gpiod_add_lookup_table(&cmx255_nand_gpiod_table);
227 platform_device_register(&cmx255_nand);
228 }
229 #else
cmx255_init_nand(void)230 static inline void cmx255_init_nand(void) {}
231 #endif
232
cmx255_init(void)233 void __init cmx255_init(void)
234 {
235 pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
236
237 cmx255_init_rtc();
238 cmx255_init_nor();
239 cmx255_init_nand();
240 }
241