1; SPDX-License-Identifier: GPL-2.0-only 2; 3; Port on Texas Instruments TMS320C6x architecture 4; 5; Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated 6; Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) 7; 8; This section handles all the interrupt vector routines. 9; At RESET the processor sets up the DRAM timing parameters and 10; branches to the label _c_int00 which handles initialization for the C code. 11; 12 13#define ALIGNMENT 5 14 15 .macro IRQVEC name, handler 16 .align ALIGNMENT 17 .hidden \name 18 .global \name 19\name: 20#ifdef CONFIG_C6X_BIG_KERNEL 21 STW .D2T1 A0,*B15--[2] 22 || MVKL .S1 \handler,A0 23 MVKH .S1 \handler,A0 24 B .S2X A0 25 LDW .D2T1 *++B15[2],A0 26 NOP 4 27 NOP 28 NOP 29 .endm 30#else /* CONFIG_C6X_BIG_KERNEL */ 31 B .S2 \handler 32 NOP 33 NOP 34 NOP 35 NOP 36 NOP 37 NOP 38 NOP 39 .endm 40#endif /* CONFIG_C6X_BIG_KERNEL */ 41 42 .sect ".vectors","ax" 43 .align ALIGNMENT 44 .global RESET 45 .hidden RESET 46RESET: 47#ifdef CONFIG_C6X_BIG_KERNEL 48 MVKL .S1 _c_int00,A0 ; branch to _c_int00 49 MVKH .S1 _c_int00,A0 50 B .S2X A0 51#else 52 B .S2 _c_int00 53 NOP 54 NOP 55#endif 56 NOP 57 NOP 58 NOP 59 NOP 60 NOP 61 62 63 IRQVEC NMI,_nmi_handler ; NMI interrupt 64 IRQVEC AINT,_bad_interrupt ; reserved 65 IRQVEC MSGINT,_bad_interrupt ; reserved 66 67 IRQVEC INT4,_int4_handler 68 IRQVEC INT5,_int5_handler 69 IRQVEC INT6,_int6_handler 70 IRQVEC INT7,_int7_handler 71 IRQVEC INT8,_int8_handler 72 IRQVEC INT9,_int9_handler 73 IRQVEC INT10,_int10_handler 74 IRQVEC INT11,_int11_handler 75 IRQVEC INT12,_int12_handler 76 IRQVEC INT13,_int13_handler 77 IRQVEC INT14,_int14_handler 78 IRQVEC INT15,_int15_handler 79