1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * platform.c: platform support for PNX833X.
4 *
5 * Copyright 2008 NXP Semiconductors
6 * Chris Steel <chris.steel@nxp.com>
7 * Daniel Laird <daniel.j.laird@nxp.com>
8 *
9 * Based on software written by:
10 * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
11 */
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/platform_device.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/resource.h>
18 #include <linux/serial.h>
19 #include <linux/serial_pnx8xxx.h>
20 #include <linux/mtd/platnand.h>
21
22 #include <irq.h>
23 #include <irq-mapping.h>
24 #include <pnx833x.h>
25
26 static u64 uart_dmamask = DMA_BIT_MASK(32);
27
28 static struct resource pnx833x_uart_resources[] = {
29 [0] = {
30 .start = PNX833X_UART0_PORTS_START,
31 .end = PNX833X_UART0_PORTS_END,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = PNX833X_PIC_UART0_INT,
36 .end = PNX833X_PIC_UART0_INT,
37 .flags = IORESOURCE_IRQ,
38 },
39 [2] = {
40 .start = PNX833X_UART1_PORTS_START,
41 .end = PNX833X_UART1_PORTS_END,
42 .flags = IORESOURCE_MEM,
43 },
44 [3] = {
45 .start = PNX833X_PIC_UART1_INT,
46 .end = PNX833X_PIC_UART1_INT,
47 .flags = IORESOURCE_IRQ,
48 },
49 };
50
51 struct pnx8xxx_port pnx8xxx_ports[] = {
52 [0] = {
53 .port = {
54 .type = PORT_PNX8XXX,
55 .iotype = UPIO_MEM,
56 .membase = (void __iomem *)PNX833X_UART0_PORTS_START,
57 .mapbase = PNX833X_UART0_PORTS_START,
58 .irq = PNX833X_PIC_UART0_INT,
59 .uartclk = 3692300,
60 .fifosize = 16,
61 .flags = UPF_BOOT_AUTOCONF,
62 .line = 0,
63 },
64 },
65 [1] = {
66 .port = {
67 .type = PORT_PNX8XXX,
68 .iotype = UPIO_MEM,
69 .membase = (void __iomem *)PNX833X_UART1_PORTS_START,
70 .mapbase = PNX833X_UART1_PORTS_START,
71 .irq = PNX833X_PIC_UART1_INT,
72 .uartclk = 3692300,
73 .fifosize = 16,
74 .flags = UPF_BOOT_AUTOCONF,
75 .line = 1,
76 },
77 },
78 };
79
80 static struct platform_device pnx833x_uart_device = {
81 .name = "pnx8xxx-uart",
82 .id = -1,
83 .dev = {
84 .dma_mask = &uart_dmamask,
85 .coherent_dma_mask = DMA_BIT_MASK(32),
86 .platform_data = pnx8xxx_ports,
87 },
88 .num_resources = ARRAY_SIZE(pnx833x_uart_resources),
89 .resource = pnx833x_uart_resources,
90 };
91
92 static u64 ehci_dmamask = DMA_BIT_MASK(32);
93
94 static struct resource pnx833x_usb_ehci_resources[] = {
95 [0] = {
96 .start = PNX833X_USB_PORTS_START,
97 .end = PNX833X_USB_PORTS_END,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = PNX833X_PIC_USB_INT,
102 .end = PNX833X_PIC_USB_INT,
103 .flags = IORESOURCE_IRQ,
104 },
105 };
106
107 static struct platform_device pnx833x_usb_ehci_device = {
108 .name = "pnx833x-ehci",
109 .id = -1,
110 .dev = {
111 .dma_mask = &ehci_dmamask,
112 .coherent_dma_mask = DMA_BIT_MASK(32),
113 },
114 .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
115 .resource = pnx833x_usb_ehci_resources,
116 };
117
118 static u64 ethernet_dmamask = DMA_BIT_MASK(32);
119
120 static struct resource pnx833x_ethernet_resources[] = {
121 [0] = {
122 .start = PNX8335_IP3902_PORTS_START,
123 .end = PNX8335_IP3902_PORTS_END,
124 .flags = IORESOURCE_MEM,
125 },
126 #ifdef CONFIG_SOC_PNX8335
127 [1] = {
128 .start = PNX8335_PIC_ETHERNET_INT,
129 .end = PNX8335_PIC_ETHERNET_INT,
130 .flags = IORESOURCE_IRQ,
131 },
132 #endif
133 };
134
135 static struct platform_device pnx833x_ethernet_device = {
136 .name = "ip3902-eth",
137 .id = -1,
138 .dev = {
139 .dma_mask = ðernet_dmamask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 },
142 .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
143 .resource = pnx833x_ethernet_resources,
144 };
145
146 static struct resource pnx833x_sata_resources[] = {
147 [0] = {
148 .start = PNX8335_SATA_PORTS_START,
149 .end = PNX8335_SATA_PORTS_END,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
153 .start = PNX8335_PIC_SATA_INT,
154 .end = PNX8335_PIC_SATA_INT,
155 .flags = IORESOURCE_IRQ,
156 },
157 };
158
159 static struct platform_device pnx833x_sata_device = {
160 .name = "pnx833x-sata",
161 .id = -1,
162 .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
163 .resource = pnx833x_sata_resources,
164 };
165
166 static void
pnx833x_flash_nand_cmd_ctrl(struct nand_chip * this,int cmd,unsigned int ctrl)167 pnx833x_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
168 {
169 unsigned long nandaddr = (unsigned long)this->legacy.IO_ADDR_W;
170
171 if (cmd == NAND_CMD_NONE)
172 return;
173
174 if (ctrl & NAND_CLE)
175 writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
176 else
177 writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
178 }
179
180 static struct platform_nand_data pnx833x_flash_nand_data = {
181 .chip = {
182 .nr_chips = 1,
183 .chip_delay = 25,
184 },
185 .ctrl = {
186 .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl
187 }
188 };
189
190 /*
191 * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
192 * 12 bytes more seems to be the standard that allows for NAND access.
193 */
194 static struct resource pnx833x_flash_nand_resource = {
195 .start = PNX8335_NAND_BASE,
196 .end = PNX8335_NAND_BASE + 12,
197 .flags = IORESOURCE_MEM,
198 };
199
200 static struct platform_device pnx833x_flash_nand = {
201 .name = "gen_nand",
202 .id = -1,
203 .num_resources = 1,
204 .resource = &pnx833x_flash_nand_resource,
205 .dev = {
206 .platform_data = &pnx833x_flash_nand_data,
207 },
208 };
209
210 static struct platform_device *pnx833x_platform_devices[] __initdata = {
211 &pnx833x_uart_device,
212 &pnx833x_usb_ehci_device,
213 &pnx833x_ethernet_device,
214 &pnx833x_sata_device,
215 &pnx833x_flash_nand,
216 };
217
pnx833x_platform_init(void)218 static int __init pnx833x_platform_init(void)
219 {
220 return platform_add_devices(pnx833x_platform_devices,
221 ARRAY_SIZE(pnx833x_platform_devices));
222 }
223
224 arch_initcall(pnx833x_platform_init);
225