1/* 2 * MPC8569 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; 39 interrupts = <19 2 0 0>; 40 sleep = <&pmc 0x08000000>; 41}; 42 43/* controller at 0xa000 */ 44&pci1 { 45 compatible = "fsl,mpc8548-pcie"; 46 device_type = "pci"; 47 #size-cells = <2>; 48 #address-cells = <3>; 49 bus-range = <0 255>; 50 clock-frequency = <33333333>; 51 interrupts = <26 2 0 0>; 52 sleep = <&pmc 0x20000000>; 53 54 pcie@0 { 55 reg = <0 0 0 0 0>; 56 #interrupt-cells = <1>; 57 #size-cells = <2>; 58 #address-cells = <3>; 59 device_type = "pci"; 60 interrupts = <26 2 0 0>; 61 interrupt-map-mask = <0xf800 0 0 7>; 62 interrupt-map = < 63 /* IDSEL 0x0 */ 64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 68 >; 69 }; 70}; 71 72&rio { 73 compatible = "fsl,srio"; 74 interrupts = <48 2 0 0>; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 fsl,srio-rmu-handle = <&rmu>; 78 sleep = <&pmc 0x00080000>; 79 ranges; 80 81 port1 { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 cell-index = <1>; 85 }; 86 87 port2 { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 cell-index = <2>; 91 }; 92}; 93 94&soc { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 compatible = "fsl,mpc8569-immr", "simple-bus"; 99 bus-frequency = <0>; // Filled out by uboot. 100 101 ecm-law@0 { 102 compatible = "fsl,ecm-law"; 103 reg = <0x0 0x1000>; 104 fsl,num-laws = <10>; 105 }; 106 107 ecm@1000 { 108 compatible = "fsl,mpc8569-ecm", "fsl,ecm"; 109 reg = <0x1000 0x1000>; 110 interrupts = <17 2 0 0>; 111 }; 112 113 memory-controller@2000 { 114 compatible = "fsl,mpc8569-memory-controller"; 115 reg = <0x2000 0x1000>; 116 interrupts = <18 2 0 0>; 117 }; 118 119 i2c-sleep-nexus { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 compatible = "simple-bus"; 123 sleep = <&pmc 0x00000004>; 124 ranges; 125 126/include/ "pq3-i2c-0.dtsi" 127/include/ "pq3-i2c-1.dtsi" 128 129 }; 130 131 duart-sleep-nexus { 132 #address-cells = <1>; 133 #size-cells = <1>; 134 compatible = "simple-bus"; 135 sleep = <&pmc 0x00000002>; 136 ranges; 137 138/include/ "pq3-duart-0.dtsi" 139 140 }; 141 142 L2: l2-cache-controller@20000 { 143 compatible = "fsl,mpc8569-l2-cache-controller"; 144 reg = <0x20000 0x1000>; 145 cache-line-size = <32>; // 32 bytes 146 cache-size = <0x80000>; // L2, 512K 147 interrupts = <16 2 0 0>; 148 }; 149 150/include/ "pq3-dma-0.dtsi" 151/include/ "pq3-esdhc-0.dtsi" 152 sdhc@2e000 { 153 sleep = <&pmc 0x00200000>; 154 }; 155 156 par_io@e0100 { 157 #address-cells = <1>; 158 #size-cells = <1>; 159 reg = <0xe0100 0x100>; 160 ranges = <0x0 0xe0100 0x100>; 161 device_type = "par_io"; 162 }; 163 164/include/ "pq3-sec3.1-0.dtsi" 165 crypto@30000 { 166 sleep = <&pmc 0x01000000>; 167 }; 168 169/include/ "pq3-mpic.dtsi" 170/include/ "pq3-rmu-0.dtsi" 171 rmu@d3000 { 172 sleep = <&pmc 0x00040000>; 173 }; 174 175 global-utilities@e0000 { 176 #address-cells = <1>; 177 #size-cells = <1>; 178 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts"; 179 reg = <0xe0000 0x1000>; 180 ranges = <0 0xe0000 0x1000>; 181 fsl,has-rstcr; 182 183 pmc: power@70 { 184 compatible = "fsl,mpc8569-pmc", 185 "fsl,mpc8548-pmc"; 186 reg = <0x70 0x20>; 187 }; 188 }; 189}; 190 191&qe { 192 #address-cells = <1>; 193 #size-cells = <1>; 194 device_type = "qe"; 195 compatible = "fsl,qe"; 196 sleep = <&pmc 0x00000800>; 197 brg-frequency = <0>; 198 bus-frequency = <0>; 199 fsl,qe-num-riscs = <4>; 200 fsl,qe-num-snums = <46>; 201 202 qeic: interrupt-controller@80 { 203 interrupt-controller; 204 compatible = "fsl,qe-ic"; 205 #address-cells = <0>; 206 #interrupt-cells = <1>; 207 reg = <0x80 0x80>; 208 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30 209 interrupt-parent = <&mpic>; 210 }; 211 212 timer@440 { 213 compatible = "fsl,mpc8569-qe-gtm", 214 "fsl,qe-gtm", "fsl,gtm"; 215 reg = <0x440 0x40>; 216 interrupts = <12 13 14 15>; 217 interrupt-parent = <&qeic>; 218 /* Filled in by U-Boot */ 219 clock-frequency = <0>; 220 }; 221 222 spi@4c0 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; 226 reg = <0x4c0 0x40>; 227 cell-index = <0>; 228 interrupts = <2>; 229 interrupt-parent = <&qeic>; 230 }; 231 232 spi@500 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 cell-index = <1>; 236 compatible = "fsl,spi"; 237 reg = <0x500 0x40>; 238 interrupts = <1>; 239 interrupt-parent = <&qeic>; 240 }; 241 242 usb@6c0 { 243 compatible = "fsl,mpc8569-qe-usb", 244 "fsl,mpc8323-qe-usb"; 245 reg = <0x6c0 0x40 0x8b00 0x100>; 246 interrupts = <11>; 247 interrupt-parent = <&qeic>; 248 }; 249 250 ucc@2000 { 251 cell-index = <1>; 252 reg = <0x2000 0x200>; 253 interrupts = <32>; 254 interrupt-parent = <&qeic>; 255 }; 256 257 ucc@2200 { 258 cell-index = <3>; 259 reg = <0x2200 0x200>; 260 interrupts = <34>; 261 interrupt-parent = <&qeic>; 262 }; 263 264 ucc@3000 { 265 cell-index = <2>; 266 reg = <0x3000 0x200>; 267 interrupts = <33>; 268 interrupt-parent = <&qeic>; 269 }; 270 271 ucc@3200 { 272 cell-index = <4>; 273 reg = <0x3200 0x200>; 274 interrupts = <35>; 275 interrupt-parent = <&qeic>; 276 }; 277 278 ucc@3400 { 279 cell-index = <6>; 280 reg = <0x3400 0x200>; 281 interrupts = <41>; 282 interrupt-parent = <&qeic>; 283 }; 284 285 ucc@3600 { 286 cell-index = <8>; 287 reg = <0x3600 0x200>; 288 interrupts = <43>; 289 interrupt-parent = <&qeic>; 290 }; 291 292 muram@10000 { 293 #address-cells = <1>; 294 #size-cells = <1>; 295 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 296 ranges = <0x0 0x10000 0x20000>; 297 298 data-only@0 { 299 compatible = "fsl,qe-muram-data", 300 "fsl,cpm-muram-data"; 301 reg = <0x0 0x20000>; 302 }; 303 }; 304}; 305