1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * vDSO provided cache flush routines 4 * 5 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), 6 * IBM Corp. 7 */ 8#include <asm/processor.h> 9#include <asm/ppc_asm.h> 10#include <asm/vdso.h> 11#include <asm/asm-offsets.h> 12 13 .text 14 15/* 16 * Default "generic" version of __kernel_sync_dicache. 17 * 18 * void __kernel_sync_dicache(unsigned long start, unsigned long end) 19 * 20 * Flushes the data cache & invalidate the instruction cache for the 21 * provided range [start, end[ 22 */ 23V_FUNCTION_BEGIN(__kernel_sync_dicache) 24 .cfi_startproc 25 mflr r12 26 .cfi_register lr,r12 27 mr r11,r3 28 bl V_LOCAL_FUNC(__get_datapage) 29 mtlr r12 30 mr r10,r3 31 32 lwz r7,CFG_DCACHE_BLOCKSZ(r10) 33 addi r5,r7,-1 34 andc r6,r11,r5 /* round low to line bdy */ 35 subf r8,r6,r4 /* compute length */ 36 add r8,r8,r5 /* ensure we get enough */ 37 lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10) 38 srd. r8,r8,r9 /* compute line count */ 39 crclr cr0*4+so 40 beqlr /* nothing to do? */ 41 mtctr r8 421: dcbst 0,r6 43 add r6,r6,r7 44 bdnz 1b 45 sync 46 47/* Now invalidate the instruction cache */ 48 49 lwz r7,CFG_ICACHE_BLOCKSZ(r10) 50 addi r5,r7,-1 51 andc r6,r11,r5 /* round low to line bdy */ 52 subf r8,r6,r4 /* compute length */ 53 add r8,r8,r5 54 lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10) 55 srd. r8,r8,r9 /* compute line count */ 56 crclr cr0*4+so 57 beqlr /* nothing to do? */ 58 mtctr r8 592: icbi 0,r6 60 add r6,r6,r7 61 bdnz 2b 62 isync 63 li r3,0 64 blr 65 .cfi_endproc 66V_FUNCTION_END(__kernel_sync_dicache) 67 68 69/* 70 * POWER5 version of __kernel_sync_dicache 71 */ 72V_FUNCTION_BEGIN(__kernel_sync_dicache_p5) 73 .cfi_startproc 74 crclr cr0*4+so 75 sync 76 isync 77 li r3,0 78 blr 79 .cfi_endproc 80V_FUNCTION_END(__kernel_sync_dicache_p5) 81