1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/sh/mach-cayman/setup.c
4 *
5 * SH5 Cayman support
6 *
7 * Copyright (C) 2002 David J. Mckay & Benedict Gaster
8 * Copyright (C) 2003 - 2007 Paul Mundt
9 */
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <cpu/irq.h>
14
15 /*
16 * Platform Dependent Interrupt Priorities.
17 */
18
19 /* Using defaults defined in irq.h */
20 #define RES NO_PRIORITY /* Disabled */
21 #define IR0 IRL0_PRIORITY /* IRLs */
22 #define IR1 IRL1_PRIORITY
23 #define IR2 IRL2_PRIORITY
24 #define IR3 IRL3_PRIORITY
25 #define PCA INTA_PRIORITY /* PCI Ints */
26 #define PCB INTB_PRIORITY
27 #define PCC INTC_PRIORITY
28 #define PCD INTD_PRIORITY
29 #define SER TOP_PRIORITY
30 #define ERR TOP_PRIORITY
31 #define PW0 TOP_PRIORITY
32 #define PW1 TOP_PRIORITY
33 #define PW2 TOP_PRIORITY
34 #define PW3 TOP_PRIORITY
35 #define DM0 NO_PRIORITY /* DMA Ints */
36 #define DM1 NO_PRIORITY
37 #define DM2 NO_PRIORITY
38 #define DM3 NO_PRIORITY
39 #define DAE NO_PRIORITY
40 #define TU0 TIMER_PRIORITY /* TMU Ints */
41 #define TU1 NO_PRIORITY
42 #define TU2 NO_PRIORITY
43 #define TI2 NO_PRIORITY
44 #define ATI NO_PRIORITY /* RTC Ints */
45 #define PRI NO_PRIORITY
46 #define CUI RTC_PRIORITY
47 #define ERI SCIF_PRIORITY /* SCIF Ints */
48 #define RXI SCIF_PRIORITY
49 #define BRI SCIF_PRIORITY
50 #define TXI SCIF_PRIORITY
51 #define ITI TOP_PRIORITY /* WDT Ints */
52
53 /* Setup for the SMSC FDC37C935 */
54 #define SMSC_SUPERIO_BASE 0x04000000
55 #define SMSC_CONFIG_PORT_ADDR 0x3f0
56 #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
57 #define SMSC_DATA_PORT_ADDR 0x3f1
58
59 #define SMSC_ENTER_CONFIG_KEY 0x55
60 #define SMSC_EXIT_CONFIG_KEY 0xaa
61
62 #define SMCS_LOGICAL_DEV_INDEX 0x07
63 #define SMSC_DEVICE_ID_INDEX 0x20
64 #define SMSC_DEVICE_REV_INDEX 0x21
65 #define SMSC_ACTIVATE_INDEX 0x30
66 #define SMSC_PRIMARY_BASE_INDEX 0x60
67 #define SMSC_SECONDARY_BASE_INDEX 0x62
68 #define SMSC_PRIMARY_INT_INDEX 0x70
69 #define SMSC_SECONDARY_INT_INDEX 0x72
70
71 #define SMSC_IDE1_DEVICE 1
72 #define SMSC_KEYBOARD_DEVICE 7
73 #define SMSC_CONFIG_REGISTERS 8
74
75 #define SMSC_SUPERIO_READ_INDEXED(index) ({ \
76 outb((index), SMSC_INDEX_PORT_ADDR); \
77 inb(SMSC_DATA_PORT_ADDR); })
78 #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
79 outb((index), SMSC_INDEX_PORT_ADDR); \
80 outb((val), SMSC_DATA_PORT_ADDR); })
81
82 #define IDE1_PRIMARY_BASE 0x01f0
83 #define IDE1_SECONDARY_BASE 0x03f6
84
85 unsigned long smsc_superio_virt;
86
87 int platform_int_priority[NR_INTC_IRQS] = {
88 IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */
89 RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */
90 PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
91 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
92 TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
93 RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
94 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
95 RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
96 };
97
smsc_superio_setup(void)98 static int __init smsc_superio_setup(void)
99 {
100 unsigned char devid, devrev;
101
102 smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
103 if (!smsc_superio_virt) {
104 panic("Unable to remap SMSC SuperIO\n");
105 }
106
107 /* Initially the chip is in run state */
108 /* Put it into configuration state */
109 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
110 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
111
112 /* Read device ID info */
113 devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
114 devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
115 printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
116
117 /* Select the keyboard device */
118 SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
119
120 /* enable it */
121 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
122
123 /* Select the interrupts */
124 /* On a PC keyboard is IRQ1, mouse is IRQ12 */
125 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
126 SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
127
128 /*
129 * Only IDE1 exists on the Cayman
130 */
131
132 /* Power it on */
133 SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
134
135 SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
136 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
137
138 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
139 SMSC_PRIMARY_BASE_INDEX + 0);
140 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
141 SMSC_PRIMARY_BASE_INDEX + 1);
142
143 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
144 SMSC_SECONDARY_BASE_INDEX + 0);
145 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
146 SMSC_SECONDARY_BASE_INDEX + 1);
147
148 SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
149
150 SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
151 SMCS_LOGICAL_DEV_INDEX);
152
153 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
154 SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
155 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
156 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
157
158 /* Exit the configuration state */
159 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
160
161 return 0;
162 }
163 device_initcall(smsc_superio_setup);
164
cayman_ioport_map(unsigned long port,unsigned int len)165 static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len)
166 {
167 if (port < 0x400) {
168 extern unsigned long smsc_superio_virt;
169 return (void __iomem *)((port << 2) | smsc_superio_virt);
170 }
171
172 return (void __iomem *)port;
173 }
174
175 extern void init_cayman_irq(void);
176
177 static struct sh_machine_vector mv_cayman __initmv = {
178 .mv_name = "Hitachi Cayman",
179 .mv_ioport_map = cayman_ioport_map,
180 .mv_init_irq = init_cayman_irq,
181 };
182