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1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * arch/sh/kernel/cpu/shmobile/pm.c
4   *
5   * Power management support code for SuperH Mobile
6   *
7   *  Copyright (C) 2009 Magnus Damm
8   */
9  #include <linux/init.h>
10  #include <linux/kernel.h>
11  #include <linux/io.h>
12  #include <linux/suspend.h>
13  #include <asm/suspend.h>
14  #include <linux/uaccess.h>
15  #include <asm/cacheflush.h>
16  #include <asm/bl_bit.h>
17  
18  /*
19   * Notifier lists for pre/post sleep notification
20   */
21  ATOMIC_NOTIFIER_HEAD(sh_mobile_pre_sleep_notifier_list);
22  ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
23  
24  /*
25   * Sleep modes available on SuperH Mobile:
26   *
27   * Sleep mode is just plain "sleep" instruction
28   * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29   * Standby Self-Refresh mode is above plus stopped clocks
30   */
31  #define SUSP_MODE_SLEEP		(SUSP_SH_SLEEP)
32  #define SUSP_MODE_SLEEP_SF	(SUSP_SH_SLEEP | SUSP_SH_SF)
33  #define SUSP_MODE_STANDBY_SF	(SUSP_SH_STANDBY | SUSP_SH_SF)
34  #define SUSP_MODE_RSTANDBY_SF \
35  	(SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_REGS | SUSP_SH_SF)
36   /*
37    * U-standby mode is unsupported since it needs bootloader hacks
38    */
39  
40  #ifdef CONFIG_CPU_SUBTYPE_SH7724
41  #define RAM_BASE 0xfd800000 /* RSMEM */
42  #else
43  #define RAM_BASE 0xe5200000 /* ILRAM */
44  #endif
45  
sh_mobile_call_standby(unsigned long mode)46  void sh_mobile_call_standby(unsigned long mode)
47  {
48  	void *onchip_mem = (void *)RAM_BASE;
49  	struct sh_sleep_data *sdp = onchip_mem;
50  	void (*standby_onchip_mem)(unsigned long, unsigned long);
51  
52  	/* code located directly after data structure */
53  	standby_onchip_mem = (void *)(sdp + 1);
54  
55  	atomic_notifier_call_chain(&sh_mobile_pre_sleep_notifier_list,
56  				   mode, NULL);
57  
58  	/* flush the caches if MMU flag is set */
59  	if (mode & SUSP_SH_MMU)
60  		flush_cache_all();
61  
62  	/* Let assembly snippet in on-chip memory handle the rest */
63  	standby_onchip_mem(mode, RAM_BASE);
64  
65  	atomic_notifier_call_chain(&sh_mobile_post_sleep_notifier_list,
66  				   mode, NULL);
67  }
68  
69  extern char sh_mobile_sleep_enter_start;
70  extern char sh_mobile_sleep_enter_end;
71  
72  extern char sh_mobile_sleep_resume_start;
73  extern char sh_mobile_sleep_resume_end;
74  
75  unsigned long sh_mobile_sleep_supported = SUSP_SH_SLEEP;
76  
sh_mobile_register_self_refresh(unsigned long flags,void * pre_start,void * pre_end,void * post_start,void * post_end)77  void sh_mobile_register_self_refresh(unsigned long flags,
78  				     void *pre_start, void *pre_end,
79  				     void *post_start, void *post_end)
80  {
81  	void *onchip_mem = (void *)RAM_BASE;
82  	void *vp;
83  	struct sh_sleep_data *sdp;
84  	int n;
85  
86  	/* part 0: data area */
87  	sdp = onchip_mem;
88  	sdp->addr.stbcr = 0xa4150020; /* STBCR */
89  	sdp->addr.bar = 0xa4150040; /* BAR */
90  	sdp->addr.pteh = 0xff000000; /* PTEH */
91  	sdp->addr.ptel = 0xff000004; /* PTEL */
92  	sdp->addr.ttb = 0xff000008; /* TTB */
93  	sdp->addr.tea = 0xff00000c; /* TEA */
94  	sdp->addr.mmucr = 0xff000010; /* MMUCR */
95  	sdp->addr.ptea = 0xff000034; /* PTEA */
96  	sdp->addr.pascr = 0xff000070; /* PASCR */
97  	sdp->addr.irmcr = 0xff000078; /* IRMCR */
98  	sdp->addr.ccr = 0xff00001c; /* CCR */
99  	sdp->addr.ramcr = 0xff000074; /* RAMCR */
100  	vp = sdp + 1;
101  
102  	/* part 1: common code to enter sleep mode */
103  	n = &sh_mobile_sleep_enter_end - &sh_mobile_sleep_enter_start;
104  	memcpy(vp, &sh_mobile_sleep_enter_start, n);
105  	vp += roundup(n, 4);
106  
107  	/* part 2: board specific code to enter self-refresh mode */
108  	n = pre_end - pre_start;
109  	memcpy(vp, pre_start, n);
110  	sdp->sf_pre = (unsigned long)vp;
111  	vp += roundup(n, 4);
112  
113  	/* part 3: board specific code to resume from self-refresh mode */
114  	n = post_end - post_start;
115  	memcpy(vp, post_start, n);
116  	sdp->sf_post = (unsigned long)vp;
117  	vp += roundup(n, 4);
118  
119  	/* part 4: common code to resume from sleep mode */
120  	WARN_ON(vp > (onchip_mem + 0x600));
121  	vp = onchip_mem + 0x600; /* located at interrupt vector */
122  	n = &sh_mobile_sleep_resume_end - &sh_mobile_sleep_resume_start;
123  	memcpy(vp, &sh_mobile_sleep_resume_start, n);
124  	sdp->resume = (unsigned long)vp;
125  
126  	sh_mobile_sleep_supported |= flags;
127  }
128  
sh_pm_enter(suspend_state_t state)129  static int sh_pm_enter(suspend_state_t state)
130  {
131  	if (!(sh_mobile_sleep_supported & SUSP_MODE_STANDBY_SF))
132  		return -ENXIO;
133  
134  	local_irq_disable();
135  	set_bl_bit();
136  	sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
137  	local_irq_disable();
138  	clear_bl_bit();
139  	return 0;
140  }
141  
142  static const struct platform_suspend_ops sh_pm_ops = {
143  	.enter          = sh_pm_enter,
144  	.valid          = suspend_valid_only_mem,
145  };
146  
sh_pm_init(void)147  static int __init sh_pm_init(void)
148  {
149  	suspend_set_ops(&sh_pm_ops);
150  	return sh_mobile_setup_cpuidle();
151  }
152  
153  late_initcall(sh_pm_init);
154