1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sata_qstor.c - Pacific Digital Corporation QStor SATA
4 *
5 * Maintained by: Mark Lord <mlord@pobox.com>
6 *
7 * Copyright 2005 Pacific Digital Corporation.
8 * (OSL/GPL code release authorized by Jalil Fadavi).
9 *
10 * libata documentation is available via 'make {ps|pdf}docs',
11 * as Documentation/driver-api/libata.rst
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/gfp.h>
17 #include <linux/pci.h>
18 #include <linux/blkdev.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
24
25 #define DRV_NAME "sata_qstor"
26 #define DRV_VERSION "0.09"
27
28 enum {
29 QS_MMIO_BAR = 4,
30
31 QS_PORTS = 4,
32 QS_MAX_PRD = LIBATA_MAX_PRD,
33 QS_CPB_ORDER = 6,
34 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
35 QS_PRD_BYTES = QS_MAX_PRD * 16,
36 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
37
38 /* global register offsets */
39 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
40 QS_HID_HPHY = 0x0004, /* host physical interface info */
41 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
42 QS_HST_SFF = 0x0100, /* host status fifo offset */
43 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
44
45 /* global control bits */
46 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
47 QS_CNFG3_GSRST = 0x01, /* global chip reset */
48 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
49
50 /* per-channel register offsets */
51 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
52 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
53 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
54 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
55 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
56 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
57 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
58 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
59 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
60
61 /* channel control bits */
62 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
63 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
64 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
65 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
66 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
67
68 /* pkt sub-field headers */
69 QS_HCB_HDR = 0x01, /* Host Control Block header */
70 QS_DCB_HDR = 0x02, /* Device Control Block header */
71
72 /* pkt HCB flag bits */
73 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
74 QS_HF_DAT = (1 << 3), /* DATa pkt */
75 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
76 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
77
78 /* pkt DCB flag bits */
79 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
80 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
81
82 /* PCI device IDs */
83 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
84 };
85
86 enum {
87 QS_DMA_BOUNDARY = ~0UL
88 };
89
90 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
91
92 struct qs_port_priv {
93 u8 *pkt;
94 dma_addr_t pkt_dma;
95 qs_state_t state;
96 };
97
98 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
99 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
100 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
101 static int qs_port_start(struct ata_port *ap);
102 static void qs_host_stop(struct ata_host *host);
103 static void qs_qc_prep(struct ata_queued_cmd *qc);
104 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
105 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
106 static void qs_freeze(struct ata_port *ap);
107 static void qs_thaw(struct ata_port *ap);
108 static int qs_prereset(struct ata_link *link, unsigned long deadline);
109 static void qs_error_handler(struct ata_port *ap);
110
111 static struct scsi_host_template qs_ata_sht = {
112 ATA_BASE_SHT(DRV_NAME),
113 .sg_tablesize = QS_MAX_PRD,
114 .dma_boundary = QS_DMA_BOUNDARY,
115 };
116
117 static struct ata_port_operations qs_ata_ops = {
118 .inherits = &ata_sff_port_ops,
119
120 .check_atapi_dma = qs_check_atapi_dma,
121 .qc_prep = qs_qc_prep,
122 .qc_issue = qs_qc_issue,
123
124 .freeze = qs_freeze,
125 .thaw = qs_thaw,
126 .prereset = qs_prereset,
127 .softreset = ATA_OP_NULL,
128 .error_handler = qs_error_handler,
129 .lost_interrupt = ATA_OP_NULL,
130
131 .scr_read = qs_scr_read,
132 .scr_write = qs_scr_write,
133
134 .port_start = qs_port_start,
135 .host_stop = qs_host_stop,
136 };
137
138 static const struct ata_port_info qs_port_info[] = {
139 /* board_2068_idx */
140 {
141 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
142 .pio_mask = ATA_PIO4_ONLY,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &qs_ata_ops,
145 },
146 };
147
148 static const struct pci_device_id qs_ata_pci_tbl[] = {
149 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
150
151 { } /* terminate list */
152 };
153
154 static struct pci_driver qs_ata_pci_driver = {
155 .name = DRV_NAME,
156 .id_table = qs_ata_pci_tbl,
157 .probe = qs_ata_init_one,
158 .remove = ata_pci_remove_one,
159 };
160
qs_mmio_base(struct ata_host * host)161 static void __iomem *qs_mmio_base(struct ata_host *host)
162 {
163 return host->iomap[QS_MMIO_BAR];
164 }
165
qs_check_atapi_dma(struct ata_queued_cmd * qc)166 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
167 {
168 return 1; /* ATAPI DMA not supported */
169 }
170
qs_enter_reg_mode(struct ata_port * ap)171 static inline void qs_enter_reg_mode(struct ata_port *ap)
172 {
173 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
174 struct qs_port_priv *pp = ap->private_data;
175
176 pp->state = qs_state_mmio;
177 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
178 readb(chan + QS_CCT_CTR0); /* flush */
179 }
180
qs_reset_channel_logic(struct ata_port * ap)181 static inline void qs_reset_channel_logic(struct ata_port *ap)
182 {
183 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
184
185 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
186 readb(chan + QS_CCT_CTR0); /* flush */
187 qs_enter_reg_mode(ap);
188 }
189
qs_freeze(struct ata_port * ap)190 static void qs_freeze(struct ata_port *ap)
191 {
192 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
193
194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
195 qs_enter_reg_mode(ap);
196 }
197
qs_thaw(struct ata_port * ap)198 static void qs_thaw(struct ata_port *ap)
199 {
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
201
202 qs_enter_reg_mode(ap);
203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
204 }
205
qs_prereset(struct ata_link * link,unsigned long deadline)206 static int qs_prereset(struct ata_link *link, unsigned long deadline)
207 {
208 struct ata_port *ap = link->ap;
209
210 qs_reset_channel_logic(ap);
211 return ata_sff_prereset(link, deadline);
212 }
213
qs_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)214 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
215 {
216 if (sc_reg > SCR_CONTROL)
217 return -EINVAL;
218 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
219 return 0;
220 }
221
qs_error_handler(struct ata_port * ap)222 static void qs_error_handler(struct ata_port *ap)
223 {
224 qs_enter_reg_mode(ap);
225 ata_sff_error_handler(ap);
226 }
227
qs_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)228 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
229 {
230 if (sc_reg > SCR_CONTROL)
231 return -EINVAL;
232 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
233 return 0;
234 }
235
qs_fill_sg(struct ata_queued_cmd * qc)236 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
237 {
238 struct scatterlist *sg;
239 struct ata_port *ap = qc->ap;
240 struct qs_port_priv *pp = ap->private_data;
241 u8 *prd = pp->pkt + QS_CPB_BYTES;
242 unsigned int si;
243
244 for_each_sg(qc->sg, sg, qc->n_elem, si) {
245 u64 addr;
246 u32 len;
247
248 addr = sg_dma_address(sg);
249 *(__le64 *)prd = cpu_to_le64(addr);
250 prd += sizeof(u64);
251
252 len = sg_dma_len(sg);
253 *(__le32 *)prd = cpu_to_le32(len);
254 prd += sizeof(u64);
255
256 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
257 (unsigned long long)addr, len);
258 }
259
260 return si;
261 }
262
qs_qc_prep(struct ata_queued_cmd * qc)263 static void qs_qc_prep(struct ata_queued_cmd *qc)
264 {
265 struct qs_port_priv *pp = qc->ap->private_data;
266 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
267 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
268 u64 addr;
269 unsigned int nelem;
270
271 VPRINTK("ENTER\n");
272
273 qs_enter_reg_mode(qc->ap);
274 if (qc->tf.protocol != ATA_PROT_DMA)
275 return;
276
277 nelem = qs_fill_sg(qc);
278
279 if ((qc->tf.flags & ATA_TFLAG_WRITE))
280 hflags |= QS_HF_DIRO;
281 if ((qc->tf.flags & ATA_TFLAG_LBA48))
282 dflags |= QS_DF_ELBA;
283
284 /* host control block (HCB) */
285 buf[ 0] = QS_HCB_HDR;
286 buf[ 1] = hflags;
287 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
288 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
289 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
290 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
291
292 /* device control block (DCB) */
293 buf[24] = QS_DCB_HDR;
294 buf[28] = dflags;
295
296 /* frame information structure (FIS) */
297 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
298 }
299
qs_packet_start(struct ata_queued_cmd * qc)300 static inline void qs_packet_start(struct ata_queued_cmd *qc)
301 {
302 struct ata_port *ap = qc->ap;
303 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
304
305 VPRINTK("ENTER, ap %p\n", ap);
306
307 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
308 wmb(); /* flush PRDs and pkt to memory */
309 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
310 readl(chan + QS_CCT_CFF); /* flush */
311 }
312
qs_qc_issue(struct ata_queued_cmd * qc)313 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
314 {
315 struct qs_port_priv *pp = qc->ap->private_data;
316
317 switch (qc->tf.protocol) {
318 case ATA_PROT_DMA:
319 pp->state = qs_state_pkt;
320 qs_packet_start(qc);
321 return 0;
322
323 case ATAPI_PROT_DMA:
324 BUG();
325 break;
326
327 default:
328 break;
329 }
330
331 pp->state = qs_state_mmio;
332 return ata_sff_qc_issue(qc);
333 }
334
qs_do_or_die(struct ata_queued_cmd * qc,u8 status)335 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
336 {
337 qc->err_mask |= ac_err_mask(status);
338
339 if (!qc->err_mask) {
340 ata_qc_complete(qc);
341 } else {
342 struct ata_port *ap = qc->ap;
343 struct ata_eh_info *ehi = &ap->link.eh_info;
344
345 ata_ehi_clear_desc(ehi);
346 ata_ehi_push_desc(ehi, "status 0x%02X", status);
347
348 if (qc->err_mask == AC_ERR_DEV)
349 ata_port_abort(ap);
350 else
351 ata_port_freeze(ap);
352 }
353 }
354
qs_intr_pkt(struct ata_host * host)355 static inline unsigned int qs_intr_pkt(struct ata_host *host)
356 {
357 unsigned int handled = 0;
358 u8 sFFE;
359 u8 __iomem *mmio_base = qs_mmio_base(host);
360
361 do {
362 u32 sff0 = readl(mmio_base + QS_HST_SFF);
363 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
364 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
365 sFFE = sff1 >> 31; /* empty flag */
366
367 if (sEVLD) {
368 u8 sDST = sff0 >> 16; /* dev status */
369 u8 sHST = sff1 & 0x3f; /* host status */
370 unsigned int port_no = (sff1 >> 8) & 0x03;
371 struct ata_port *ap = host->ports[port_no];
372 struct qs_port_priv *pp = ap->private_data;
373 struct ata_queued_cmd *qc;
374
375 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
376 sff1, sff0, port_no, sHST, sDST);
377 handled = 1;
378 if (!pp || pp->state != qs_state_pkt)
379 continue;
380 qc = ata_qc_from_tag(ap, ap->link.active_tag);
381 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
382 switch (sHST) {
383 case 0: /* successful CPB */
384 case 3: /* device error */
385 qs_enter_reg_mode(qc->ap);
386 qs_do_or_die(qc, sDST);
387 break;
388 default:
389 break;
390 }
391 }
392 }
393 } while (!sFFE);
394 return handled;
395 }
396
qs_intr_mmio(struct ata_host * host)397 static inline unsigned int qs_intr_mmio(struct ata_host *host)
398 {
399 unsigned int handled = 0, port_no;
400
401 for (port_no = 0; port_no < host->n_ports; ++port_no) {
402 struct ata_port *ap = host->ports[port_no];
403 struct qs_port_priv *pp = ap->private_data;
404 struct ata_queued_cmd *qc;
405
406 qc = ata_qc_from_tag(ap, ap->link.active_tag);
407 if (!qc) {
408 /*
409 * The qstor hardware generates spurious
410 * interrupts from time to time when switching
411 * in and out of packet mode. There's no
412 * obvious way to know if we're here now due
413 * to that, so just ack the irq and pretend we
414 * knew it was ours.. (ugh). This does not
415 * affect packet mode.
416 */
417 ata_sff_check_status(ap);
418 handled = 1;
419 continue;
420 }
421
422 if (!pp || pp->state != qs_state_mmio)
423 continue;
424 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
425 handled |= ata_sff_port_intr(ap, qc);
426 }
427 return handled;
428 }
429
qs_intr(int irq,void * dev_instance)430 static irqreturn_t qs_intr(int irq, void *dev_instance)
431 {
432 struct ata_host *host = dev_instance;
433 unsigned int handled = 0;
434 unsigned long flags;
435
436 VPRINTK("ENTER\n");
437
438 spin_lock_irqsave(&host->lock, flags);
439 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
440 spin_unlock_irqrestore(&host->lock, flags);
441
442 VPRINTK("EXIT\n");
443
444 return IRQ_RETVAL(handled);
445 }
446
qs_ata_setup_port(struct ata_ioports * port,void __iomem * base)447 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
448 {
449 port->cmd_addr =
450 port->data_addr = base + 0x400;
451 port->error_addr =
452 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
453 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
454 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
455 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
456 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
457 port->device_addr = base + 0x430;
458 port->status_addr =
459 port->command_addr = base + 0x438;
460 port->altstatus_addr =
461 port->ctl_addr = base + 0x440;
462 port->scr_addr = base + 0xc00;
463 }
464
qs_port_start(struct ata_port * ap)465 static int qs_port_start(struct ata_port *ap)
466 {
467 struct device *dev = ap->host->dev;
468 struct qs_port_priv *pp;
469 void __iomem *mmio_base = qs_mmio_base(ap->host);
470 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
471 u64 addr;
472
473 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
474 if (!pp)
475 return -ENOMEM;
476 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
477 GFP_KERNEL);
478 if (!pp->pkt)
479 return -ENOMEM;
480 ap->private_data = pp;
481
482 qs_enter_reg_mode(ap);
483 addr = (u64)pp->pkt_dma;
484 writel((u32) addr, chan + QS_CCF_CPBA);
485 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
486 return 0;
487 }
488
qs_host_stop(struct ata_host * host)489 static void qs_host_stop(struct ata_host *host)
490 {
491 void __iomem *mmio_base = qs_mmio_base(host);
492
493 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
494 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
495 }
496
qs_host_init(struct ata_host * host,unsigned int chip_id)497 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
498 {
499 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
500 unsigned int port_no;
501
502 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
503 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
504
505 /* reset each channel in turn */
506 for (port_no = 0; port_no < host->n_ports; ++port_no) {
507 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
508 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
509 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
510 readb(chan + QS_CCT_CTR0); /* flush */
511 }
512 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
513
514 for (port_no = 0; port_no < host->n_ports; ++port_no) {
515 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
516 /* set FIFO depths to same settings as Windows driver */
517 writew(32, chan + QS_CFC_HUFT);
518 writew(32, chan + QS_CFC_HDFT);
519 writew(10, chan + QS_CFC_DUFT);
520 writew( 8, chan + QS_CFC_DDFT);
521 /* set CPB size in bytes, as a power of two */
522 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
523 }
524 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
525 }
526
527 /*
528 * The QStor understands 64-bit buses, and uses 64-bit fields
529 * for DMA pointers regardless of bus width. We just have to
530 * make sure our DMA masks are set appropriately for whatever
531 * bridge lies between us and the QStor, and then the DMA mapping
532 * code will ensure we only ever "see" appropriate buffer addresses.
533 * If we're 32-bit limited somewhere, then our 64-bit fields will
534 * just end up with zeros in the upper 32-bits, without any special
535 * logic required outside of this routine (below).
536 */
qs_set_dma_masks(struct pci_dev * pdev,void __iomem * mmio_base)537 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
538 {
539 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
540 int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
541 int rc;
542
543 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
544 if (rc)
545 dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
546 return rc;
547 }
548
qs_ata_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)549 static int qs_ata_init_one(struct pci_dev *pdev,
550 const struct pci_device_id *ent)
551 {
552 unsigned int board_idx = (unsigned int) ent->driver_data;
553 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
554 struct ata_host *host;
555 int rc, port_no;
556
557 ata_print_version_once(&pdev->dev, DRV_VERSION);
558
559 /* alloc host */
560 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
561 if (!host)
562 return -ENOMEM;
563
564 /* acquire resources and fill host */
565 rc = pcim_enable_device(pdev);
566 if (rc)
567 return rc;
568
569 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
570 return -ENODEV;
571
572 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
573 if (rc)
574 return rc;
575 host->iomap = pcim_iomap_table(pdev);
576
577 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
578 if (rc)
579 return rc;
580
581 for (port_no = 0; port_no < host->n_ports; ++port_no) {
582 struct ata_port *ap = host->ports[port_no];
583 unsigned int offset = port_no * 0x4000;
584 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
585
586 qs_ata_setup_port(&ap->ioaddr, chan);
587
588 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
589 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
590 }
591
592 /* initialize adapter */
593 qs_host_init(host, board_idx);
594
595 pci_set_master(pdev);
596 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
597 &qs_ata_sht);
598 }
599
600 module_pci_driver(qs_ata_pci_driver);
601
602 MODULE_AUTHOR("Mark Lord");
603 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
604 MODULE_LICENSE("GPL");
605 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
606 MODULE_VERSION(DRV_VERSION);
607