1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
9 #include "clk.h"
10
11 struct clk_cpu {
12 struct clk_hw hw;
13 struct clk *div;
14 struct clk *mux;
15 struct clk *pll;
16 struct clk *step;
17 };
18
to_clk_cpu(struct clk_hw * hw)19 static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
20 {
21 return container_of(hw, struct clk_cpu, hw);
22 }
23
clk_cpu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)24 static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
25 unsigned long parent_rate)
26 {
27 struct clk_cpu *cpu = to_clk_cpu(hw);
28
29 return clk_get_rate(cpu->div);
30 }
31
clk_cpu_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)32 static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
33 unsigned long *prate)
34 {
35 struct clk_cpu *cpu = to_clk_cpu(hw);
36
37 return clk_round_rate(cpu->pll, rate);
38 }
39
clk_cpu_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)40 static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
41 unsigned long parent_rate)
42 {
43 struct clk_cpu *cpu = to_clk_cpu(hw);
44 int ret;
45
46 /* switch to PLL bypass clock */
47 ret = clk_set_parent(cpu->mux, cpu->step);
48 if (ret)
49 return ret;
50
51 /* reprogram PLL */
52 ret = clk_set_rate(cpu->pll, rate);
53 if (ret) {
54 clk_set_parent(cpu->mux, cpu->pll);
55 return ret;
56 }
57 /* switch back to PLL clock */
58 clk_set_parent(cpu->mux, cpu->pll);
59
60 /* Ensure the divider is what we expect */
61 clk_set_rate(cpu->div, rate);
62
63 return 0;
64 }
65
66 static const struct clk_ops clk_cpu_ops = {
67 .recalc_rate = clk_cpu_recalc_rate,
68 .round_rate = clk_cpu_round_rate,
69 .set_rate = clk_cpu_set_rate,
70 };
71
imx_clk_hw_cpu(const char * name,const char * parent_name,struct clk * div,struct clk * mux,struct clk * pll,struct clk * step)72 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
73 struct clk *div, struct clk *mux, struct clk *pll,
74 struct clk *step)
75 {
76 struct clk_cpu *cpu;
77 struct clk_hw *hw;
78 struct clk_init_data init;
79 int ret;
80
81 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
82 if (!cpu)
83 return ERR_PTR(-ENOMEM);
84
85 cpu->div = div;
86 cpu->mux = mux;
87 cpu->pll = pll;
88 cpu->step = step;
89
90 init.name = name;
91 init.ops = &clk_cpu_ops;
92 init.flags = CLK_IS_CRITICAL;
93 init.parent_names = &parent_name;
94 init.num_parents = 1;
95
96 cpu->hw.init = &init;
97 hw = &cpu->hw;
98
99 ret = clk_hw_register(NULL, hw);
100 if (ret) {
101 kfree(cpu);
102 return ERR_PTR(ret);
103 }
104
105 return hw;
106 }
107