1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
4 #include <linux/err.h>
5 #include <linux/io.h>
6 #include <linux/of.h>
7 #include <linux/slab.h>
8 #include <linux/spinlock.h>
9 #include "clk.h"
10
11 #define CCM_CCDR 0x4
12 #define CCDR_MMDC_CH0_MASK BIT(17)
13 #define CCDR_MMDC_CH1_MASK BIT(16)
14
15 DEFINE_SPINLOCK(imx_ccm_lock);
16
imx_unregister_clocks(struct clk * clks[],unsigned int count)17 void imx_unregister_clocks(struct clk *clks[], unsigned int count)
18 {
19 unsigned int i;
20
21 for (i = 0; i < count; i++)
22 clk_unregister(clks[i]);
23 }
24
imx_mmdc_mask_handshake(void __iomem * ccm_base,unsigned int chn)25 void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
26 unsigned int chn)
27 {
28 unsigned int reg;
29
30 reg = readl_relaxed(ccm_base + CCM_CCDR);
31 reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK;
32 writel_relaxed(reg, ccm_base + CCM_CCDR);
33 }
34
imx_check_clocks(struct clk * clks[],unsigned int count)35 void imx_check_clocks(struct clk *clks[], unsigned int count)
36 {
37 unsigned i;
38
39 for (i = 0; i < count; i++)
40 if (IS_ERR(clks[i]))
41 pr_err("i.MX clk %u: register failed with %ld\n",
42 i, PTR_ERR(clks[i]));
43 }
44
imx_check_clk_hws(struct clk_hw * clks[],unsigned int count)45 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
46 {
47 unsigned int i;
48
49 for (i = 0; i < count; i++)
50 if (IS_ERR(clks[i]))
51 pr_err("i.MX clk %u: register failed with %ld\n",
52 i, PTR_ERR(clks[i]));
53 }
54
imx_obtain_fixed_clock_from_dt(const char * name)55 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
56 {
57 struct of_phandle_args phandle;
58 struct clk *clk = ERR_PTR(-ENODEV);
59 char *path;
60
61 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
62 if (!path)
63 return ERR_PTR(-ENOMEM);
64
65 phandle.np = of_find_node_by_path(path);
66 kfree(path);
67
68 if (phandle.np) {
69 clk = of_clk_get_from_provider(&phandle);
70 of_node_put(phandle.np);
71 }
72 return clk;
73 }
74
imx_obtain_fixed_clock(const char * name,unsigned long rate)75 struct clk * __init imx_obtain_fixed_clock(
76 const char *name, unsigned long rate)
77 {
78 struct clk *clk;
79
80 clk = imx_obtain_fixed_clock_from_dt(name);
81 if (IS_ERR(clk))
82 clk = imx_clk_fixed(name, rate);
83 return clk;
84 }
85
imx_obtain_fixed_clock_hw(const char * name,unsigned long rate)86 struct clk_hw * __init imx_obtain_fixed_clock_hw(
87 const char *name, unsigned long rate)
88 {
89 struct clk *clk;
90
91 clk = imx_obtain_fixed_clock_from_dt(name);
92 if (IS_ERR(clk))
93 clk = imx_clk_fixed(name, rate);
94 return __clk_get_hw(clk);
95 }
96
imx_obtain_fixed_clk_hw(struct device_node * np,const char * name)97 struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
98 const char *name)
99 {
100 struct clk *clk;
101
102 clk = of_clk_get_by_name(np, name);
103 if (IS_ERR(clk))
104 return ERR_PTR(-ENOENT);
105
106 return __clk_get_hw(clk);
107 }
108
109 /*
110 * This fixups the register CCM_CSCMR1 write value.
111 * The write/read/divider values of the aclk_podf field
112 * of that register have the relationship described by
113 * the following table:
114 *
115 * write value read value divider
116 * 3b'000 3b'110 7
117 * 3b'001 3b'111 8
118 * 3b'010 3b'100 5
119 * 3b'011 3b'101 6
120 * 3b'100 3b'010 3
121 * 3b'101 3b'011 4
122 * 3b'110 3b'000 1
123 * 3b'111 3b'001 2(default)
124 *
125 * That's why we do the xor operation below.
126 */
127 #define CSCMR1_FIXUP 0x00600000
128
imx_cscmr1_fixup(u32 * val)129 void imx_cscmr1_fixup(u32 *val)
130 {
131 *val ^= CSCMR1_FIXUP;
132 return;
133 }
134
135 static int imx_keep_uart_clocks;
136 static struct clk ** const *imx_uart_clocks;
137
imx_keep_uart_clocks_param(char * str)138 static int __init imx_keep_uart_clocks_param(char *str)
139 {
140 imx_keep_uart_clocks = 1;
141
142 return 0;
143 }
144 __setup_param("earlycon", imx_keep_uart_earlycon,
145 imx_keep_uart_clocks_param, 0);
146 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
147 imx_keep_uart_clocks_param, 0);
148
imx_register_uart_clocks(struct clk ** const clks[])149 void imx_register_uart_clocks(struct clk ** const clks[])
150 {
151 if (imx_keep_uart_clocks) {
152 int i;
153
154 imx_uart_clocks = clks;
155 for (i = 0; imx_uart_clocks[i]; i++)
156 clk_prepare_enable(*imx_uart_clocks[i]);
157 }
158 }
159
imx_clk_disable_uart(void)160 static int __init imx_clk_disable_uart(void)
161 {
162 if (imx_keep_uart_clocks && imx_uart_clocks) {
163 int i;
164
165 for (i = 0; imx_uart_clocks[i]; i++)
166 clk_disable_unprepare(*imx_uart_clocks[i]);
167 }
168
169 return 0;
170 }
171 late_initcall_sync(imx_clk_disable_uart);
172