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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/export.h>
8 #include <linux/slab.h>
9 #include <linux/err.h>
10 
11 #include "clk.h"
12 
clk_periph_get_parent(struct clk_hw * hw)13 static u8 clk_periph_get_parent(struct clk_hw *hw)
14 {
15 	struct tegra_clk_periph *periph = to_clk_periph(hw);
16 	const struct clk_ops *mux_ops = periph->mux_ops;
17 	struct clk_hw *mux_hw = &periph->mux.hw;
18 
19 	__clk_hw_set_clk(mux_hw, hw);
20 
21 	return mux_ops->get_parent(mux_hw);
22 }
23 
clk_periph_set_parent(struct clk_hw * hw,u8 index)24 static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
25 {
26 	struct tegra_clk_periph *periph = to_clk_periph(hw);
27 	const struct clk_ops *mux_ops = periph->mux_ops;
28 	struct clk_hw *mux_hw = &periph->mux.hw;
29 
30 	__clk_hw_set_clk(mux_hw, hw);
31 
32 	return mux_ops->set_parent(mux_hw, index);
33 }
34 
clk_periph_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)35 static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
36 					    unsigned long parent_rate)
37 {
38 	struct tegra_clk_periph *periph = to_clk_periph(hw);
39 	const struct clk_ops *div_ops = periph->div_ops;
40 	struct clk_hw *div_hw = &periph->divider.hw;
41 
42 	__clk_hw_set_clk(div_hw, hw);
43 
44 	return div_ops->recalc_rate(div_hw, parent_rate);
45 }
46 
clk_periph_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)47 static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
48 				  unsigned long *prate)
49 {
50 	struct tegra_clk_periph *periph = to_clk_periph(hw);
51 	const struct clk_ops *div_ops = periph->div_ops;
52 	struct clk_hw *div_hw = &periph->divider.hw;
53 
54 	__clk_hw_set_clk(div_hw, hw);
55 
56 	return div_ops->round_rate(div_hw, rate, prate);
57 }
58 
clk_periph_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)59 static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
60 			       unsigned long parent_rate)
61 {
62 	struct tegra_clk_periph *periph = to_clk_periph(hw);
63 	const struct clk_ops *div_ops = periph->div_ops;
64 	struct clk_hw *div_hw = &periph->divider.hw;
65 
66 	__clk_hw_set_clk(div_hw, hw);
67 
68 	return div_ops->set_rate(div_hw, rate, parent_rate);
69 }
70 
clk_periph_is_enabled(struct clk_hw * hw)71 static int clk_periph_is_enabled(struct clk_hw *hw)
72 {
73 	struct tegra_clk_periph *periph = to_clk_periph(hw);
74 	const struct clk_ops *gate_ops = periph->gate_ops;
75 	struct clk_hw *gate_hw = &periph->gate.hw;
76 
77 	__clk_hw_set_clk(gate_hw, hw);
78 
79 	return gate_ops->is_enabled(gate_hw);
80 }
81 
clk_periph_enable(struct clk_hw * hw)82 static int clk_periph_enable(struct clk_hw *hw)
83 {
84 	struct tegra_clk_periph *periph = to_clk_periph(hw);
85 	const struct clk_ops *gate_ops = periph->gate_ops;
86 	struct clk_hw *gate_hw = &periph->gate.hw;
87 
88 	__clk_hw_set_clk(gate_hw, hw);
89 
90 	return gate_ops->enable(gate_hw);
91 }
92 
clk_periph_disable(struct clk_hw * hw)93 static void clk_periph_disable(struct clk_hw *hw)
94 {
95 	struct tegra_clk_periph *periph = to_clk_periph(hw);
96 	const struct clk_ops *gate_ops = periph->gate_ops;
97 	struct clk_hw *gate_hw = &periph->gate.hw;
98 
99 	gate_ops->disable(gate_hw);
100 }
101 
102 const struct clk_ops tegra_clk_periph_ops = {
103 	.get_parent = clk_periph_get_parent,
104 	.set_parent = clk_periph_set_parent,
105 	.recalc_rate = clk_periph_recalc_rate,
106 	.round_rate = clk_periph_round_rate,
107 	.set_rate = clk_periph_set_rate,
108 	.is_enabled = clk_periph_is_enabled,
109 	.enable = clk_periph_enable,
110 	.disable = clk_periph_disable,
111 };
112 
113 static const struct clk_ops tegra_clk_periph_nodiv_ops = {
114 	.get_parent = clk_periph_get_parent,
115 	.set_parent = clk_periph_set_parent,
116 	.is_enabled = clk_periph_is_enabled,
117 	.enable = clk_periph_enable,
118 	.disable = clk_periph_disable,
119 };
120 
121 static const struct clk_ops tegra_clk_periph_no_gate_ops = {
122 	.get_parent = clk_periph_get_parent,
123 	.set_parent = clk_periph_set_parent,
124 	.recalc_rate = clk_periph_recalc_rate,
125 	.round_rate = clk_periph_round_rate,
126 	.set_rate = clk_periph_set_rate,
127 };
128 
_tegra_clk_register_periph(const char * name,const char * const * parent_names,int num_parents,struct tegra_clk_periph * periph,void __iomem * clk_base,u32 offset,unsigned long flags)129 static struct clk *_tegra_clk_register_periph(const char *name,
130 			const char * const *parent_names, int num_parents,
131 			struct tegra_clk_periph *periph,
132 			void __iomem *clk_base, u32 offset,
133 			unsigned long flags)
134 {
135 	struct clk *clk;
136 	struct clk_init_data init;
137 	const struct tegra_clk_periph_regs *bank;
138 	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
139 
140 	if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
141 		flags |= CLK_SET_RATE_PARENT;
142 		init.ops = &tegra_clk_periph_nodiv_ops;
143 	} else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
144 		init.ops = &tegra_clk_periph_no_gate_ops;
145 	else
146 		init.ops = &tegra_clk_periph_ops;
147 
148 	init.name = name;
149 	init.flags = flags;
150 	init.parent_names = parent_names;
151 	init.num_parents = num_parents;
152 
153 	bank = get_reg_bank(periph->gate.clk_num);
154 	if (!bank)
155 		return ERR_PTR(-EINVAL);
156 
157 	/* Data in .init is copied by clk_register(), so stack variable OK */
158 	periph->hw.init = &init;
159 	periph->magic = TEGRA_CLK_PERIPH_MAGIC;
160 	periph->mux.reg = clk_base + offset;
161 	periph->divider.reg = div ? (clk_base + offset) : NULL;
162 	periph->gate.clk_base = clk_base;
163 	periph->gate.regs = bank;
164 	periph->gate.enable_refcnt = periph_clk_enb_refcnt;
165 
166 	clk = clk_register(NULL, &periph->hw);
167 	if (IS_ERR(clk))
168 		return clk;
169 
170 	periph->mux.hw.clk = clk;
171 	periph->divider.hw.clk = div ? clk : NULL;
172 	periph->gate.hw.clk = clk;
173 
174 	return clk;
175 }
176 
tegra_clk_register_periph(const char * name,const char * const * parent_names,int num_parents,struct tegra_clk_periph * periph,void __iomem * clk_base,u32 offset,unsigned long flags)177 struct clk *tegra_clk_register_periph(const char *name,
178 		const char * const *parent_names, int num_parents,
179 		struct tegra_clk_periph *periph, void __iomem *clk_base,
180 		u32 offset, unsigned long flags)
181 {
182 	return _tegra_clk_register_periph(name, parent_names, num_parents,
183 			periph, clk_base, offset, flags);
184 }
185 
tegra_clk_register_periph_nodiv(const char * name,const char * const * parent_names,int num_parents,struct tegra_clk_periph * periph,void __iomem * clk_base,u32 offset)186 struct clk *tegra_clk_register_periph_nodiv(const char *name,
187 		const char * const *parent_names, int num_parents,
188 		struct tegra_clk_periph *periph, void __iomem *clk_base,
189 		u32 offset)
190 {
191 	periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
192 	return _tegra_clk_register_periph(name, parent_names, num_parents,
193 			periph, clk_base, offset, CLK_SET_RATE_PARENT);
194 }
195 
tegra_clk_register_periph_data(void __iomem * clk_base,struct tegra_periph_init_data * init)196 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
197 					   struct tegra_periph_init_data *init)
198 {
199 	return _tegra_clk_register_periph(init->name, init->p.parent_names,
200 					  init->num_parents, &init->periph,
201 					  clk_base, init->offset, init->flags);
202 }
203