1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cryptographic API.
4 *
5 * Support for ATMEL AES HW acceleration.
6 *
7 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
8 * Author: Nicolas Royer <nicolas@eukrea.com>
9 *
10 * Some ideas are from omap-aes.c driver.
11 */
12
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/hw_random.h>
21 #include <linux/platform_device.h>
22
23 #include <linux/device.h>
24 #include <linux/init.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/scatterlist.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/delay.h>
32 #include <linux/crypto.h>
33 #include <crypto/scatterwalk.h>
34 #include <crypto/algapi.h>
35 #include <crypto/aes.h>
36 #include <crypto/gcm.h>
37 #include <crypto/xts.h>
38 #include <crypto/internal/aead.h>
39 #include <linux/platform_data/crypto-atmel.h>
40 #include <dt-bindings/dma/at91.h>
41 #include "atmel-aes-regs.h"
42 #include "atmel-authenc.h"
43
44 #define ATMEL_AES_PRIORITY 300
45
46 #define ATMEL_AES_BUFFER_ORDER 2
47 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
48
49 #define CFB8_BLOCK_SIZE 1
50 #define CFB16_BLOCK_SIZE 2
51 #define CFB32_BLOCK_SIZE 4
52 #define CFB64_BLOCK_SIZE 8
53
54 #define SIZE_IN_WORDS(x) ((x) >> 2)
55
56 /* AES flags */
57 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
58 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
59 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
60 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
61 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
62 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
63 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
64 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
65 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
66 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
67 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
68 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
69 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
70 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
71 #define AES_FLAGS_XTS AES_MR_OPMOD_XTS
72
73 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
74 AES_FLAGS_ENCRYPT | \
75 AES_FLAGS_GTAGEN)
76
77 #define AES_FLAGS_BUSY BIT(3)
78 #define AES_FLAGS_DUMP_REG BIT(4)
79 #define AES_FLAGS_OWN_SHA BIT(5)
80
81 #define AES_FLAGS_PERSISTENT AES_FLAGS_BUSY
82
83 #define ATMEL_AES_QUEUE_LENGTH 50
84
85 #define ATMEL_AES_DMA_THRESHOLD 256
86
87
88 struct atmel_aes_caps {
89 bool has_dualbuff;
90 bool has_cfb64;
91 bool has_ctr32;
92 bool has_gcm;
93 bool has_xts;
94 bool has_authenc;
95 u32 max_burst_size;
96 };
97
98 struct atmel_aes_dev;
99
100
101 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
102
103
104 struct atmel_aes_base_ctx {
105 struct atmel_aes_dev *dd;
106 atmel_aes_fn_t start;
107 int keylen;
108 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
109 u16 block_size;
110 bool is_aead;
111 };
112
113 struct atmel_aes_ctx {
114 struct atmel_aes_base_ctx base;
115 };
116
117 struct atmel_aes_ctr_ctx {
118 struct atmel_aes_base_ctx base;
119
120 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
121 size_t offset;
122 struct scatterlist src[2];
123 struct scatterlist dst[2];
124 };
125
126 struct atmel_aes_gcm_ctx {
127 struct atmel_aes_base_ctx base;
128
129 struct scatterlist src[2];
130 struct scatterlist dst[2];
131
132 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
133 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
134 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
135 size_t textlen;
136
137 const u32 *ghash_in;
138 u32 *ghash_out;
139 atmel_aes_fn_t ghash_resume;
140 };
141
142 struct atmel_aes_xts_ctx {
143 struct atmel_aes_base_ctx base;
144
145 u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
146 };
147
148 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
149 struct atmel_aes_authenc_ctx {
150 struct atmel_aes_base_ctx base;
151 struct atmel_sha_authenc_ctx *auth;
152 };
153 #endif
154
155 struct atmel_aes_reqctx {
156 unsigned long mode;
157 u32 lastc[AES_BLOCK_SIZE / sizeof(u32)];
158 };
159
160 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
161 struct atmel_aes_authenc_reqctx {
162 struct atmel_aes_reqctx base;
163
164 struct scatterlist src[2];
165 struct scatterlist dst[2];
166 size_t textlen;
167 u32 digest[SHA512_DIGEST_SIZE / sizeof(u32)];
168
169 /* auth_req MUST be place last. */
170 struct ahash_request auth_req;
171 };
172 #endif
173
174 struct atmel_aes_dma {
175 struct dma_chan *chan;
176 struct scatterlist *sg;
177 int nents;
178 unsigned int remainder;
179 unsigned int sg_len;
180 };
181
182 struct atmel_aes_dev {
183 struct list_head list;
184 unsigned long phys_base;
185 void __iomem *io_base;
186
187 struct crypto_async_request *areq;
188 struct atmel_aes_base_ctx *ctx;
189
190 bool is_async;
191 atmel_aes_fn_t resume;
192 atmel_aes_fn_t cpu_transfer_complete;
193
194 struct device *dev;
195 struct clk *iclk;
196 int irq;
197
198 unsigned long flags;
199
200 spinlock_t lock;
201 struct crypto_queue queue;
202
203 struct tasklet_struct done_task;
204 struct tasklet_struct queue_task;
205
206 size_t total;
207 size_t datalen;
208 u32 *data;
209
210 struct atmel_aes_dma src;
211 struct atmel_aes_dma dst;
212
213 size_t buflen;
214 void *buf;
215 struct scatterlist aligned_sg;
216 struct scatterlist *real_dst;
217
218 struct atmel_aes_caps caps;
219
220 u32 hw_version;
221 };
222
223 struct atmel_aes_drv {
224 struct list_head dev_list;
225 spinlock_t lock;
226 };
227
228 static struct atmel_aes_drv atmel_aes = {
229 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
230 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
231 };
232
233 #ifdef VERBOSE_DEBUG
atmel_aes_reg_name(u32 offset,char * tmp,size_t sz)234 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
235 {
236 switch (offset) {
237 case AES_CR:
238 return "CR";
239
240 case AES_MR:
241 return "MR";
242
243 case AES_ISR:
244 return "ISR";
245
246 case AES_IMR:
247 return "IMR";
248
249 case AES_IER:
250 return "IER";
251
252 case AES_IDR:
253 return "IDR";
254
255 case AES_KEYWR(0):
256 case AES_KEYWR(1):
257 case AES_KEYWR(2):
258 case AES_KEYWR(3):
259 case AES_KEYWR(4):
260 case AES_KEYWR(5):
261 case AES_KEYWR(6):
262 case AES_KEYWR(7):
263 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
264 break;
265
266 case AES_IDATAR(0):
267 case AES_IDATAR(1):
268 case AES_IDATAR(2):
269 case AES_IDATAR(3):
270 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
271 break;
272
273 case AES_ODATAR(0):
274 case AES_ODATAR(1):
275 case AES_ODATAR(2):
276 case AES_ODATAR(3):
277 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
278 break;
279
280 case AES_IVR(0):
281 case AES_IVR(1):
282 case AES_IVR(2):
283 case AES_IVR(3):
284 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
285 break;
286
287 case AES_AADLENR:
288 return "AADLENR";
289
290 case AES_CLENR:
291 return "CLENR";
292
293 case AES_GHASHR(0):
294 case AES_GHASHR(1):
295 case AES_GHASHR(2):
296 case AES_GHASHR(3):
297 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
298 break;
299
300 case AES_TAGR(0):
301 case AES_TAGR(1):
302 case AES_TAGR(2):
303 case AES_TAGR(3):
304 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
305 break;
306
307 case AES_CTRR:
308 return "CTRR";
309
310 case AES_GCMHR(0):
311 case AES_GCMHR(1):
312 case AES_GCMHR(2):
313 case AES_GCMHR(3):
314 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
315 break;
316
317 case AES_EMR:
318 return "EMR";
319
320 case AES_TWR(0):
321 case AES_TWR(1):
322 case AES_TWR(2):
323 case AES_TWR(3):
324 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
325 break;
326
327 case AES_ALPHAR(0):
328 case AES_ALPHAR(1):
329 case AES_ALPHAR(2):
330 case AES_ALPHAR(3):
331 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
332 break;
333
334 default:
335 snprintf(tmp, sz, "0x%02x", offset);
336 break;
337 }
338
339 return tmp;
340 }
341 #endif /* VERBOSE_DEBUG */
342
343 /* Shared functions */
344
atmel_aes_read(struct atmel_aes_dev * dd,u32 offset)345 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
346 {
347 u32 value = readl_relaxed(dd->io_base + offset);
348
349 #ifdef VERBOSE_DEBUG
350 if (dd->flags & AES_FLAGS_DUMP_REG) {
351 char tmp[16];
352
353 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
354 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
355 }
356 #endif /* VERBOSE_DEBUG */
357
358 return value;
359 }
360
atmel_aes_write(struct atmel_aes_dev * dd,u32 offset,u32 value)361 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
362 u32 offset, u32 value)
363 {
364 #ifdef VERBOSE_DEBUG
365 if (dd->flags & AES_FLAGS_DUMP_REG) {
366 char tmp[16];
367
368 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
369 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
370 }
371 #endif /* VERBOSE_DEBUG */
372
373 writel_relaxed(value, dd->io_base + offset);
374 }
375
atmel_aes_read_n(struct atmel_aes_dev * dd,u32 offset,u32 * value,int count)376 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
377 u32 *value, int count)
378 {
379 for (; count--; value++, offset += 4)
380 *value = atmel_aes_read(dd, offset);
381 }
382
atmel_aes_write_n(struct atmel_aes_dev * dd,u32 offset,const u32 * value,int count)383 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
384 const u32 *value, int count)
385 {
386 for (; count--; value++, offset += 4)
387 atmel_aes_write(dd, offset, *value);
388 }
389
atmel_aes_read_block(struct atmel_aes_dev * dd,u32 offset,u32 * value)390 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
391 u32 *value)
392 {
393 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
394 }
395
atmel_aes_write_block(struct atmel_aes_dev * dd,u32 offset,const u32 * value)396 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
397 const u32 *value)
398 {
399 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
400 }
401
atmel_aes_wait_for_data_ready(struct atmel_aes_dev * dd,atmel_aes_fn_t resume)402 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
403 atmel_aes_fn_t resume)
404 {
405 u32 isr = atmel_aes_read(dd, AES_ISR);
406
407 if (unlikely(isr & AES_INT_DATARDY))
408 return resume(dd);
409
410 dd->resume = resume;
411 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
412 return -EINPROGRESS;
413 }
414
atmel_aes_padlen(size_t len,size_t block_size)415 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
416 {
417 len &= block_size - 1;
418 return len ? block_size - len : 0;
419 }
420
atmel_aes_find_dev(struct atmel_aes_base_ctx * ctx)421 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
422 {
423 struct atmel_aes_dev *aes_dd = NULL;
424 struct atmel_aes_dev *tmp;
425
426 spin_lock_bh(&atmel_aes.lock);
427 if (!ctx->dd) {
428 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
429 aes_dd = tmp;
430 break;
431 }
432 ctx->dd = aes_dd;
433 } else {
434 aes_dd = ctx->dd;
435 }
436
437 spin_unlock_bh(&atmel_aes.lock);
438
439 return aes_dd;
440 }
441
atmel_aes_hw_init(struct atmel_aes_dev * dd)442 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
443 {
444 int err;
445
446 err = clk_enable(dd->iclk);
447 if (err)
448 return err;
449
450 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
451 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
452
453 return 0;
454 }
455
atmel_aes_get_version(struct atmel_aes_dev * dd)456 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
457 {
458 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
459 }
460
atmel_aes_hw_version_init(struct atmel_aes_dev * dd)461 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
462 {
463 int err;
464
465 err = atmel_aes_hw_init(dd);
466 if (err)
467 return err;
468
469 dd->hw_version = atmel_aes_get_version(dd);
470
471 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
472
473 clk_disable(dd->iclk);
474 return 0;
475 }
476
atmel_aes_set_mode(struct atmel_aes_dev * dd,const struct atmel_aes_reqctx * rctx)477 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
478 const struct atmel_aes_reqctx *rctx)
479 {
480 /* Clear all but persistent flags and set request flags. */
481 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
482 }
483
atmel_aes_is_encrypt(const struct atmel_aes_dev * dd)484 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
485 {
486 return (dd->flags & AES_FLAGS_ENCRYPT);
487 }
488
489 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
490 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err);
491 #endif
492
atmel_aes_set_iv_as_last_ciphertext_block(struct atmel_aes_dev * dd)493 static void atmel_aes_set_iv_as_last_ciphertext_block(struct atmel_aes_dev *dd)
494 {
495 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
496 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
497 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
498 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
499
500 if (req->nbytes < ivsize)
501 return;
502
503 if (rctx->mode & AES_FLAGS_ENCRYPT) {
504 scatterwalk_map_and_copy(req->info, req->dst,
505 req->nbytes - ivsize, ivsize, 0);
506 } else {
507 if (req->src == req->dst)
508 memcpy(req->info, rctx->lastc, ivsize);
509 else
510 scatterwalk_map_and_copy(req->info, req->src,
511 req->nbytes - ivsize,
512 ivsize, 0);
513 }
514 }
515
atmel_aes_complete(struct atmel_aes_dev * dd,int err)516 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
517 {
518 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
519 if (dd->ctx->is_aead)
520 atmel_aes_authenc_complete(dd, err);
521 #endif
522
523 clk_disable(dd->iclk);
524 dd->flags &= ~AES_FLAGS_BUSY;
525
526 if (!dd->ctx->is_aead)
527 atmel_aes_set_iv_as_last_ciphertext_block(dd);
528
529 if (dd->is_async)
530 dd->areq->complete(dd->areq, err);
531
532 tasklet_schedule(&dd->queue_task);
533
534 return err;
535 }
536
atmel_aes_write_ctrl_key(struct atmel_aes_dev * dd,bool use_dma,const u32 * iv,const u32 * key,int keylen)537 static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
538 const u32 *iv, const u32 *key, int keylen)
539 {
540 u32 valmr = 0;
541
542 /* MR register must be set before IV registers */
543 if (keylen == AES_KEYSIZE_128)
544 valmr |= AES_MR_KEYSIZE_128;
545 else if (keylen == AES_KEYSIZE_192)
546 valmr |= AES_MR_KEYSIZE_192;
547 else
548 valmr |= AES_MR_KEYSIZE_256;
549
550 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
551
552 if (use_dma) {
553 valmr |= AES_MR_SMOD_IDATAR0;
554 if (dd->caps.has_dualbuff)
555 valmr |= AES_MR_DUALBUFF;
556 } else {
557 valmr |= AES_MR_SMOD_AUTO;
558 }
559
560 atmel_aes_write(dd, AES_MR, valmr);
561
562 atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
563
564 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
565 atmel_aes_write_block(dd, AES_IVR(0), iv);
566 }
567
atmel_aes_write_ctrl(struct atmel_aes_dev * dd,bool use_dma,const u32 * iv)568 static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
569 const u32 *iv)
570
571 {
572 atmel_aes_write_ctrl_key(dd, use_dma, iv,
573 dd->ctx->key, dd->ctx->keylen);
574 }
575
576 /* CPU transfer */
577
atmel_aes_cpu_transfer(struct atmel_aes_dev * dd)578 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
579 {
580 int err = 0;
581 u32 isr;
582
583 for (;;) {
584 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
585 dd->data += 4;
586 dd->datalen -= AES_BLOCK_SIZE;
587
588 if (dd->datalen < AES_BLOCK_SIZE)
589 break;
590
591 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
592
593 isr = atmel_aes_read(dd, AES_ISR);
594 if (!(isr & AES_INT_DATARDY)) {
595 dd->resume = atmel_aes_cpu_transfer;
596 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
597 return -EINPROGRESS;
598 }
599 }
600
601 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
602 dd->buf, dd->total))
603 err = -EINVAL;
604
605 if (err)
606 return atmel_aes_complete(dd, err);
607
608 return dd->cpu_transfer_complete(dd);
609 }
610
atmel_aes_cpu_start(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len,atmel_aes_fn_t resume)611 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
612 struct scatterlist *src,
613 struct scatterlist *dst,
614 size_t len,
615 atmel_aes_fn_t resume)
616 {
617 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
618
619 if (unlikely(len == 0))
620 return -EINVAL;
621
622 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
623
624 dd->total = len;
625 dd->real_dst = dst;
626 dd->cpu_transfer_complete = resume;
627 dd->datalen = len + padlen;
628 dd->data = (u32 *)dd->buf;
629 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
630 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
631 }
632
633
634 /* DMA transfer */
635
636 static void atmel_aes_dma_callback(void *data);
637
atmel_aes_check_aligned(struct atmel_aes_dev * dd,struct scatterlist * sg,size_t len,struct atmel_aes_dma * dma)638 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
639 struct scatterlist *sg,
640 size_t len,
641 struct atmel_aes_dma *dma)
642 {
643 int nents;
644
645 if (!IS_ALIGNED(len, dd->ctx->block_size))
646 return false;
647
648 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
649 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
650 return false;
651
652 if (len <= sg->length) {
653 if (!IS_ALIGNED(len, dd->ctx->block_size))
654 return false;
655
656 dma->nents = nents+1;
657 dma->remainder = sg->length - len;
658 sg->length = len;
659 return true;
660 }
661
662 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
663 return false;
664
665 len -= sg->length;
666 }
667
668 return false;
669 }
670
atmel_aes_restore_sg(const struct atmel_aes_dma * dma)671 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
672 {
673 struct scatterlist *sg = dma->sg;
674 int nents = dma->nents;
675
676 if (!dma->remainder)
677 return;
678
679 while (--nents > 0 && sg)
680 sg = sg_next(sg);
681
682 if (!sg)
683 return;
684
685 sg->length += dma->remainder;
686 }
687
atmel_aes_map(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len)688 static int atmel_aes_map(struct atmel_aes_dev *dd,
689 struct scatterlist *src,
690 struct scatterlist *dst,
691 size_t len)
692 {
693 bool src_aligned, dst_aligned;
694 size_t padlen;
695
696 dd->total = len;
697 dd->src.sg = src;
698 dd->dst.sg = dst;
699 dd->real_dst = dst;
700
701 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
702 if (src == dst)
703 dst_aligned = src_aligned;
704 else
705 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
706 if (!src_aligned || !dst_aligned) {
707 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
708
709 if (dd->buflen < len + padlen)
710 return -ENOMEM;
711
712 if (!src_aligned) {
713 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
714 dd->src.sg = &dd->aligned_sg;
715 dd->src.nents = 1;
716 dd->src.remainder = 0;
717 }
718
719 if (!dst_aligned) {
720 dd->dst.sg = &dd->aligned_sg;
721 dd->dst.nents = 1;
722 dd->dst.remainder = 0;
723 }
724
725 sg_init_table(&dd->aligned_sg, 1);
726 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
727 }
728
729 if (dd->src.sg == dd->dst.sg) {
730 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
731 DMA_BIDIRECTIONAL);
732 dd->dst.sg_len = dd->src.sg_len;
733 if (!dd->src.sg_len)
734 return -EFAULT;
735 } else {
736 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
737 DMA_TO_DEVICE);
738 if (!dd->src.sg_len)
739 return -EFAULT;
740
741 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
742 DMA_FROM_DEVICE);
743 if (!dd->dst.sg_len) {
744 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
745 DMA_TO_DEVICE);
746 return -EFAULT;
747 }
748 }
749
750 return 0;
751 }
752
atmel_aes_unmap(struct atmel_aes_dev * dd)753 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
754 {
755 if (dd->src.sg == dd->dst.sg) {
756 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
757 DMA_BIDIRECTIONAL);
758
759 if (dd->src.sg != &dd->aligned_sg)
760 atmel_aes_restore_sg(&dd->src);
761 } else {
762 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
763 DMA_FROM_DEVICE);
764
765 if (dd->dst.sg != &dd->aligned_sg)
766 atmel_aes_restore_sg(&dd->dst);
767
768 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
769 DMA_TO_DEVICE);
770
771 if (dd->src.sg != &dd->aligned_sg)
772 atmel_aes_restore_sg(&dd->src);
773 }
774
775 if (dd->dst.sg == &dd->aligned_sg)
776 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
777 dd->buf, dd->total);
778 }
779
atmel_aes_dma_transfer_start(struct atmel_aes_dev * dd,enum dma_slave_buswidth addr_width,enum dma_transfer_direction dir,u32 maxburst)780 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
781 enum dma_slave_buswidth addr_width,
782 enum dma_transfer_direction dir,
783 u32 maxburst)
784 {
785 struct dma_async_tx_descriptor *desc;
786 struct dma_slave_config config;
787 dma_async_tx_callback callback;
788 struct atmel_aes_dma *dma;
789 int err;
790
791 memset(&config, 0, sizeof(config));
792 config.direction = dir;
793 config.src_addr_width = addr_width;
794 config.dst_addr_width = addr_width;
795 config.src_maxburst = maxburst;
796 config.dst_maxburst = maxburst;
797
798 switch (dir) {
799 case DMA_MEM_TO_DEV:
800 dma = &dd->src;
801 callback = NULL;
802 config.dst_addr = dd->phys_base + AES_IDATAR(0);
803 break;
804
805 case DMA_DEV_TO_MEM:
806 dma = &dd->dst;
807 callback = atmel_aes_dma_callback;
808 config.src_addr = dd->phys_base + AES_ODATAR(0);
809 break;
810
811 default:
812 return -EINVAL;
813 }
814
815 err = dmaengine_slave_config(dma->chan, &config);
816 if (err)
817 return err;
818
819 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
820 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
821 if (!desc)
822 return -ENOMEM;
823
824 desc->callback = callback;
825 desc->callback_param = dd;
826 dmaengine_submit(desc);
827 dma_async_issue_pending(dma->chan);
828
829 return 0;
830 }
831
atmel_aes_dma_transfer_stop(struct atmel_aes_dev * dd,enum dma_transfer_direction dir)832 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
833 enum dma_transfer_direction dir)
834 {
835 struct atmel_aes_dma *dma;
836
837 switch (dir) {
838 case DMA_MEM_TO_DEV:
839 dma = &dd->src;
840 break;
841
842 case DMA_DEV_TO_MEM:
843 dma = &dd->dst;
844 break;
845
846 default:
847 return;
848 }
849
850 dmaengine_terminate_all(dma->chan);
851 }
852
atmel_aes_dma_start(struct atmel_aes_dev * dd,struct scatterlist * src,struct scatterlist * dst,size_t len,atmel_aes_fn_t resume)853 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
854 struct scatterlist *src,
855 struct scatterlist *dst,
856 size_t len,
857 atmel_aes_fn_t resume)
858 {
859 enum dma_slave_buswidth addr_width;
860 u32 maxburst;
861 int err;
862
863 switch (dd->ctx->block_size) {
864 case CFB8_BLOCK_SIZE:
865 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
866 maxburst = 1;
867 break;
868
869 case CFB16_BLOCK_SIZE:
870 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
871 maxburst = 1;
872 break;
873
874 case CFB32_BLOCK_SIZE:
875 case CFB64_BLOCK_SIZE:
876 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
877 maxburst = 1;
878 break;
879
880 case AES_BLOCK_SIZE:
881 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
882 maxburst = dd->caps.max_burst_size;
883 break;
884
885 default:
886 err = -EINVAL;
887 goto exit;
888 }
889
890 err = atmel_aes_map(dd, src, dst, len);
891 if (err)
892 goto exit;
893
894 dd->resume = resume;
895
896 /* Set output DMA transfer first */
897 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
898 maxburst);
899 if (err)
900 goto unmap;
901
902 /* Then set input DMA transfer */
903 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
904 maxburst);
905 if (err)
906 goto output_transfer_stop;
907
908 return -EINPROGRESS;
909
910 output_transfer_stop:
911 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
912 unmap:
913 atmel_aes_unmap(dd);
914 exit:
915 return atmel_aes_complete(dd, err);
916 }
917
atmel_aes_dma_stop(struct atmel_aes_dev * dd)918 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
919 {
920 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
921 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
922 atmel_aes_unmap(dd);
923 }
924
atmel_aes_dma_callback(void * data)925 static void atmel_aes_dma_callback(void *data)
926 {
927 struct atmel_aes_dev *dd = data;
928
929 atmel_aes_dma_stop(dd);
930 dd->is_async = true;
931 (void)dd->resume(dd);
932 }
933
atmel_aes_handle_queue(struct atmel_aes_dev * dd,struct crypto_async_request * new_areq)934 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
935 struct crypto_async_request *new_areq)
936 {
937 struct crypto_async_request *areq, *backlog;
938 struct atmel_aes_base_ctx *ctx;
939 unsigned long flags;
940 bool start_async;
941 int err, ret = 0;
942
943 spin_lock_irqsave(&dd->lock, flags);
944 if (new_areq)
945 ret = crypto_enqueue_request(&dd->queue, new_areq);
946 if (dd->flags & AES_FLAGS_BUSY) {
947 spin_unlock_irqrestore(&dd->lock, flags);
948 return ret;
949 }
950 backlog = crypto_get_backlog(&dd->queue);
951 areq = crypto_dequeue_request(&dd->queue);
952 if (areq)
953 dd->flags |= AES_FLAGS_BUSY;
954 spin_unlock_irqrestore(&dd->lock, flags);
955
956 if (!areq)
957 return ret;
958
959 if (backlog)
960 backlog->complete(backlog, -EINPROGRESS);
961
962 ctx = crypto_tfm_ctx(areq->tfm);
963
964 dd->areq = areq;
965 dd->ctx = ctx;
966 start_async = (areq != new_areq);
967 dd->is_async = start_async;
968
969 /* WARNING: ctx->start() MAY change dd->is_async. */
970 err = ctx->start(dd);
971 return (start_async) ? ret : err;
972 }
973
974
975 /* AES async block ciphers */
976
atmel_aes_transfer_complete(struct atmel_aes_dev * dd)977 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
978 {
979 return atmel_aes_complete(dd, 0);
980 }
981
atmel_aes_start(struct atmel_aes_dev * dd)982 static int atmel_aes_start(struct atmel_aes_dev *dd)
983 {
984 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
985 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
986 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
987 dd->ctx->block_size != AES_BLOCK_SIZE);
988 int err;
989
990 atmel_aes_set_mode(dd, rctx);
991
992 err = atmel_aes_hw_init(dd);
993 if (err)
994 return atmel_aes_complete(dd, err);
995
996 atmel_aes_write_ctrl(dd, use_dma, req->info);
997 if (use_dma)
998 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
999 atmel_aes_transfer_complete);
1000
1001 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1002 atmel_aes_transfer_complete);
1003 }
1004
1005 static inline struct atmel_aes_ctr_ctx *
atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx * ctx)1006 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
1007 {
1008 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
1009 }
1010
atmel_aes_ctr_transfer(struct atmel_aes_dev * dd)1011 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
1012 {
1013 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1014 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1015 struct scatterlist *src, *dst;
1016 u32 ctr, blocks;
1017 size_t datalen;
1018 bool use_dma, fragmented = false;
1019
1020 /* Check for transfer completion. */
1021 ctx->offset += dd->total;
1022 if (ctx->offset >= req->nbytes)
1023 return atmel_aes_transfer_complete(dd);
1024
1025 /* Compute data length. */
1026 datalen = req->nbytes - ctx->offset;
1027 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
1028 ctr = be32_to_cpu(ctx->iv[3]);
1029 if (dd->caps.has_ctr32) {
1030 /* Check 32bit counter overflow. */
1031 u32 start = ctr;
1032 u32 end = start + blocks - 1;
1033
1034 if (end < start) {
1035 ctr |= 0xffffffff;
1036 datalen = AES_BLOCK_SIZE * -start;
1037 fragmented = true;
1038 }
1039 } else {
1040 /* Check 16bit counter overflow. */
1041 u16 start = ctr & 0xffff;
1042 u16 end = start + (u16)blocks - 1;
1043
1044 if (blocks >> 16 || end < start) {
1045 ctr |= 0xffff;
1046 datalen = AES_BLOCK_SIZE * (0x10000-start);
1047 fragmented = true;
1048 }
1049 }
1050 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
1051
1052 /* Jump to offset. */
1053 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
1054 dst = ((req->src == req->dst) ? src :
1055 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
1056
1057 /* Configure hardware. */
1058 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
1059 if (unlikely(fragmented)) {
1060 /*
1061 * Increment the counter manually to cope with the hardware
1062 * counter overflow.
1063 */
1064 ctx->iv[3] = cpu_to_be32(ctr);
1065 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
1066 }
1067
1068 if (use_dma)
1069 return atmel_aes_dma_start(dd, src, dst, datalen,
1070 atmel_aes_ctr_transfer);
1071
1072 return atmel_aes_cpu_start(dd, src, dst, datalen,
1073 atmel_aes_ctr_transfer);
1074 }
1075
atmel_aes_ctr_start(struct atmel_aes_dev * dd)1076 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
1077 {
1078 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1079 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1080 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1081 int err;
1082
1083 atmel_aes_set_mode(dd, rctx);
1084
1085 err = atmel_aes_hw_init(dd);
1086 if (err)
1087 return atmel_aes_complete(dd, err);
1088
1089 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1090 ctx->offset = 0;
1091 dd->total = 0;
1092 return atmel_aes_ctr_transfer(dd);
1093 }
1094
atmel_aes_crypt(struct ablkcipher_request * req,unsigned long mode)1095 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1096 {
1097 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1098 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1099 struct atmel_aes_reqctx *rctx;
1100 struct atmel_aes_dev *dd;
1101
1102 switch (mode & AES_FLAGS_OPMODE_MASK) {
1103 case AES_FLAGS_CFB8:
1104 ctx->block_size = CFB8_BLOCK_SIZE;
1105 break;
1106
1107 case AES_FLAGS_CFB16:
1108 ctx->block_size = CFB16_BLOCK_SIZE;
1109 break;
1110
1111 case AES_FLAGS_CFB32:
1112 ctx->block_size = CFB32_BLOCK_SIZE;
1113 break;
1114
1115 case AES_FLAGS_CFB64:
1116 ctx->block_size = CFB64_BLOCK_SIZE;
1117 break;
1118
1119 default:
1120 ctx->block_size = AES_BLOCK_SIZE;
1121 break;
1122 }
1123 ctx->is_aead = false;
1124
1125 dd = atmel_aes_find_dev(ctx);
1126 if (!dd)
1127 return -ENODEV;
1128
1129 rctx = ablkcipher_request_ctx(req);
1130 rctx->mode = mode;
1131
1132 if (!(mode & AES_FLAGS_ENCRYPT) && (req->src == req->dst)) {
1133 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
1134
1135 if (req->nbytes >= ivsize)
1136 scatterwalk_map_and_copy(rctx->lastc, req->src,
1137 req->nbytes - ivsize,
1138 ivsize, 0);
1139 }
1140
1141 return atmel_aes_handle_queue(dd, &req->base);
1142 }
1143
atmel_aes_setkey(struct crypto_ablkcipher * tfm,const u8 * key,unsigned int keylen)1144 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1145 unsigned int keylen)
1146 {
1147 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1148
1149 if (keylen != AES_KEYSIZE_128 &&
1150 keylen != AES_KEYSIZE_192 &&
1151 keylen != AES_KEYSIZE_256) {
1152 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1153 return -EINVAL;
1154 }
1155
1156 memcpy(ctx->key, key, keylen);
1157 ctx->keylen = keylen;
1158
1159 return 0;
1160 }
1161
atmel_aes_ecb_encrypt(struct ablkcipher_request * req)1162 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1163 {
1164 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1165 }
1166
atmel_aes_ecb_decrypt(struct ablkcipher_request * req)1167 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1168 {
1169 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1170 }
1171
atmel_aes_cbc_encrypt(struct ablkcipher_request * req)1172 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1173 {
1174 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1175 }
1176
atmel_aes_cbc_decrypt(struct ablkcipher_request * req)1177 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1178 {
1179 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1180 }
1181
atmel_aes_ofb_encrypt(struct ablkcipher_request * req)1182 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1183 {
1184 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1185 }
1186
atmel_aes_ofb_decrypt(struct ablkcipher_request * req)1187 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1188 {
1189 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1190 }
1191
atmel_aes_cfb_encrypt(struct ablkcipher_request * req)1192 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1193 {
1194 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1195 }
1196
atmel_aes_cfb_decrypt(struct ablkcipher_request * req)1197 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1198 {
1199 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1200 }
1201
atmel_aes_cfb64_encrypt(struct ablkcipher_request * req)1202 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1203 {
1204 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1205 }
1206
atmel_aes_cfb64_decrypt(struct ablkcipher_request * req)1207 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1208 {
1209 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1210 }
1211
atmel_aes_cfb32_encrypt(struct ablkcipher_request * req)1212 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1213 {
1214 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1215 }
1216
atmel_aes_cfb32_decrypt(struct ablkcipher_request * req)1217 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1218 {
1219 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1220 }
1221
atmel_aes_cfb16_encrypt(struct ablkcipher_request * req)1222 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1223 {
1224 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1225 }
1226
atmel_aes_cfb16_decrypt(struct ablkcipher_request * req)1227 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1228 {
1229 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1230 }
1231
atmel_aes_cfb8_encrypt(struct ablkcipher_request * req)1232 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1233 {
1234 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1235 }
1236
atmel_aes_cfb8_decrypt(struct ablkcipher_request * req)1237 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1238 {
1239 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1240 }
1241
atmel_aes_ctr_encrypt(struct ablkcipher_request * req)1242 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1243 {
1244 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1245 }
1246
atmel_aes_ctr_decrypt(struct ablkcipher_request * req)1247 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1248 {
1249 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1250 }
1251
atmel_aes_cra_init(struct crypto_tfm * tfm)1252 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1253 {
1254 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1255
1256 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1257 ctx->base.start = atmel_aes_start;
1258
1259 return 0;
1260 }
1261
atmel_aes_ctr_cra_init(struct crypto_tfm * tfm)1262 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1263 {
1264 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1265
1266 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1267 ctx->base.start = atmel_aes_ctr_start;
1268
1269 return 0;
1270 }
1271
1272 static struct crypto_alg aes_algs[] = {
1273 {
1274 .cra_name = "ecb(aes)",
1275 .cra_driver_name = "atmel-ecb-aes",
1276 .cra_priority = ATMEL_AES_PRIORITY,
1277 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1278 .cra_blocksize = AES_BLOCK_SIZE,
1279 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1280 .cra_alignmask = 0xf,
1281 .cra_type = &crypto_ablkcipher_type,
1282 .cra_module = THIS_MODULE,
1283 .cra_init = atmel_aes_cra_init,
1284 .cra_u.ablkcipher = {
1285 .min_keysize = AES_MIN_KEY_SIZE,
1286 .max_keysize = AES_MAX_KEY_SIZE,
1287 .setkey = atmel_aes_setkey,
1288 .encrypt = atmel_aes_ecb_encrypt,
1289 .decrypt = atmel_aes_ecb_decrypt,
1290 }
1291 },
1292 {
1293 .cra_name = "cbc(aes)",
1294 .cra_driver_name = "atmel-cbc-aes",
1295 .cra_priority = ATMEL_AES_PRIORITY,
1296 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1297 .cra_blocksize = AES_BLOCK_SIZE,
1298 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1299 .cra_alignmask = 0xf,
1300 .cra_type = &crypto_ablkcipher_type,
1301 .cra_module = THIS_MODULE,
1302 .cra_init = atmel_aes_cra_init,
1303 .cra_u.ablkcipher = {
1304 .min_keysize = AES_MIN_KEY_SIZE,
1305 .max_keysize = AES_MAX_KEY_SIZE,
1306 .ivsize = AES_BLOCK_SIZE,
1307 .setkey = atmel_aes_setkey,
1308 .encrypt = atmel_aes_cbc_encrypt,
1309 .decrypt = atmel_aes_cbc_decrypt,
1310 }
1311 },
1312 {
1313 .cra_name = "ofb(aes)",
1314 .cra_driver_name = "atmel-ofb-aes",
1315 .cra_priority = ATMEL_AES_PRIORITY,
1316 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1317 .cra_blocksize = AES_BLOCK_SIZE,
1318 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1319 .cra_alignmask = 0xf,
1320 .cra_type = &crypto_ablkcipher_type,
1321 .cra_module = THIS_MODULE,
1322 .cra_init = atmel_aes_cra_init,
1323 .cra_u.ablkcipher = {
1324 .min_keysize = AES_MIN_KEY_SIZE,
1325 .max_keysize = AES_MAX_KEY_SIZE,
1326 .ivsize = AES_BLOCK_SIZE,
1327 .setkey = atmel_aes_setkey,
1328 .encrypt = atmel_aes_ofb_encrypt,
1329 .decrypt = atmel_aes_ofb_decrypt,
1330 }
1331 },
1332 {
1333 .cra_name = "cfb(aes)",
1334 .cra_driver_name = "atmel-cfb-aes",
1335 .cra_priority = ATMEL_AES_PRIORITY,
1336 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1337 .cra_blocksize = AES_BLOCK_SIZE,
1338 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1339 .cra_alignmask = 0xf,
1340 .cra_type = &crypto_ablkcipher_type,
1341 .cra_module = THIS_MODULE,
1342 .cra_init = atmel_aes_cra_init,
1343 .cra_u.ablkcipher = {
1344 .min_keysize = AES_MIN_KEY_SIZE,
1345 .max_keysize = AES_MAX_KEY_SIZE,
1346 .ivsize = AES_BLOCK_SIZE,
1347 .setkey = atmel_aes_setkey,
1348 .encrypt = atmel_aes_cfb_encrypt,
1349 .decrypt = atmel_aes_cfb_decrypt,
1350 }
1351 },
1352 {
1353 .cra_name = "cfb32(aes)",
1354 .cra_driver_name = "atmel-cfb32-aes",
1355 .cra_priority = ATMEL_AES_PRIORITY,
1356 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1357 .cra_blocksize = CFB32_BLOCK_SIZE,
1358 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1359 .cra_alignmask = 0x3,
1360 .cra_type = &crypto_ablkcipher_type,
1361 .cra_module = THIS_MODULE,
1362 .cra_init = atmel_aes_cra_init,
1363 .cra_u.ablkcipher = {
1364 .min_keysize = AES_MIN_KEY_SIZE,
1365 .max_keysize = AES_MAX_KEY_SIZE,
1366 .ivsize = AES_BLOCK_SIZE,
1367 .setkey = atmel_aes_setkey,
1368 .encrypt = atmel_aes_cfb32_encrypt,
1369 .decrypt = atmel_aes_cfb32_decrypt,
1370 }
1371 },
1372 {
1373 .cra_name = "cfb16(aes)",
1374 .cra_driver_name = "atmel-cfb16-aes",
1375 .cra_priority = ATMEL_AES_PRIORITY,
1376 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1377 .cra_blocksize = CFB16_BLOCK_SIZE,
1378 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1379 .cra_alignmask = 0x1,
1380 .cra_type = &crypto_ablkcipher_type,
1381 .cra_module = THIS_MODULE,
1382 .cra_init = atmel_aes_cra_init,
1383 .cra_u.ablkcipher = {
1384 .min_keysize = AES_MIN_KEY_SIZE,
1385 .max_keysize = AES_MAX_KEY_SIZE,
1386 .ivsize = AES_BLOCK_SIZE,
1387 .setkey = atmel_aes_setkey,
1388 .encrypt = atmel_aes_cfb16_encrypt,
1389 .decrypt = atmel_aes_cfb16_decrypt,
1390 }
1391 },
1392 {
1393 .cra_name = "cfb8(aes)",
1394 .cra_driver_name = "atmel-cfb8-aes",
1395 .cra_priority = ATMEL_AES_PRIORITY,
1396 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1397 .cra_blocksize = CFB8_BLOCK_SIZE,
1398 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1399 .cra_alignmask = 0x0,
1400 .cra_type = &crypto_ablkcipher_type,
1401 .cra_module = THIS_MODULE,
1402 .cra_init = atmel_aes_cra_init,
1403 .cra_u.ablkcipher = {
1404 .min_keysize = AES_MIN_KEY_SIZE,
1405 .max_keysize = AES_MAX_KEY_SIZE,
1406 .ivsize = AES_BLOCK_SIZE,
1407 .setkey = atmel_aes_setkey,
1408 .encrypt = atmel_aes_cfb8_encrypt,
1409 .decrypt = atmel_aes_cfb8_decrypt,
1410 }
1411 },
1412 {
1413 .cra_name = "ctr(aes)",
1414 .cra_driver_name = "atmel-ctr-aes",
1415 .cra_priority = ATMEL_AES_PRIORITY,
1416 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1417 .cra_blocksize = 1,
1418 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1419 .cra_alignmask = 0xf,
1420 .cra_type = &crypto_ablkcipher_type,
1421 .cra_module = THIS_MODULE,
1422 .cra_init = atmel_aes_ctr_cra_init,
1423 .cra_u.ablkcipher = {
1424 .min_keysize = AES_MIN_KEY_SIZE,
1425 .max_keysize = AES_MAX_KEY_SIZE,
1426 .ivsize = AES_BLOCK_SIZE,
1427 .setkey = atmel_aes_setkey,
1428 .encrypt = atmel_aes_ctr_encrypt,
1429 .decrypt = atmel_aes_ctr_decrypt,
1430 }
1431 },
1432 };
1433
1434 static struct crypto_alg aes_cfb64_alg = {
1435 .cra_name = "cfb64(aes)",
1436 .cra_driver_name = "atmel-cfb64-aes",
1437 .cra_priority = ATMEL_AES_PRIORITY,
1438 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1439 .cra_blocksize = CFB64_BLOCK_SIZE,
1440 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1441 .cra_alignmask = 0x7,
1442 .cra_type = &crypto_ablkcipher_type,
1443 .cra_module = THIS_MODULE,
1444 .cra_init = atmel_aes_cra_init,
1445 .cra_u.ablkcipher = {
1446 .min_keysize = AES_MIN_KEY_SIZE,
1447 .max_keysize = AES_MAX_KEY_SIZE,
1448 .ivsize = AES_BLOCK_SIZE,
1449 .setkey = atmel_aes_setkey,
1450 .encrypt = atmel_aes_cfb64_encrypt,
1451 .decrypt = atmel_aes_cfb64_decrypt,
1452 }
1453 };
1454
1455
1456 /* gcm aead functions */
1457
1458 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1459 const u32 *data, size_t datalen,
1460 const u32 *ghash_in, u32 *ghash_out,
1461 atmel_aes_fn_t resume);
1462 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1463 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1464
1465 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1466 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1467 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1468 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1469 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1470 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1471 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1472
1473 static inline struct atmel_aes_gcm_ctx *
atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx * ctx)1474 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1475 {
1476 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1477 }
1478
atmel_aes_gcm_ghash(struct atmel_aes_dev * dd,const u32 * data,size_t datalen,const u32 * ghash_in,u32 * ghash_out,atmel_aes_fn_t resume)1479 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1480 const u32 *data, size_t datalen,
1481 const u32 *ghash_in, u32 *ghash_out,
1482 atmel_aes_fn_t resume)
1483 {
1484 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1485
1486 dd->data = (u32 *)data;
1487 dd->datalen = datalen;
1488 ctx->ghash_in = ghash_in;
1489 ctx->ghash_out = ghash_out;
1490 ctx->ghash_resume = resume;
1491
1492 atmel_aes_write_ctrl(dd, false, NULL);
1493 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1494 }
1495
atmel_aes_gcm_ghash_init(struct atmel_aes_dev * dd)1496 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1497 {
1498 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1499
1500 /* Set the data length. */
1501 atmel_aes_write(dd, AES_AADLENR, dd->total);
1502 atmel_aes_write(dd, AES_CLENR, 0);
1503
1504 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1505 if (ctx->ghash_in)
1506 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1507
1508 return atmel_aes_gcm_ghash_finalize(dd);
1509 }
1510
atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev * dd)1511 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1512 {
1513 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1514 u32 isr;
1515
1516 /* Write data into the Input Data Registers. */
1517 while (dd->datalen > 0) {
1518 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1519 dd->data += 4;
1520 dd->datalen -= AES_BLOCK_SIZE;
1521
1522 isr = atmel_aes_read(dd, AES_ISR);
1523 if (!(isr & AES_INT_DATARDY)) {
1524 dd->resume = atmel_aes_gcm_ghash_finalize;
1525 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1526 return -EINPROGRESS;
1527 }
1528 }
1529
1530 /* Read the computed hash from GHASHRx. */
1531 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1532
1533 return ctx->ghash_resume(dd);
1534 }
1535
1536
atmel_aes_gcm_start(struct atmel_aes_dev * dd)1537 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1538 {
1539 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1540 struct aead_request *req = aead_request_cast(dd->areq);
1541 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1542 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1543 size_t ivsize = crypto_aead_ivsize(tfm);
1544 size_t datalen, padlen;
1545 const void *iv = req->iv;
1546 u8 *data = dd->buf;
1547 int err;
1548
1549 atmel_aes_set_mode(dd, rctx);
1550
1551 err = atmel_aes_hw_init(dd);
1552 if (err)
1553 return atmel_aes_complete(dd, err);
1554
1555 if (likely(ivsize == GCM_AES_IV_SIZE)) {
1556 memcpy(ctx->j0, iv, ivsize);
1557 ctx->j0[3] = cpu_to_be32(1);
1558 return atmel_aes_gcm_process(dd);
1559 }
1560
1561 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1562 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1563 if (datalen > dd->buflen)
1564 return atmel_aes_complete(dd, -EINVAL);
1565
1566 memcpy(data, iv, ivsize);
1567 memset(data + ivsize, 0, padlen + sizeof(u64));
1568 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1569
1570 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1571 NULL, ctx->j0, atmel_aes_gcm_process);
1572 }
1573
atmel_aes_gcm_process(struct atmel_aes_dev * dd)1574 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1575 {
1576 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1577 struct aead_request *req = aead_request_cast(dd->areq);
1578 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1579 bool enc = atmel_aes_is_encrypt(dd);
1580 u32 authsize;
1581
1582 /* Compute text length. */
1583 authsize = crypto_aead_authsize(tfm);
1584 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1585
1586 /*
1587 * According to tcrypt test suite, the GCM Automatic Tag Generation
1588 * fails when both the message and its associated data are empty.
1589 */
1590 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1591 dd->flags |= AES_FLAGS_GTAGEN;
1592
1593 atmel_aes_write_ctrl(dd, false, NULL);
1594 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1595 }
1596
atmel_aes_gcm_length(struct atmel_aes_dev * dd)1597 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1598 {
1599 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1600 struct aead_request *req = aead_request_cast(dd->areq);
1601 u32 j0_lsw, *j0 = ctx->j0;
1602 size_t padlen;
1603
1604 /* Write incr32(J0) into IV. */
1605 j0_lsw = j0[3];
1606 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1607 atmel_aes_write_block(dd, AES_IVR(0), j0);
1608 j0[3] = j0_lsw;
1609
1610 /* Set aad and text lengths. */
1611 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1612 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1613
1614 /* Check whether AAD are present. */
1615 if (unlikely(req->assoclen == 0)) {
1616 dd->datalen = 0;
1617 return atmel_aes_gcm_data(dd);
1618 }
1619
1620 /* Copy assoc data and add padding. */
1621 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1622 if (unlikely(req->assoclen + padlen > dd->buflen))
1623 return atmel_aes_complete(dd, -EINVAL);
1624 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1625
1626 /* Write assoc data into the Input Data register. */
1627 dd->data = (u32 *)dd->buf;
1628 dd->datalen = req->assoclen + padlen;
1629 return atmel_aes_gcm_data(dd);
1630 }
1631
atmel_aes_gcm_data(struct atmel_aes_dev * dd)1632 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1633 {
1634 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1635 struct aead_request *req = aead_request_cast(dd->areq);
1636 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1637 struct scatterlist *src, *dst;
1638 u32 isr, mr;
1639
1640 /* Write AAD first. */
1641 while (dd->datalen > 0) {
1642 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1643 dd->data += 4;
1644 dd->datalen -= AES_BLOCK_SIZE;
1645
1646 isr = atmel_aes_read(dd, AES_ISR);
1647 if (!(isr & AES_INT_DATARDY)) {
1648 dd->resume = atmel_aes_gcm_data;
1649 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1650 return -EINPROGRESS;
1651 }
1652 }
1653
1654 /* GMAC only. */
1655 if (unlikely(ctx->textlen == 0))
1656 return atmel_aes_gcm_tag_init(dd);
1657
1658 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1659 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1660 dst = ((req->src == req->dst) ? src :
1661 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1662
1663 if (use_dma) {
1664 /* Update the Mode Register for DMA transfers. */
1665 mr = atmel_aes_read(dd, AES_MR);
1666 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1667 mr |= AES_MR_SMOD_IDATAR0;
1668 if (dd->caps.has_dualbuff)
1669 mr |= AES_MR_DUALBUFF;
1670 atmel_aes_write(dd, AES_MR, mr);
1671
1672 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1673 atmel_aes_gcm_tag_init);
1674 }
1675
1676 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1677 atmel_aes_gcm_tag_init);
1678 }
1679
atmel_aes_gcm_tag_init(struct atmel_aes_dev * dd)1680 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1681 {
1682 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1683 struct aead_request *req = aead_request_cast(dd->areq);
1684 u64 *data = dd->buf;
1685
1686 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1687 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1688 dd->resume = atmel_aes_gcm_tag_init;
1689 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1690 return -EINPROGRESS;
1691 }
1692
1693 return atmel_aes_gcm_finalize(dd);
1694 }
1695
1696 /* Read the GCM Intermediate Hash Word Registers. */
1697 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1698
1699 data[0] = cpu_to_be64(req->assoclen * 8);
1700 data[1] = cpu_to_be64(ctx->textlen * 8);
1701
1702 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1703 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1704 }
1705
atmel_aes_gcm_tag(struct atmel_aes_dev * dd)1706 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1707 {
1708 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1709 unsigned long flags;
1710
1711 /*
1712 * Change mode to CTR to complete the tag generation.
1713 * Use J0 as Initialization Vector.
1714 */
1715 flags = dd->flags;
1716 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1717 dd->flags |= AES_FLAGS_CTR;
1718 atmel_aes_write_ctrl(dd, false, ctx->j0);
1719 dd->flags = flags;
1720
1721 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1722 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1723 }
1724
atmel_aes_gcm_finalize(struct atmel_aes_dev * dd)1725 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1726 {
1727 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1728 struct aead_request *req = aead_request_cast(dd->areq);
1729 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1730 bool enc = atmel_aes_is_encrypt(dd);
1731 u32 offset, authsize, itag[4], *otag = ctx->tag;
1732 int err;
1733
1734 /* Read the computed tag. */
1735 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1736 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1737 else
1738 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1739
1740 offset = req->assoclen + ctx->textlen;
1741 authsize = crypto_aead_authsize(tfm);
1742 if (enc) {
1743 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1744 err = 0;
1745 } else {
1746 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1747 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1748 }
1749
1750 return atmel_aes_complete(dd, err);
1751 }
1752
atmel_aes_gcm_crypt(struct aead_request * req,unsigned long mode)1753 static int atmel_aes_gcm_crypt(struct aead_request *req,
1754 unsigned long mode)
1755 {
1756 struct atmel_aes_base_ctx *ctx;
1757 struct atmel_aes_reqctx *rctx;
1758 struct atmel_aes_dev *dd;
1759
1760 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1761 ctx->block_size = AES_BLOCK_SIZE;
1762 ctx->is_aead = true;
1763
1764 dd = atmel_aes_find_dev(ctx);
1765 if (!dd)
1766 return -ENODEV;
1767
1768 rctx = aead_request_ctx(req);
1769 rctx->mode = AES_FLAGS_GCM | mode;
1770
1771 return atmel_aes_handle_queue(dd, &req->base);
1772 }
1773
atmel_aes_gcm_setkey(struct crypto_aead * tfm,const u8 * key,unsigned int keylen)1774 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1775 unsigned int keylen)
1776 {
1777 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1778
1779 if (keylen != AES_KEYSIZE_256 &&
1780 keylen != AES_KEYSIZE_192 &&
1781 keylen != AES_KEYSIZE_128) {
1782 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1783 return -EINVAL;
1784 }
1785
1786 memcpy(ctx->key, key, keylen);
1787 ctx->keylen = keylen;
1788
1789 return 0;
1790 }
1791
atmel_aes_gcm_setauthsize(struct crypto_aead * tfm,unsigned int authsize)1792 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1793 unsigned int authsize)
1794 {
1795 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1796 switch (authsize) {
1797 case 4:
1798 case 8:
1799 case 12:
1800 case 13:
1801 case 14:
1802 case 15:
1803 case 16:
1804 break;
1805 default:
1806 return -EINVAL;
1807 }
1808
1809 return 0;
1810 }
1811
atmel_aes_gcm_encrypt(struct aead_request * req)1812 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1813 {
1814 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1815 }
1816
atmel_aes_gcm_decrypt(struct aead_request * req)1817 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1818 {
1819 return atmel_aes_gcm_crypt(req, 0);
1820 }
1821
atmel_aes_gcm_init(struct crypto_aead * tfm)1822 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1823 {
1824 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1825
1826 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1827 ctx->base.start = atmel_aes_gcm_start;
1828
1829 return 0;
1830 }
1831
1832 static struct aead_alg aes_gcm_alg = {
1833 .setkey = atmel_aes_gcm_setkey,
1834 .setauthsize = atmel_aes_gcm_setauthsize,
1835 .encrypt = atmel_aes_gcm_encrypt,
1836 .decrypt = atmel_aes_gcm_decrypt,
1837 .init = atmel_aes_gcm_init,
1838 .ivsize = GCM_AES_IV_SIZE,
1839 .maxauthsize = AES_BLOCK_SIZE,
1840
1841 .base = {
1842 .cra_name = "gcm(aes)",
1843 .cra_driver_name = "atmel-gcm-aes",
1844 .cra_priority = ATMEL_AES_PRIORITY,
1845 .cra_flags = CRYPTO_ALG_ASYNC,
1846 .cra_blocksize = 1,
1847 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1848 .cra_alignmask = 0xf,
1849 .cra_module = THIS_MODULE,
1850 },
1851 };
1852
1853
1854 /* xts functions */
1855
1856 static inline struct atmel_aes_xts_ctx *
atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx * ctx)1857 atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
1858 {
1859 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1860 }
1861
1862 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
1863
atmel_aes_xts_start(struct atmel_aes_dev * dd)1864 static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
1865 {
1866 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
1867 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1868 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1869 unsigned long flags;
1870 int err;
1871
1872 atmel_aes_set_mode(dd, rctx);
1873
1874 err = atmel_aes_hw_init(dd);
1875 if (err)
1876 return atmel_aes_complete(dd, err);
1877
1878 /* Compute the tweak value from req->info with ecb(aes). */
1879 flags = dd->flags;
1880 dd->flags &= ~AES_FLAGS_MODE_MASK;
1881 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1882 atmel_aes_write_ctrl_key(dd, false, NULL,
1883 ctx->key2, ctx->base.keylen);
1884 dd->flags = flags;
1885
1886 atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
1887 return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
1888 }
1889
atmel_aes_xts_process_data(struct atmel_aes_dev * dd)1890 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
1891 {
1892 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1893 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
1894 u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
1895 static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
1896 u8 *tweak_bytes = (u8 *)tweak;
1897 int i;
1898
1899 /* Read the computed ciphered tweak value. */
1900 atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
1901 /*
1902 * Hardware quirk:
1903 * the order of the ciphered tweak bytes need to be reversed before
1904 * writing them into the ODATARx registers.
1905 */
1906 for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
1907 u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
1908
1909 tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
1910 tweak_bytes[i] = tmp;
1911 }
1912
1913 /* Process the data. */
1914 atmel_aes_write_ctrl(dd, use_dma, NULL);
1915 atmel_aes_write_block(dd, AES_TWR(0), tweak);
1916 atmel_aes_write_block(dd, AES_ALPHAR(0), one);
1917 if (use_dma)
1918 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1919 atmel_aes_transfer_complete);
1920
1921 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1922 atmel_aes_transfer_complete);
1923 }
1924
atmel_aes_xts_setkey(struct crypto_ablkcipher * tfm,const u8 * key,unsigned int keylen)1925 static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1926 unsigned int keylen)
1927 {
1928 struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1929 int err;
1930
1931 err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
1932 if (err)
1933 return err;
1934
1935 memcpy(ctx->base.key, key, keylen/2);
1936 memcpy(ctx->key2, key + keylen/2, keylen/2);
1937 ctx->base.keylen = keylen/2;
1938
1939 return 0;
1940 }
1941
atmel_aes_xts_encrypt(struct ablkcipher_request * req)1942 static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
1943 {
1944 return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
1945 }
1946
atmel_aes_xts_decrypt(struct ablkcipher_request * req)1947 static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
1948 {
1949 return atmel_aes_crypt(req, AES_FLAGS_XTS);
1950 }
1951
atmel_aes_xts_cra_init(struct crypto_tfm * tfm)1952 static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
1953 {
1954 struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
1955
1956 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1957 ctx->base.start = atmel_aes_xts_start;
1958
1959 return 0;
1960 }
1961
1962 static struct crypto_alg aes_xts_alg = {
1963 .cra_name = "xts(aes)",
1964 .cra_driver_name = "atmel-xts-aes",
1965 .cra_priority = ATMEL_AES_PRIORITY,
1966 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1967 .cra_blocksize = AES_BLOCK_SIZE,
1968 .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1969 .cra_alignmask = 0xf,
1970 .cra_type = &crypto_ablkcipher_type,
1971 .cra_module = THIS_MODULE,
1972 .cra_init = atmel_aes_xts_cra_init,
1973 .cra_u.ablkcipher = {
1974 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1975 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1976 .ivsize = AES_BLOCK_SIZE,
1977 .setkey = atmel_aes_xts_setkey,
1978 .encrypt = atmel_aes_xts_encrypt,
1979 .decrypt = atmel_aes_xts_decrypt,
1980 }
1981 };
1982
1983 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
1984 /* authenc aead functions */
1985
1986 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd);
1987 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
1988 bool is_async);
1989 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
1990 bool is_async);
1991 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd);
1992 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
1993 bool is_async);
1994
atmel_aes_authenc_complete(struct atmel_aes_dev * dd,int err)1995 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err)
1996 {
1997 struct aead_request *req = aead_request_cast(dd->areq);
1998 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
1999
2000 if (err && (dd->flags & AES_FLAGS_OWN_SHA))
2001 atmel_sha_authenc_abort(&rctx->auth_req);
2002 dd->flags &= ~AES_FLAGS_OWN_SHA;
2003 }
2004
atmel_aes_authenc_start(struct atmel_aes_dev * dd)2005 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd)
2006 {
2007 struct aead_request *req = aead_request_cast(dd->areq);
2008 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2009 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2010 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2011 int err;
2012
2013 atmel_aes_set_mode(dd, &rctx->base);
2014
2015 err = atmel_aes_hw_init(dd);
2016 if (err)
2017 return atmel_aes_complete(dd, err);
2018
2019 return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth,
2020 atmel_aes_authenc_init, dd);
2021 }
2022
atmel_aes_authenc_init(struct atmel_aes_dev * dd,int err,bool is_async)2023 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
2024 bool is_async)
2025 {
2026 struct aead_request *req = aead_request_cast(dd->areq);
2027 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2028
2029 if (is_async)
2030 dd->is_async = true;
2031 if (err)
2032 return atmel_aes_complete(dd, err);
2033
2034 /* If here, we've got the ownership of the SHA device. */
2035 dd->flags |= AES_FLAGS_OWN_SHA;
2036
2037 /* Configure the SHA device. */
2038 return atmel_sha_authenc_init(&rctx->auth_req,
2039 req->src, req->assoclen,
2040 rctx->textlen,
2041 atmel_aes_authenc_transfer, dd);
2042 }
2043
atmel_aes_authenc_transfer(struct atmel_aes_dev * dd,int err,bool is_async)2044 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
2045 bool is_async)
2046 {
2047 struct aead_request *req = aead_request_cast(dd->areq);
2048 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2049 bool enc = atmel_aes_is_encrypt(dd);
2050 struct scatterlist *src, *dst;
2051 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
2052 u32 emr;
2053
2054 if (is_async)
2055 dd->is_async = true;
2056 if (err)
2057 return atmel_aes_complete(dd, err);
2058
2059 /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */
2060 src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen);
2061 dst = src;
2062
2063 if (req->src != req->dst)
2064 dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen);
2065
2066 /* Configure the AES device. */
2067 memcpy(iv, req->iv, sizeof(iv));
2068
2069 /*
2070 * Here we always set the 2nd parameter of atmel_aes_write_ctrl() to
2071 * 'true' even if the data transfer is actually performed by the CPU (so
2072 * not by the DMA) because we must force the AES_MR_SMOD bitfield to the
2073 * value AES_MR_SMOD_IDATAR0. Indeed, both AES_MR_SMOD and SHA_MR_SMOD
2074 * must be set to *_MR_SMOD_IDATAR0.
2075 */
2076 atmel_aes_write_ctrl(dd, true, iv);
2077 emr = AES_EMR_PLIPEN;
2078 if (!enc)
2079 emr |= AES_EMR_PLIPD;
2080 atmel_aes_write(dd, AES_EMR, emr);
2081
2082 /* Transfer data. */
2083 return atmel_aes_dma_start(dd, src, dst, rctx->textlen,
2084 atmel_aes_authenc_digest);
2085 }
2086
atmel_aes_authenc_digest(struct atmel_aes_dev * dd)2087 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd)
2088 {
2089 struct aead_request *req = aead_request_cast(dd->areq);
2090 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2091
2092 /* atmel_sha_authenc_final() releases the SHA device. */
2093 dd->flags &= ~AES_FLAGS_OWN_SHA;
2094 return atmel_sha_authenc_final(&rctx->auth_req,
2095 rctx->digest, sizeof(rctx->digest),
2096 atmel_aes_authenc_final, dd);
2097 }
2098
atmel_aes_authenc_final(struct atmel_aes_dev * dd,int err,bool is_async)2099 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
2100 bool is_async)
2101 {
2102 struct aead_request *req = aead_request_cast(dd->areq);
2103 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2104 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2105 bool enc = atmel_aes_is_encrypt(dd);
2106 u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest;
2107 u32 offs, authsize;
2108
2109 if (is_async)
2110 dd->is_async = true;
2111 if (err)
2112 goto complete;
2113
2114 offs = req->assoclen + rctx->textlen;
2115 authsize = crypto_aead_authsize(tfm);
2116 if (enc) {
2117 scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1);
2118 } else {
2119 scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0);
2120 if (crypto_memneq(idigest, odigest, authsize))
2121 err = -EBADMSG;
2122 }
2123
2124 complete:
2125 return atmel_aes_complete(dd, err);
2126 }
2127
atmel_aes_authenc_setkey(struct crypto_aead * tfm,const u8 * key,unsigned int keylen)2128 static int atmel_aes_authenc_setkey(struct crypto_aead *tfm, const u8 *key,
2129 unsigned int keylen)
2130 {
2131 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2132 struct crypto_authenc_keys keys;
2133 u32 flags;
2134 int err;
2135
2136 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
2137 goto badkey;
2138
2139 if (keys.enckeylen > sizeof(ctx->base.key))
2140 goto badkey;
2141
2142 /* Save auth key. */
2143 flags = crypto_aead_get_flags(tfm);
2144 err = atmel_sha_authenc_setkey(ctx->auth,
2145 keys.authkey, keys.authkeylen,
2146 &flags);
2147 crypto_aead_set_flags(tfm, flags & CRYPTO_TFM_RES_MASK);
2148 if (err) {
2149 memzero_explicit(&keys, sizeof(keys));
2150 return err;
2151 }
2152
2153 /* Save enc key. */
2154 ctx->base.keylen = keys.enckeylen;
2155 memcpy(ctx->base.key, keys.enckey, keys.enckeylen);
2156
2157 memzero_explicit(&keys, sizeof(keys));
2158 return 0;
2159
2160 badkey:
2161 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
2162 memzero_explicit(&keys, sizeof(keys));
2163 return -EINVAL;
2164 }
2165
atmel_aes_authenc_init_tfm(struct crypto_aead * tfm,unsigned long auth_mode)2166 static int atmel_aes_authenc_init_tfm(struct crypto_aead *tfm,
2167 unsigned long auth_mode)
2168 {
2169 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2170 unsigned int auth_reqsize = atmel_sha_authenc_get_reqsize();
2171
2172 ctx->auth = atmel_sha_authenc_spawn(auth_mode);
2173 if (IS_ERR(ctx->auth))
2174 return PTR_ERR(ctx->auth);
2175
2176 crypto_aead_set_reqsize(tfm, (sizeof(struct atmel_aes_authenc_reqctx) +
2177 auth_reqsize));
2178 ctx->base.start = atmel_aes_authenc_start;
2179
2180 return 0;
2181 }
2182
atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead * tfm)2183 static int atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead *tfm)
2184 {
2185 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA1);
2186 }
2187
atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead * tfm)2188 static int atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead *tfm)
2189 {
2190 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA224);
2191 }
2192
atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead * tfm)2193 static int atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead *tfm)
2194 {
2195 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA256);
2196 }
2197
atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead * tfm)2198 static int atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead *tfm)
2199 {
2200 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA384);
2201 }
2202
atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead * tfm)2203 static int atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead *tfm)
2204 {
2205 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA512);
2206 }
2207
atmel_aes_authenc_exit_tfm(struct crypto_aead * tfm)2208 static void atmel_aes_authenc_exit_tfm(struct crypto_aead *tfm)
2209 {
2210 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2211
2212 atmel_sha_authenc_free(ctx->auth);
2213 }
2214
atmel_aes_authenc_crypt(struct aead_request * req,unsigned long mode)2215 static int atmel_aes_authenc_crypt(struct aead_request *req,
2216 unsigned long mode)
2217 {
2218 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2219 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2220 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
2221 u32 authsize = crypto_aead_authsize(tfm);
2222 bool enc = (mode & AES_FLAGS_ENCRYPT);
2223 struct atmel_aes_dev *dd;
2224
2225 /* Compute text length. */
2226 if (!enc && req->cryptlen < authsize)
2227 return -EINVAL;
2228 rctx->textlen = req->cryptlen - (enc ? 0 : authsize);
2229
2230 /*
2231 * Currently, empty messages are not supported yet:
2232 * the SHA auto-padding can be used only on non-empty messages.
2233 * Hence a special case needs to be implemented for empty message.
2234 */
2235 if (!rctx->textlen && !req->assoclen)
2236 return -EINVAL;
2237
2238 rctx->base.mode = mode;
2239 ctx->block_size = AES_BLOCK_SIZE;
2240 ctx->is_aead = true;
2241
2242 dd = atmel_aes_find_dev(ctx);
2243 if (!dd)
2244 return -ENODEV;
2245
2246 return atmel_aes_handle_queue(dd, &req->base);
2247 }
2248
atmel_aes_authenc_cbc_aes_encrypt(struct aead_request * req)2249 static int atmel_aes_authenc_cbc_aes_encrypt(struct aead_request *req)
2250 {
2251 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
2252 }
2253
atmel_aes_authenc_cbc_aes_decrypt(struct aead_request * req)2254 static int atmel_aes_authenc_cbc_aes_decrypt(struct aead_request *req)
2255 {
2256 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC);
2257 }
2258
2259 static struct aead_alg aes_authenc_algs[] = {
2260 {
2261 .setkey = atmel_aes_authenc_setkey,
2262 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2263 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2264 .init = atmel_aes_authenc_hmac_sha1_init_tfm,
2265 .exit = atmel_aes_authenc_exit_tfm,
2266 .ivsize = AES_BLOCK_SIZE,
2267 .maxauthsize = SHA1_DIGEST_SIZE,
2268
2269 .base = {
2270 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2271 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes",
2272 .cra_priority = ATMEL_AES_PRIORITY,
2273 .cra_flags = CRYPTO_ALG_ASYNC,
2274 .cra_blocksize = AES_BLOCK_SIZE,
2275 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2276 .cra_alignmask = 0xf,
2277 .cra_module = THIS_MODULE,
2278 },
2279 },
2280 {
2281 .setkey = atmel_aes_authenc_setkey,
2282 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2283 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2284 .init = atmel_aes_authenc_hmac_sha224_init_tfm,
2285 .exit = atmel_aes_authenc_exit_tfm,
2286 .ivsize = AES_BLOCK_SIZE,
2287 .maxauthsize = SHA224_DIGEST_SIZE,
2288
2289 .base = {
2290 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2291 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes",
2292 .cra_priority = ATMEL_AES_PRIORITY,
2293 .cra_flags = CRYPTO_ALG_ASYNC,
2294 .cra_blocksize = AES_BLOCK_SIZE,
2295 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2296 .cra_alignmask = 0xf,
2297 .cra_module = THIS_MODULE,
2298 },
2299 },
2300 {
2301 .setkey = atmel_aes_authenc_setkey,
2302 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2303 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2304 .init = atmel_aes_authenc_hmac_sha256_init_tfm,
2305 .exit = atmel_aes_authenc_exit_tfm,
2306 .ivsize = AES_BLOCK_SIZE,
2307 .maxauthsize = SHA256_DIGEST_SIZE,
2308
2309 .base = {
2310 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2311 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes",
2312 .cra_priority = ATMEL_AES_PRIORITY,
2313 .cra_flags = CRYPTO_ALG_ASYNC,
2314 .cra_blocksize = AES_BLOCK_SIZE,
2315 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2316 .cra_alignmask = 0xf,
2317 .cra_module = THIS_MODULE,
2318 },
2319 },
2320 {
2321 .setkey = atmel_aes_authenc_setkey,
2322 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2323 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2324 .init = atmel_aes_authenc_hmac_sha384_init_tfm,
2325 .exit = atmel_aes_authenc_exit_tfm,
2326 .ivsize = AES_BLOCK_SIZE,
2327 .maxauthsize = SHA384_DIGEST_SIZE,
2328
2329 .base = {
2330 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2331 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes",
2332 .cra_priority = ATMEL_AES_PRIORITY,
2333 .cra_flags = CRYPTO_ALG_ASYNC,
2334 .cra_blocksize = AES_BLOCK_SIZE,
2335 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2336 .cra_alignmask = 0xf,
2337 .cra_module = THIS_MODULE,
2338 },
2339 },
2340 {
2341 .setkey = atmel_aes_authenc_setkey,
2342 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2343 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2344 .init = atmel_aes_authenc_hmac_sha512_init_tfm,
2345 .exit = atmel_aes_authenc_exit_tfm,
2346 .ivsize = AES_BLOCK_SIZE,
2347 .maxauthsize = SHA512_DIGEST_SIZE,
2348
2349 .base = {
2350 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2351 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes",
2352 .cra_priority = ATMEL_AES_PRIORITY,
2353 .cra_flags = CRYPTO_ALG_ASYNC,
2354 .cra_blocksize = AES_BLOCK_SIZE,
2355 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2356 .cra_alignmask = 0xf,
2357 .cra_module = THIS_MODULE,
2358 },
2359 },
2360 };
2361 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2362
2363 /* Probe functions */
2364
atmel_aes_buff_init(struct atmel_aes_dev * dd)2365 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
2366 {
2367 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
2368 dd->buflen = ATMEL_AES_BUFFER_SIZE;
2369 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
2370
2371 if (!dd->buf) {
2372 dev_err(dd->dev, "unable to alloc pages.\n");
2373 return -ENOMEM;
2374 }
2375
2376 return 0;
2377 }
2378
atmel_aes_buff_cleanup(struct atmel_aes_dev * dd)2379 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
2380 {
2381 free_page((unsigned long)dd->buf);
2382 }
2383
atmel_aes_filter(struct dma_chan * chan,void * slave)2384 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
2385 {
2386 struct at_dma_slave *sl = slave;
2387
2388 if (sl && sl->dma_dev == chan->device->dev) {
2389 chan->private = sl;
2390 return true;
2391 } else {
2392 return false;
2393 }
2394 }
2395
atmel_aes_dma_init(struct atmel_aes_dev * dd,struct crypto_platform_data * pdata)2396 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
2397 struct crypto_platform_data *pdata)
2398 {
2399 struct at_dma_slave *slave;
2400 dma_cap_mask_t mask;
2401
2402 dma_cap_zero(mask);
2403 dma_cap_set(DMA_SLAVE, mask);
2404
2405 /* Try to grab 2 DMA channels */
2406 slave = &pdata->dma_slave->rxdata;
2407 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2408 slave, dd->dev, "tx");
2409 if (!dd->src.chan)
2410 goto err_dma_in;
2411
2412 slave = &pdata->dma_slave->txdata;
2413 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2414 slave, dd->dev, "rx");
2415 if (!dd->dst.chan)
2416 goto err_dma_out;
2417
2418 return 0;
2419
2420 err_dma_out:
2421 dma_release_channel(dd->src.chan);
2422 err_dma_in:
2423 dev_warn(dd->dev, "no DMA channel available\n");
2424 return -ENODEV;
2425 }
2426
atmel_aes_dma_cleanup(struct atmel_aes_dev * dd)2427 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
2428 {
2429 dma_release_channel(dd->dst.chan);
2430 dma_release_channel(dd->src.chan);
2431 }
2432
atmel_aes_queue_task(unsigned long data)2433 static void atmel_aes_queue_task(unsigned long data)
2434 {
2435 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2436
2437 atmel_aes_handle_queue(dd, NULL);
2438 }
2439
atmel_aes_done_task(unsigned long data)2440 static void atmel_aes_done_task(unsigned long data)
2441 {
2442 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2443
2444 dd->is_async = true;
2445 (void)dd->resume(dd);
2446 }
2447
atmel_aes_irq(int irq,void * dev_id)2448 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
2449 {
2450 struct atmel_aes_dev *aes_dd = dev_id;
2451 u32 reg;
2452
2453 reg = atmel_aes_read(aes_dd, AES_ISR);
2454 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
2455 atmel_aes_write(aes_dd, AES_IDR, reg);
2456 if (AES_FLAGS_BUSY & aes_dd->flags)
2457 tasklet_schedule(&aes_dd->done_task);
2458 else
2459 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
2460 return IRQ_HANDLED;
2461 }
2462
2463 return IRQ_NONE;
2464 }
2465
atmel_aes_unregister_algs(struct atmel_aes_dev * dd)2466 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
2467 {
2468 int i;
2469
2470 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2471 if (dd->caps.has_authenc)
2472 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++)
2473 crypto_unregister_aead(&aes_authenc_algs[i]);
2474 #endif
2475
2476 if (dd->caps.has_xts)
2477 crypto_unregister_alg(&aes_xts_alg);
2478
2479 if (dd->caps.has_gcm)
2480 crypto_unregister_aead(&aes_gcm_alg);
2481
2482 if (dd->caps.has_cfb64)
2483 crypto_unregister_alg(&aes_cfb64_alg);
2484
2485 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
2486 crypto_unregister_alg(&aes_algs[i]);
2487 }
2488
atmel_aes_register_algs(struct atmel_aes_dev * dd)2489 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
2490 {
2491 int err, i, j;
2492
2493 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
2494 err = crypto_register_alg(&aes_algs[i]);
2495 if (err)
2496 goto err_aes_algs;
2497 }
2498
2499 if (dd->caps.has_cfb64) {
2500 err = crypto_register_alg(&aes_cfb64_alg);
2501 if (err)
2502 goto err_aes_cfb64_alg;
2503 }
2504
2505 if (dd->caps.has_gcm) {
2506 err = crypto_register_aead(&aes_gcm_alg);
2507 if (err)
2508 goto err_aes_gcm_alg;
2509 }
2510
2511 if (dd->caps.has_xts) {
2512 err = crypto_register_alg(&aes_xts_alg);
2513 if (err)
2514 goto err_aes_xts_alg;
2515 }
2516
2517 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2518 if (dd->caps.has_authenc) {
2519 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) {
2520 err = crypto_register_aead(&aes_authenc_algs[i]);
2521 if (err)
2522 goto err_aes_authenc_alg;
2523 }
2524 }
2525 #endif
2526
2527 return 0;
2528
2529 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2530 /* i = ARRAY_SIZE(aes_authenc_algs); */
2531 err_aes_authenc_alg:
2532 for (j = 0; j < i; j++)
2533 crypto_unregister_aead(&aes_authenc_algs[j]);
2534 crypto_unregister_alg(&aes_xts_alg);
2535 #endif
2536 err_aes_xts_alg:
2537 crypto_unregister_aead(&aes_gcm_alg);
2538 err_aes_gcm_alg:
2539 crypto_unregister_alg(&aes_cfb64_alg);
2540 err_aes_cfb64_alg:
2541 i = ARRAY_SIZE(aes_algs);
2542 err_aes_algs:
2543 for (j = 0; j < i; j++)
2544 crypto_unregister_alg(&aes_algs[j]);
2545
2546 return err;
2547 }
2548
atmel_aes_get_cap(struct atmel_aes_dev * dd)2549 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
2550 {
2551 dd->caps.has_dualbuff = 0;
2552 dd->caps.has_cfb64 = 0;
2553 dd->caps.has_ctr32 = 0;
2554 dd->caps.has_gcm = 0;
2555 dd->caps.has_xts = 0;
2556 dd->caps.has_authenc = 0;
2557 dd->caps.max_burst_size = 1;
2558
2559 /* keep only major version number */
2560 switch (dd->hw_version & 0xff0) {
2561 case 0x500:
2562 dd->caps.has_dualbuff = 1;
2563 dd->caps.has_cfb64 = 1;
2564 dd->caps.has_ctr32 = 1;
2565 dd->caps.has_gcm = 1;
2566 dd->caps.has_xts = 1;
2567 dd->caps.has_authenc = 1;
2568 dd->caps.max_burst_size = 4;
2569 break;
2570 case 0x200:
2571 dd->caps.has_dualbuff = 1;
2572 dd->caps.has_cfb64 = 1;
2573 dd->caps.has_ctr32 = 1;
2574 dd->caps.has_gcm = 1;
2575 dd->caps.max_burst_size = 4;
2576 break;
2577 case 0x130:
2578 dd->caps.has_dualbuff = 1;
2579 dd->caps.has_cfb64 = 1;
2580 dd->caps.max_burst_size = 4;
2581 break;
2582 case 0x120:
2583 break;
2584 default:
2585 dev_warn(dd->dev,
2586 "Unmanaged aes version, set minimum capabilities\n");
2587 break;
2588 }
2589 }
2590
2591 #if defined(CONFIG_OF)
2592 static const struct of_device_id atmel_aes_dt_ids[] = {
2593 { .compatible = "atmel,at91sam9g46-aes" },
2594 { /* sentinel */ }
2595 };
2596 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
2597
atmel_aes_of_init(struct platform_device * pdev)2598 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2599 {
2600 struct device_node *np = pdev->dev.of_node;
2601 struct crypto_platform_data *pdata;
2602
2603 if (!np) {
2604 dev_err(&pdev->dev, "device node not found\n");
2605 return ERR_PTR(-EINVAL);
2606 }
2607
2608 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2609 if (!pdata)
2610 return ERR_PTR(-ENOMEM);
2611
2612 pdata->dma_slave = devm_kzalloc(&pdev->dev,
2613 sizeof(*(pdata->dma_slave)),
2614 GFP_KERNEL);
2615 if (!pdata->dma_slave) {
2616 devm_kfree(&pdev->dev, pdata);
2617 return ERR_PTR(-ENOMEM);
2618 }
2619
2620 return pdata;
2621 }
2622 #else
atmel_aes_of_init(struct platform_device * pdev)2623 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2624 {
2625 return ERR_PTR(-EINVAL);
2626 }
2627 #endif
2628
atmel_aes_probe(struct platform_device * pdev)2629 static int atmel_aes_probe(struct platform_device *pdev)
2630 {
2631 struct atmel_aes_dev *aes_dd;
2632 struct crypto_platform_data *pdata;
2633 struct device *dev = &pdev->dev;
2634 struct resource *aes_res;
2635 int err;
2636
2637 pdata = pdev->dev.platform_data;
2638 if (!pdata) {
2639 pdata = atmel_aes_of_init(pdev);
2640 if (IS_ERR(pdata)) {
2641 err = PTR_ERR(pdata);
2642 goto aes_dd_err;
2643 }
2644 }
2645
2646 if (!pdata->dma_slave) {
2647 err = -ENXIO;
2648 goto aes_dd_err;
2649 }
2650
2651 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2652 if (aes_dd == NULL) {
2653 err = -ENOMEM;
2654 goto aes_dd_err;
2655 }
2656
2657 aes_dd->dev = dev;
2658
2659 platform_set_drvdata(pdev, aes_dd);
2660
2661 INIT_LIST_HEAD(&aes_dd->list);
2662 spin_lock_init(&aes_dd->lock);
2663
2664 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2665 (unsigned long)aes_dd);
2666 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2667 (unsigned long)aes_dd);
2668
2669 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2670
2671 /* Get the base address */
2672 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673 if (!aes_res) {
2674 dev_err(dev, "no MEM resource info\n");
2675 err = -ENODEV;
2676 goto res_err;
2677 }
2678 aes_dd->phys_base = aes_res->start;
2679
2680 /* Get the IRQ */
2681 aes_dd->irq = platform_get_irq(pdev, 0);
2682 if (aes_dd->irq < 0) {
2683 err = aes_dd->irq;
2684 goto res_err;
2685 }
2686
2687 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2688 IRQF_SHARED, "atmel-aes", aes_dd);
2689 if (err) {
2690 dev_err(dev, "unable to request aes irq.\n");
2691 goto res_err;
2692 }
2693
2694 /* Initializing the clock */
2695 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2696 if (IS_ERR(aes_dd->iclk)) {
2697 dev_err(dev, "clock initialization failed.\n");
2698 err = PTR_ERR(aes_dd->iclk);
2699 goto res_err;
2700 }
2701
2702 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2703 if (IS_ERR(aes_dd->io_base)) {
2704 dev_err(dev, "can't ioremap\n");
2705 err = PTR_ERR(aes_dd->io_base);
2706 goto res_err;
2707 }
2708
2709 err = clk_prepare(aes_dd->iclk);
2710 if (err)
2711 goto res_err;
2712
2713 err = atmel_aes_hw_version_init(aes_dd);
2714 if (err)
2715 goto iclk_unprepare;
2716
2717 atmel_aes_get_cap(aes_dd);
2718
2719 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2720 if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) {
2721 err = -EPROBE_DEFER;
2722 goto iclk_unprepare;
2723 }
2724 #endif
2725
2726 err = atmel_aes_buff_init(aes_dd);
2727 if (err)
2728 goto err_aes_buff;
2729
2730 err = atmel_aes_dma_init(aes_dd, pdata);
2731 if (err)
2732 goto err_aes_dma;
2733
2734 spin_lock(&atmel_aes.lock);
2735 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2736 spin_unlock(&atmel_aes.lock);
2737
2738 err = atmel_aes_register_algs(aes_dd);
2739 if (err)
2740 goto err_algs;
2741
2742 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2743 dma_chan_name(aes_dd->src.chan),
2744 dma_chan_name(aes_dd->dst.chan));
2745
2746 return 0;
2747
2748 err_algs:
2749 spin_lock(&atmel_aes.lock);
2750 list_del(&aes_dd->list);
2751 spin_unlock(&atmel_aes.lock);
2752 atmel_aes_dma_cleanup(aes_dd);
2753 err_aes_dma:
2754 atmel_aes_buff_cleanup(aes_dd);
2755 err_aes_buff:
2756 iclk_unprepare:
2757 clk_unprepare(aes_dd->iclk);
2758 res_err:
2759 tasklet_kill(&aes_dd->done_task);
2760 tasklet_kill(&aes_dd->queue_task);
2761 aes_dd_err:
2762 if (err != -EPROBE_DEFER)
2763 dev_err(dev, "initialization failed.\n");
2764
2765 return err;
2766 }
2767
atmel_aes_remove(struct platform_device * pdev)2768 static int atmel_aes_remove(struct platform_device *pdev)
2769 {
2770 struct atmel_aes_dev *aes_dd;
2771
2772 aes_dd = platform_get_drvdata(pdev);
2773 if (!aes_dd)
2774 return -ENODEV;
2775 spin_lock(&atmel_aes.lock);
2776 list_del(&aes_dd->list);
2777 spin_unlock(&atmel_aes.lock);
2778
2779 atmel_aes_unregister_algs(aes_dd);
2780
2781 tasklet_kill(&aes_dd->done_task);
2782 tasklet_kill(&aes_dd->queue_task);
2783
2784 atmel_aes_dma_cleanup(aes_dd);
2785 atmel_aes_buff_cleanup(aes_dd);
2786
2787 clk_unprepare(aes_dd->iclk);
2788
2789 return 0;
2790 }
2791
2792 static struct platform_driver atmel_aes_driver = {
2793 .probe = atmel_aes_probe,
2794 .remove = atmel_aes_remove,
2795 .driver = {
2796 .name = "atmel_aes",
2797 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2798 },
2799 };
2800
2801 module_platform_driver(atmel_aes_driver);
2802
2803 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2804 MODULE_LICENSE("GPL v2");
2805 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
2806