1 #ifndef __KIRIN_DRM_DSI_H__ 2 #define __KIRIN_DRM_DSI_H__ 3 4 5 #include <linux/clk.h> 6 #include <linux/component.h> 7 #include <linux/of_graph.h> 8 #include <linux/iopoll.h> 9 #include <video/mipi_display.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/of_address.h> 12 #include <linux/of_platform.h> 13 14 #include <drm/drm_of.h> 15 #include <drm/drm_crtc_helper.h> 16 #include <drm/drm_mipi_dsi.h> 17 #include <drm/drm_encoder_slave.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_panel.h> 20 21 #define ROUND(x, y) ((x) / (y) + \ 22 ((x) % (y) * 10 / (y) >= 5 ? 1 : 0)) 23 #define PHY_REF_CLK_RATE 19200000 24 #define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000)) 25 26 #define encoder_to_dsi(encoder) \ 27 container_of(encoder, struct dw_dsi, encoder) 28 #define host_to_dsi(host) \ 29 container_of(host, struct dw_dsi, host) 30 #define connector_to_dsi(connector) \ 31 container_of(connector, struct dw_dsi, connector) 32 33 enum dsi_output_client { 34 OUT_HDMI = 0, 35 OUT_PANEL, 36 OUT_MAX 37 }; 38 39 struct dsi_phy_range { 40 u32 min_range_kHz; 41 u32 max_range_kHz; 42 u32 pll_vco_750M; 43 u32 hstx_ckg_sel; 44 }; 45 46 static const struct dsi_phy_range dphy_range_info[] = { 47 { 46875, 62500, 1, 7 }, 48 { 62500, 93750, 0, 7 }, 49 { 93750, 125000, 1, 6 }, 50 { 125000, 187500, 0, 6 }, 51 { 187500, 250000, 1, 5 }, 52 { 250000, 375000, 0, 5 }, 53 { 375000, 500000, 1, 4 }, 54 { 500000, 750000, 0, 4 }, 55 { 750000, 1000000, 1, 0 }, 56 { 1000000, 1500000, 0, 0 } 57 }; 58 59 struct dsi_hw_ctx { 60 void __iomem *base; 61 char __iomem *peri_crg_base; 62 63 struct clk *pclk; 64 struct clk *dss_dphy0_ref_clk; 65 struct clk *dss_dphy1_ref_clk; 66 struct clk *dss_dphy0_cfg_clk; 67 struct clk *dss_dphy1_cfg_clk; 68 struct clk *dss_pclk_dsi0_clk; 69 struct clk *dss_pclk_dsi1_clk; 70 }; 71 72 struct mipi_panel_info { 73 u8 dsi_version; 74 u8 vc; 75 u8 lane_nums; 76 u8 lane_nums_select_support; 77 u8 color_mode; 78 u32 dsi_bit_clk; /* clock lane(p/n) */ 79 u32 burst_mode; 80 u32 max_tx_esc_clk; 81 u8 non_continue_en; 82 83 u32 dsi_bit_clk_val1; 84 u32 dsi_bit_clk_val2; 85 u32 dsi_bit_clk_val3; 86 u32 dsi_bit_clk_val4; 87 u32 dsi_bit_clk_val5; 88 u32 dsi_bit_clk_upt; 89 /*uint32_t dsi_pclk_rate;*/ 90 91 u32 hs_wr_to_time; 92 93 /* dphy config parameter adjust*/ 94 u32 clk_post_adjust; 95 u32 clk_pre_adjust; 96 u32 clk_pre_delay_adjust; 97 u32 clk_t_hs_exit_adjust; 98 u32 clk_t_hs_trial_adjust; 99 u32 clk_t_hs_prepare_adjust; 100 int clk_t_lpx_adjust; 101 u32 clk_t_hs_zero_adjust; 102 u32 data_post_delay_adjust; 103 int data_t_lpx_adjust; 104 u32 data_t_hs_prepare_adjust; 105 u32 data_t_hs_zero_adjust; 106 u32 data_t_hs_trial_adjust; 107 u32 rg_vrefsel_vcm_adjust; 108 109 /*only for Chicago<3660> use*/ 110 u32 rg_vrefsel_vcm_clk_adjust; 111 u32 rg_vrefsel_vcm_data_adjust; 112 }; 113 114 struct mipi_phy_params { 115 u32 clk_t_lpx; 116 u32 clk_t_hs_prepare; 117 u32 clk_t_hs_zero; 118 u32 clk_t_hs_trial; 119 u32 clk_t_wakeup; 120 u32 data_t_lpx; 121 u32 data_t_hs_prepare; 122 u32 data_t_hs_zero; 123 u32 data_t_hs_trial; 124 u32 data_t_ta_go; 125 u32 data_t_ta_get; 126 u32 data_t_wakeup; 127 u32 hstx_ckg_sel; 128 u32 pll_fbd_div5f; 129 u32 pll_fbd_div1f; 130 u32 pll_fbd_2p; 131 u32 pll_enbwt; 132 u32 pll_fbd_p; 133 u32 pll_fbd_s; 134 u32 pll_pre_div1p; 135 u32 pll_pre_p; 136 u32 pll_vco_750M; 137 u32 pll_lpf_rs; 138 u32 pll_lpf_cs; 139 u32 clk_division; 140 /********for hikey620************/ 141 u32 clklp2hs_time; 142 u32 clkhs2lp_time; 143 u32 lp2hs_time; 144 u32 hs2lp_time; 145 u32 clk_to_data_delay; 146 u32 data_to_clk_delay; 147 u32 lane_byte_clk_kHz; 148 /*****************/ 149 150 /****for hikey960*****/ 151 u64 lane_byte_clk; 152 153 u32 clk_lane_lp2hs_time; 154 u32 clk_lane_hs2lp_time; 155 u32 data_lane_lp2hs_time; 156 u32 data_lane_hs2lp_time; 157 u32 clk2data_delay; 158 u32 data2clk_delay; 159 160 u32 clk_pre_delay; 161 u32 clk_post_delay; 162 u32 data_pre_delay; 163 u32 data_post_delay; 164 u32 phy_stop_wait_time; 165 u32 rg_vrefsel_vcm; 166 167 u32 rg_pll_enswc; 168 u32 rg_pll_chp; 169 170 u32 pll_register_override; /*0x1E[0]*/ 171 u32 pll_power_down; /*0x1E[1]*/ 172 u32 rg_band_sel; /*0x1E[2]*/ 173 u32 rg_phase_gen_en; /*0x1E[3]*/ 174 u32 reload_sel; /*0x1E[4]*/ 175 u32 rg_pll_cp_p; /*0x1E[7:5]*/ 176 u32 rg_pll_refsel; /*0x16[1:0]*/ 177 u32 rg_pll_cp; /*0x16[7:5]*/ 178 u32 load_command; 179 /*********/ 180 }; 181 182 struct ldi_panel_info { 183 u32 h_back_porch; 184 u32 h_front_porch; 185 u32 h_pulse_width; 186 187 /* 188 ** note: vbp > 8 if used overlay compose, 189 ** also lcd vbp > 8 in lcd power on sequence 190 */ 191 u32 v_back_porch; 192 u32 v_front_porch; 193 u32 v_pulse_width; 194 195 u8 hsync_plr; 196 u8 vsync_plr; 197 u8 pixelclk_plr; 198 u8 data_en_plr; 199 200 /* for cabc */ 201 u8 dpi0_overlap_size; 202 u8 dpi1_overlap_size; 203 }; 204 205 struct dw_dsi_client { 206 u32 lanes; 207 u32 phy_clock; /* in kHz */ 208 enum mipi_dsi_pixel_format format; 209 unsigned long mode_flags; 210 }; 211 212 struct dw_dsi { 213 struct drm_encoder encoder; 214 struct drm_bridge *bridge; 215 struct drm_panel *panel; 216 struct mipi_dsi_host host; 217 struct drm_connector connector; /* connector for panel */ 218 struct drm_display_mode cur_mode; 219 struct dsi_hw_ctx *ctx; 220 struct mipi_phy_params phy; 221 struct mipi_panel_info mipi; 222 struct ldi_panel_info ldi; 223 u32 lanes; 224 enum mipi_dsi_pixel_format format; 225 unsigned long mode_flags; 226 struct gpio_desc *gpio_mux; 227 struct dw_dsi_client client[OUT_MAX]; 228 enum dsi_output_client cur_client; 229 bool enable; 230 }; 231 232 struct dsi_data { 233 struct dw_dsi dsi; 234 struct dsi_hw_ctx ctx; 235 }; 236 237 enum kirin_dsi_version { 238 KIRIN620_DSI = 0, 239 KIRIN960_DSI 240 }; 241 242 /* display controller init/cleanup ops */ 243 struct kirin_dsi_ops { 244 enum kirin_dsi_version version; 245 int (*parse_dt)(struct platform_device *pdev, struct dw_dsi *dsi); 246 int (*host_init)(struct device *dev, struct dw_dsi *dsi); 247 void (*encoder_enable)(struct drm_encoder *encoder); 248 enum drm_mode_status(*encoder_valid)(struct drm_encoder *encoder, 249 const struct drm_display_mode *mode); 250 }; 251 252 #ifdef CONFIG_DRM_HISI_KIRIN960 253 extern const struct kirin_dsi_ops kirin_dsi_960; 254 #endif 255 #ifdef CONFIG_DRM_HISI_KIRIN620 256 extern const struct kirin_dsi_ops kirin_dsi_620; 257 #endif 258 259 #endif /* __KIRIN_DRM_DSI_H__ */ 260