1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Ingenic JZ47xx KMS driver
4 //
5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
6
7 #include <linux/clk.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_fb_helper.h>
22 #include <drm/drm_fourcc.h>
23 #include <drm/drm_gem_framebuffer_helper.h>
24 #include <drm/drm_irq.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_plane.h>
28 #include <drm/drm_plane_helper.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/drm_vblank.h>
31
32 #define JZ_REG_LCD_CFG 0x00
33 #define JZ_REG_LCD_VSYNC 0x04
34 #define JZ_REG_LCD_HSYNC 0x08
35 #define JZ_REG_LCD_VAT 0x0C
36 #define JZ_REG_LCD_DAH 0x10
37 #define JZ_REG_LCD_DAV 0x14
38 #define JZ_REG_LCD_PS 0x18
39 #define JZ_REG_LCD_CLS 0x1C
40 #define JZ_REG_LCD_SPL 0x20
41 #define JZ_REG_LCD_REV 0x24
42 #define JZ_REG_LCD_CTRL 0x30
43 #define JZ_REG_LCD_STATE 0x34
44 #define JZ_REG_LCD_IID 0x38
45 #define JZ_REG_LCD_DA0 0x40
46 #define JZ_REG_LCD_SA0 0x44
47 #define JZ_REG_LCD_FID0 0x48
48 #define JZ_REG_LCD_CMD0 0x4C
49 #define JZ_REG_LCD_DA1 0x50
50 #define JZ_REG_LCD_SA1 0x54
51 #define JZ_REG_LCD_FID1 0x58
52 #define JZ_REG_LCD_CMD1 0x5C
53
54 #define JZ_LCD_CFG_SLCD BIT(31)
55 #define JZ_LCD_CFG_PS_DISABLE BIT(23)
56 #define JZ_LCD_CFG_CLS_DISABLE BIT(22)
57 #define JZ_LCD_CFG_SPL_DISABLE BIT(21)
58 #define JZ_LCD_CFG_REV_DISABLE BIT(20)
59 #define JZ_LCD_CFG_HSYNCM BIT(19)
60 #define JZ_LCD_CFG_PCLKM BIT(18)
61 #define JZ_LCD_CFG_INV BIT(17)
62 #define JZ_LCD_CFG_SYNC_DIR BIT(16)
63 #define JZ_LCD_CFG_PS_POLARITY BIT(15)
64 #define JZ_LCD_CFG_CLS_POLARITY BIT(14)
65 #define JZ_LCD_CFG_SPL_POLARITY BIT(13)
66 #define JZ_LCD_CFG_REV_POLARITY BIT(12)
67 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
68 #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
69 #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
70 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
71 #define JZ_LCD_CFG_18_BIT BIT(7)
72 #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
73
74 #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
75 #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
76 #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
77
78 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
79 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
80 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
81
82 #define JZ_LCD_CFG_MODE_TV_OUT_P 4
83 #define JZ_LCD_CFG_MODE_TV_OUT_I 6
84
85 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
86 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
87 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
88 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
89
90 #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
91 #define JZ_LCD_CFG_MODE_LCM 13
92
93 #define JZ_LCD_VSYNC_VPS_OFFSET 16
94 #define JZ_LCD_VSYNC_VPE_OFFSET 0
95
96 #define JZ_LCD_HSYNC_HPS_OFFSET 16
97 #define JZ_LCD_HSYNC_HPE_OFFSET 0
98
99 #define JZ_LCD_VAT_HT_OFFSET 16
100 #define JZ_LCD_VAT_VT_OFFSET 0
101
102 #define JZ_LCD_DAH_HDS_OFFSET 16
103 #define JZ_LCD_DAH_HDE_OFFSET 0
104
105 #define JZ_LCD_DAV_VDS_OFFSET 16
106 #define JZ_LCD_DAV_VDE_OFFSET 0
107
108 #define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
109 #define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
110 #define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
111 #define JZ_LCD_CTRL_RGB555 BIT(27)
112 #define JZ_LCD_CTRL_OFUP BIT(26)
113 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
114 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
115 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
116 #define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
117 #define JZ_LCD_CTRL_EOF_IRQ BIT(13)
118 #define JZ_LCD_CTRL_SOF_IRQ BIT(12)
119 #define JZ_LCD_CTRL_OFU_IRQ BIT(11)
120 #define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
121 #define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
122 #define JZ_LCD_CTRL_DD_IRQ BIT(8)
123 #define JZ_LCD_CTRL_QDD_IRQ BIT(7)
124 #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
125 #define JZ_LCD_CTRL_LSB_FISRT BIT(5)
126 #define JZ_LCD_CTRL_DISABLE BIT(4)
127 #define JZ_LCD_CTRL_ENABLE BIT(3)
128 #define JZ_LCD_CTRL_BPP_1 0x0
129 #define JZ_LCD_CTRL_BPP_2 0x1
130 #define JZ_LCD_CTRL_BPP_4 0x2
131 #define JZ_LCD_CTRL_BPP_8 0x3
132 #define JZ_LCD_CTRL_BPP_15_16 0x4
133 #define JZ_LCD_CTRL_BPP_18_24 0x5
134 #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | (0x7 << 0))
135
136 #define JZ_LCD_CMD_SOF_IRQ BIT(31)
137 #define JZ_LCD_CMD_EOF_IRQ BIT(30)
138 #define JZ_LCD_CMD_ENABLE_PAL BIT(28)
139
140 #define JZ_LCD_SYNC_MASK 0x3ff
141
142 #define JZ_LCD_STATE_EOF_IRQ BIT(5)
143 #define JZ_LCD_STATE_SOF_IRQ BIT(4)
144 #define JZ_LCD_STATE_DISABLED BIT(0)
145
146 struct ingenic_dma_hwdesc {
147 u32 next;
148 u32 addr;
149 u32 id;
150 u32 cmd;
151 } __packed;
152
153 struct jz_soc_info {
154 bool needs_dev_clk;
155 };
156
157 struct ingenic_drm {
158 struct drm_device drm;
159 struct drm_plane primary;
160 struct drm_crtc crtc;
161 struct drm_encoder encoder;
162
163 struct device *dev;
164 struct regmap *map;
165 struct clk *lcd_clk, *pix_clk;
166
167 struct ingenic_dma_hwdesc *dma_hwdesc;
168 dma_addr_t dma_hwdesc_phys;
169
170 bool panel_is_sharp;
171 };
172
173 static const u32 ingenic_drm_primary_formats[] = {
174 DRM_FORMAT_XRGB1555,
175 DRM_FORMAT_RGB565,
176 DRM_FORMAT_XRGB8888,
177 };
178
ingenic_drm_writeable_reg(struct device * dev,unsigned int reg)179 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
180 {
181 switch (reg) {
182 case JZ_REG_LCD_IID:
183 case JZ_REG_LCD_SA0:
184 case JZ_REG_LCD_FID0:
185 case JZ_REG_LCD_CMD0:
186 case JZ_REG_LCD_SA1:
187 case JZ_REG_LCD_FID1:
188 case JZ_REG_LCD_CMD1:
189 return false;
190 default:
191 return true;
192 }
193 }
194
195 static const struct regmap_config ingenic_drm_regmap_config = {
196 .reg_bits = 32,
197 .val_bits = 32,
198 .reg_stride = 4,
199
200 .max_register = JZ_REG_LCD_CMD1,
201 .writeable_reg = ingenic_drm_writeable_reg,
202 };
203
drm_device_get_priv(struct drm_device * drm)204 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
205 {
206 return container_of(drm, struct ingenic_drm, drm);
207 }
208
drm_crtc_get_priv(struct drm_crtc * crtc)209 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
210 {
211 return container_of(crtc, struct ingenic_drm, crtc);
212 }
213
214 static inline struct ingenic_drm *
drm_encoder_get_priv(struct drm_encoder * encoder)215 drm_encoder_get_priv(struct drm_encoder *encoder)
216 {
217 return container_of(encoder, struct ingenic_drm, encoder);
218 }
219
drm_plane_get_priv(struct drm_plane * plane)220 static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane)
221 {
222 return container_of(plane, struct ingenic_drm, primary);
223 }
224
ingenic_drm_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * state)225 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
226 struct drm_crtc_state *state)
227 {
228 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
229
230 regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
231
232 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
233 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
234 JZ_LCD_CTRL_ENABLE);
235
236 drm_crtc_vblank_on(crtc);
237 }
238
ingenic_drm_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * state)239 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
240 struct drm_crtc_state *state)
241 {
242 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
243 unsigned int var;
244
245 drm_crtc_vblank_off(crtc);
246
247 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
248 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
249
250 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
251 var & JZ_LCD_STATE_DISABLED,
252 1000, 0);
253 }
254
ingenic_drm_crtc_update_timings(struct ingenic_drm * priv,struct drm_display_mode * mode)255 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
256 struct drm_display_mode *mode)
257 {
258 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
259
260 vpe = mode->vsync_end - mode->vsync_start;
261 vds = mode->vtotal - mode->vsync_start;
262 vde = vds + mode->vdisplay;
263 vt = vde + mode->vsync_start - mode->vdisplay;
264
265 hpe = mode->hsync_end - mode->hsync_start;
266 hds = mode->htotal - mode->hsync_start;
267 hde = hds + mode->hdisplay;
268 ht = hde + mode->hsync_start - mode->hdisplay;
269
270 regmap_write(priv->map, JZ_REG_LCD_VSYNC,
271 0 << JZ_LCD_VSYNC_VPS_OFFSET |
272 vpe << JZ_LCD_VSYNC_VPE_OFFSET);
273
274 regmap_write(priv->map, JZ_REG_LCD_HSYNC,
275 0 << JZ_LCD_HSYNC_HPS_OFFSET |
276 hpe << JZ_LCD_HSYNC_HPE_OFFSET);
277
278 regmap_write(priv->map, JZ_REG_LCD_VAT,
279 ht << JZ_LCD_VAT_HT_OFFSET |
280 vt << JZ_LCD_VAT_VT_OFFSET);
281
282 regmap_write(priv->map, JZ_REG_LCD_DAH,
283 hds << JZ_LCD_DAH_HDS_OFFSET |
284 hde << JZ_LCD_DAH_HDE_OFFSET);
285 regmap_write(priv->map, JZ_REG_LCD_DAV,
286 vds << JZ_LCD_DAV_VDS_OFFSET |
287 vde << JZ_LCD_DAV_VDE_OFFSET);
288
289 if (priv->panel_is_sharp) {
290 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
291 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
292 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
293 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
294 }
295 }
296
ingenic_drm_crtc_update_ctrl(struct ingenic_drm * priv,const struct drm_format_info * finfo)297 static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
298 const struct drm_format_info *finfo)
299 {
300 unsigned int ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
301
302 switch (finfo->format) {
303 case DRM_FORMAT_XRGB1555:
304 ctrl |= JZ_LCD_CTRL_RGB555;
305 /* fall-through */
306 case DRM_FORMAT_RGB565:
307 ctrl |= JZ_LCD_CTRL_BPP_15_16;
308 break;
309 case DRM_FORMAT_XRGB8888:
310 ctrl |= JZ_LCD_CTRL_BPP_18_24;
311 break;
312 }
313
314 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
315 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16 |
316 JZ_LCD_CTRL_BPP_MASK, ctrl);
317 }
318
ingenic_drm_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)319 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
320 struct drm_crtc_state *state)
321 {
322 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
323 long rate;
324
325 if (!drm_atomic_crtc_needs_modeset(state))
326 return 0;
327
328 rate = clk_round_rate(priv->pix_clk,
329 state->adjusted_mode.clock * 1000);
330 if (rate < 0)
331 return rate;
332
333 return 0;
334 }
335
ingenic_drm_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * oldstate)336 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
337 struct drm_crtc_state *oldstate)
338 {
339 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
340 struct drm_crtc_state *state = crtc->state;
341 struct drm_pending_vblank_event *event = state->event;
342 struct drm_framebuffer *drm_fb = crtc->primary->state->fb;
343 const struct drm_format_info *finfo;
344
345 if (drm_atomic_crtc_needs_modeset(state)) {
346 finfo = drm_format_info(drm_fb->format->format);
347
348 ingenic_drm_crtc_update_timings(priv, &state->mode);
349 ingenic_drm_crtc_update_ctrl(priv, finfo);
350
351 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
352
353 regmap_write(priv->map, JZ_REG_LCD_DA0, priv->dma_hwdesc->next);
354 }
355
356 if (event) {
357 state->event = NULL;
358
359 spin_lock_irq(&crtc->dev->event_lock);
360 if (drm_crtc_vblank_get(crtc) == 0)
361 drm_crtc_arm_vblank_event(crtc, event);
362 else
363 drm_crtc_send_vblank_event(crtc, event);
364 spin_unlock_irq(&crtc->dev->event_lock);
365 }
366 }
367
ingenic_drm_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * oldstate)368 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
369 struct drm_plane_state *oldstate)
370 {
371 struct ingenic_drm *priv = drm_plane_get_priv(plane);
372 struct drm_plane_state *state = plane->state;
373 unsigned int width, height, cpp;
374
375 width = state->crtc->state->adjusted_mode.hdisplay;
376 height = state->crtc->state->adjusted_mode.vdisplay;
377 cpp = state->fb->format->cpp[plane->index];
378
379 priv->dma_hwdesc->addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
380 priv->dma_hwdesc->cmd = width * height * cpp / 4;
381 priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
382 }
383
ingenic_drm_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)384 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
385 struct drm_crtc_state *crtc_state,
386 struct drm_connector_state *conn_state)
387 {
388 struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
389 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
390 struct drm_connector *conn = conn_state->connector;
391 struct drm_display_info *info = &conn->display_info;
392 unsigned int cfg;
393
394 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
395
396 if (priv->panel_is_sharp) {
397 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
398 } else {
399 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
400 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
401 }
402
403 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
404 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
405 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
406 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
407 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
408 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
409 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
410 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
411
412 if (!priv->panel_is_sharp) {
413 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
414 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
415 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
416 else
417 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
418 } else {
419 switch (*info->bus_formats) {
420 case MEDIA_BUS_FMT_RGB565_1X16:
421 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
422 break;
423 case MEDIA_BUS_FMT_RGB666_1X18:
424 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
425 break;
426 case MEDIA_BUS_FMT_RGB888_1X24:
427 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
428 break;
429 case MEDIA_BUS_FMT_RGB888_3X8:
430 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
431 break;
432 default:
433 break;
434 }
435 }
436 }
437
438 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
439 }
440
ingenic_drm_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)441 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
442 struct drm_crtc_state *crtc_state,
443 struct drm_connector_state *conn_state)
444 {
445 struct drm_display_info *info = &conn_state->connector->display_info;
446
447 if (info->num_bus_formats != 1)
448 return -EINVAL;
449
450 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
451 return 0;
452
453 switch (*info->bus_formats) {
454 case MEDIA_BUS_FMT_RGB565_1X16:
455 case MEDIA_BUS_FMT_RGB666_1X18:
456 case MEDIA_BUS_FMT_RGB888_1X24:
457 case MEDIA_BUS_FMT_RGB888_3X8:
458 return 0;
459 default:
460 return -EINVAL;
461 }
462 }
463
ingenic_drm_irq_handler(int irq,void * arg)464 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
465 {
466 struct ingenic_drm *priv = arg;
467 unsigned int state;
468
469 regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
470
471 regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
472 JZ_LCD_STATE_EOF_IRQ, 0);
473
474 if (state & JZ_LCD_STATE_EOF_IRQ)
475 drm_crtc_handle_vblank(&priv->crtc);
476
477 return IRQ_HANDLED;
478 }
479
ingenic_drm_release(struct drm_device * drm)480 static void ingenic_drm_release(struct drm_device *drm)
481 {
482 struct ingenic_drm *priv = drm_device_get_priv(drm);
483
484 drm_mode_config_cleanup(drm);
485 drm_dev_fini(drm);
486 kfree(priv);
487 }
488
ingenic_drm_enable_vblank(struct drm_crtc * crtc)489 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
490 {
491 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
492
493 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
494 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
495
496 return 0;
497 }
498
ingenic_drm_disable_vblank(struct drm_crtc * crtc)499 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
500 {
501 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
502
503 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
504 }
505
506 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
507
508 static struct drm_driver ingenic_drm_driver_data = {
509 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
510 .name = "ingenic-drm",
511 .desc = "DRM module for Ingenic SoCs",
512 .date = "20190422",
513 .major = 1,
514 .minor = 0,
515 .patchlevel = 0,
516
517 .fops = &ingenic_drm_fops,
518
519 .dumb_create = drm_gem_cma_dumb_create,
520 .gem_free_object_unlocked = drm_gem_cma_free_object,
521 .gem_vm_ops = &drm_gem_cma_vm_ops,
522
523 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
524 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
525 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
526 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
527 .gem_prime_vmap = drm_gem_cma_prime_vmap,
528 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
529 .gem_prime_mmap = drm_gem_cma_prime_mmap,
530
531 .irq_handler = ingenic_drm_irq_handler,
532 .release = ingenic_drm_release,
533 };
534
535 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
536 .update_plane = drm_atomic_helper_update_plane,
537 .disable_plane = drm_atomic_helper_disable_plane,
538 .reset = drm_atomic_helper_plane_reset,
539 .destroy = drm_plane_cleanup,
540
541 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
542 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
543 };
544
545 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
546 .set_config = drm_atomic_helper_set_config,
547 .page_flip = drm_atomic_helper_page_flip,
548 .reset = drm_atomic_helper_crtc_reset,
549 .destroy = drm_crtc_cleanup,
550
551 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
552 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
553
554 .enable_vblank = ingenic_drm_enable_vblank,
555 .disable_vblank = ingenic_drm_disable_vblank,
556
557 .gamma_set = drm_atomic_helper_legacy_gamma_set,
558 };
559
560 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
561 .atomic_update = ingenic_drm_plane_atomic_update,
562 .prepare_fb = drm_gem_fb_prepare_fb,
563 };
564
565 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
566 .atomic_enable = ingenic_drm_crtc_atomic_enable,
567 .atomic_disable = ingenic_drm_crtc_atomic_disable,
568 .atomic_flush = ingenic_drm_crtc_atomic_flush,
569 .atomic_check = ingenic_drm_crtc_atomic_check,
570 };
571
572 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
573 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set,
574 .atomic_check = ingenic_drm_encoder_atomic_check,
575 };
576
577 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
578 .fb_create = drm_gem_fb_create,
579 .output_poll_changed = drm_fb_helper_output_poll_changed,
580 .atomic_check = drm_atomic_helper_check,
581 .atomic_commit = drm_atomic_helper_commit,
582 };
583
584 static const struct drm_encoder_funcs ingenic_drm_encoder_funcs = {
585 .destroy = drm_encoder_cleanup,
586 };
587
ingenic_drm_free_dma_hwdesc(void * d)588 static void ingenic_drm_free_dma_hwdesc(void *d)
589 {
590 struct ingenic_drm *priv = d;
591
592 dma_free_coherent(priv->dev, sizeof(*priv->dma_hwdesc),
593 priv->dma_hwdesc, priv->dma_hwdesc_phys);
594 }
595
ingenic_drm_probe(struct platform_device * pdev)596 static int ingenic_drm_probe(struct platform_device *pdev)
597 {
598 const struct jz_soc_info *soc_info;
599 struct device *dev = &pdev->dev;
600 struct ingenic_drm *priv;
601 struct clk *parent_clk;
602 struct drm_bridge *bridge;
603 struct drm_panel *panel;
604 struct drm_device *drm;
605 void __iomem *base;
606 long parent_rate;
607 int ret, irq;
608
609 soc_info = of_device_get_match_data(dev);
610 if (!soc_info) {
611 dev_err(dev, "Missing platform data\n");
612 return -EINVAL;
613 }
614
615 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
616 if (!priv)
617 return -ENOMEM;
618
619 priv->dev = dev;
620 drm = &priv->drm;
621 drm->dev_private = priv;
622
623 platform_set_drvdata(pdev, priv);
624
625 ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data);
626 if (ret) {
627 kfree(priv);
628 return ret;
629 }
630
631 drm_mode_config_init(drm);
632 drm->mode_config.min_width = 0;
633 drm->mode_config.min_height = 0;
634 drm->mode_config.max_width = 800;
635 drm->mode_config.max_height = 600;
636 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
637
638 base = devm_platform_ioremap_resource(pdev, 0);
639 if (IS_ERR(base)) {
640 dev_err(dev, "Failed to get memory resource");
641 return PTR_ERR(base);
642 }
643
644 priv->map = devm_regmap_init_mmio(dev, base,
645 &ingenic_drm_regmap_config);
646 if (IS_ERR(priv->map)) {
647 dev_err(dev, "Failed to create regmap");
648 return PTR_ERR(priv->map);
649 }
650
651 irq = platform_get_irq(pdev, 0);
652 if (irq < 0) {
653 dev_err(dev, "Failed to get platform irq");
654 return irq;
655 }
656
657 if (soc_info->needs_dev_clk) {
658 priv->lcd_clk = devm_clk_get(dev, "lcd");
659 if (IS_ERR(priv->lcd_clk)) {
660 dev_err(dev, "Failed to get lcd clock");
661 return PTR_ERR(priv->lcd_clk);
662 }
663 }
664
665 priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
666 if (IS_ERR(priv->pix_clk)) {
667 dev_err(dev, "Failed to get pixel clock");
668 return PTR_ERR(priv->pix_clk);
669 }
670
671 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, &bridge);
672 if (ret) {
673 if (ret != -EPROBE_DEFER)
674 dev_err(dev, "Failed to get panel handle");
675 return ret;
676 }
677
678 if (panel)
679 bridge = devm_drm_panel_bridge_add(dev, panel,
680 DRM_MODE_CONNECTOR_DPI);
681
682 priv->dma_hwdesc = dma_alloc_coherent(dev, sizeof(*priv->dma_hwdesc),
683 &priv->dma_hwdesc_phys,
684 GFP_KERNEL);
685 if (!priv->dma_hwdesc)
686 return -ENOMEM;
687
688 ret = devm_add_action_or_reset(dev, ingenic_drm_free_dma_hwdesc, priv);
689 if (ret)
690 return ret;
691
692 priv->dma_hwdesc->next = priv->dma_hwdesc_phys;
693 priv->dma_hwdesc->id = 0xdeafbead;
694
695 drm_plane_helper_add(&priv->primary, &ingenic_drm_plane_helper_funcs);
696
697 ret = drm_universal_plane_init(drm, &priv->primary,
698 0, &ingenic_drm_primary_plane_funcs,
699 ingenic_drm_primary_formats,
700 ARRAY_SIZE(ingenic_drm_primary_formats),
701 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
702 if (ret) {
703 dev_err(dev, "Failed to register primary plane: %i", ret);
704 return ret;
705 }
706
707 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
708
709 ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary,
710 NULL, &ingenic_drm_crtc_funcs, NULL);
711 if (ret) {
712 dev_err(dev, "Failed to init CRTC: %i", ret);
713 return ret;
714 }
715
716 priv->encoder.possible_crtcs = 1;
717
718 drm_encoder_helper_add(&priv->encoder,
719 &ingenic_drm_encoder_helper_funcs);
720
721 ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs,
722 DRM_MODE_ENCODER_DPI, NULL);
723 if (ret) {
724 dev_err(dev, "Failed to init encoder: %i", ret);
725 return ret;
726 }
727
728 ret = drm_bridge_attach(&priv->encoder, bridge, NULL);
729 if (ret) {
730 dev_err(dev, "Unable to attach bridge");
731 return ret;
732 }
733
734 ret = drm_irq_install(drm, irq);
735 if (ret) {
736 dev_err(dev, "Unable to install IRQ handler");
737 return ret;
738 }
739
740 ret = drm_vblank_init(drm, 1);
741 if (ret) {
742 dev_err(dev, "Failed calling drm_vblank_init()");
743 return ret;
744 }
745
746 drm_mode_config_reset(drm);
747
748 ret = clk_prepare_enable(priv->pix_clk);
749 if (ret) {
750 dev_err(dev, "Unable to start pixel clock");
751 return ret;
752 }
753
754 if (priv->lcd_clk) {
755 parent_clk = clk_get_parent(priv->lcd_clk);
756 parent_rate = clk_get_rate(parent_clk);
757
758 /* LCD Device clock must be 3x the pixel clock for STN panels,
759 * or 1.5x the pixel clock for TFT panels. To avoid having to
760 * check for the LCD device clock everytime we do a mode change,
761 * we set the LCD device clock to the highest rate possible.
762 */
763 ret = clk_set_rate(priv->lcd_clk, parent_rate);
764 if (ret) {
765 dev_err(dev, "Unable to set LCD clock rate");
766 goto err_pixclk_disable;
767 }
768
769 ret = clk_prepare_enable(priv->lcd_clk);
770 if (ret) {
771 dev_err(dev, "Unable to start lcd clock");
772 goto err_pixclk_disable;
773 }
774 }
775
776 ret = drm_dev_register(drm, 0);
777 if (ret) {
778 dev_err(dev, "Failed to register DRM driver");
779 goto err_devclk_disable;
780 }
781
782 ret = drm_fbdev_generic_setup(drm, 32);
783 if (ret)
784 dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
785
786 return 0;
787
788 err_devclk_disable:
789 if (priv->lcd_clk)
790 clk_disable_unprepare(priv->lcd_clk);
791 err_pixclk_disable:
792 clk_disable_unprepare(priv->pix_clk);
793 return ret;
794 }
795
ingenic_drm_remove(struct platform_device * pdev)796 static int ingenic_drm_remove(struct platform_device *pdev)
797 {
798 struct ingenic_drm *priv = platform_get_drvdata(pdev);
799
800 if (priv->lcd_clk)
801 clk_disable_unprepare(priv->lcd_clk);
802 clk_disable_unprepare(priv->pix_clk);
803
804 drm_dev_unregister(&priv->drm);
805 drm_atomic_helper_shutdown(&priv->drm);
806
807 return 0;
808 }
809
810 static const struct jz_soc_info jz4740_soc_info = {
811 .needs_dev_clk = true,
812 };
813
814 static const struct jz_soc_info jz4725b_soc_info = {
815 .needs_dev_clk = false,
816 };
817
818 static const struct of_device_id ingenic_drm_of_match[] = {
819 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
820 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
821 { /* sentinel */ },
822 };
823
824 static struct platform_driver ingenic_drm_driver = {
825 .driver = {
826 .name = "ingenic-drm",
827 .of_match_table = of_match_ptr(ingenic_drm_of_match),
828 },
829 .probe = ingenic_drm_probe,
830 .remove = ingenic_drm_remove,
831 };
832 module_platform_driver(ingenic_drm_driver);
833
834 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
835 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
836 MODULE_LICENSE("GPL v2");
837