1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51
52 #include <rdma/ib_verbs.h>
53 #include <rdma/ib_user_verbs.h>
54 #include <rdma/ib_umem.h>
55 #include <rdma/ib_addr.h>
56
57 #include "bnxt_ulp.h"
58 #include "roce_hsi.h"
59 #include "qplib_res.h"
60 #include "qplib_sp.h"
61 #include "qplib_fp.h"
62 #include "qplib_rcfw.h"
63 #include "bnxt_re.h"
64 #include "ib_verbs.h"
65 #include <rdma/bnxt_re-abi.h>
66 #include "bnxt.h"
67 #include "hw_counters.h"
68
69 static char version[] =
70 BNXT_RE_DESC "\n";
71
72 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
73 MODULE_DESCRIPTION(BNXT_RE_DESC " Driver");
74 MODULE_LICENSE("Dual BSD/GPL");
75
76 /* globals */
77 static struct list_head bnxt_re_dev_list = LIST_HEAD_INIT(bnxt_re_dev_list);
78 /* Mutex to protect the list of bnxt_re devices added */
79 static DEFINE_MUTEX(bnxt_re_dev_lock);
80 static struct workqueue_struct *bnxt_re_wq;
81 static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev);
82
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)83 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
84 {
85 rdev->rcfw.res = NULL;
86 rdev->qplib_res.cctx = NULL;
87 }
88
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev)89 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
90 {
91 struct bnxt_en_dev *en_dev;
92 struct bnxt *bp;
93
94 en_dev = rdev->en_dev;
95 bp = netdev_priv(en_dev->net);
96
97 rdev->chip_ctx.chip_num = bp->chip_num;
98 /* rest members to follow eventually */
99
100 rdev->qplib_res.cctx = &rdev->chip_ctx;
101 rdev->rcfw.res = &rdev->qplib_res;
102
103 return 0;
104 }
105
106 /* SR-IOV helper functions */
107
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)108 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
109 {
110 struct bnxt *bp;
111
112 bp = netdev_priv(rdev->en_dev->net);
113 if (BNXT_VF(bp))
114 rdev->is_virtfn = 1;
115 }
116
117 /* Set the maximum number of each resource that the driver actually wants
118 * to allocate. This may be up to the maximum number the firmware has
119 * reserved for the function. The driver may choose to allocate fewer
120 * resources than the firmware maximum.
121 */
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)122 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
123 {
124 u32 vf_qps = 0, vf_srqs = 0, vf_cqs = 0, vf_mrws = 0, vf_gids = 0;
125 u32 i;
126 u32 vf_pct;
127 u32 num_vfs;
128 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
129
130 rdev->qplib_ctx.qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
131 dev_attr->max_qp);
132
133 rdev->qplib_ctx.mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
134 /* Use max_mr from fw since max_mrw does not get set */
135 rdev->qplib_ctx.mrw_count = min_t(u32, rdev->qplib_ctx.mrw_count,
136 dev_attr->max_mr);
137 rdev->qplib_ctx.srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
138 dev_attr->max_srq);
139 rdev->qplib_ctx.cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT,
140 dev_attr->max_cq);
141
142 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
143 rdev->qplib_ctx.tqm_count[i] =
144 rdev->dev_attr.tqm_alloc_reqs[i];
145
146 if (rdev->num_vfs) {
147 /*
148 * Reserve a set of resources for the PF. Divide the remaining
149 * resources among the VFs
150 */
151 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
152 num_vfs = 100 * rdev->num_vfs;
153 vf_qps = (rdev->qplib_ctx.qpc_count * vf_pct) / num_vfs;
154 vf_srqs = (rdev->qplib_ctx.srqc_count * vf_pct) / num_vfs;
155 vf_cqs = (rdev->qplib_ctx.cq_count * vf_pct) / num_vfs;
156 /*
157 * The driver allows many more MRs than other resources. If the
158 * firmware does also, then reserve a fixed amount for the PF
159 * and divide the rest among VFs. VFs may use many MRs for NFS
160 * mounts, ISER, NVME applications, etc. If the firmware
161 * severely restricts the number of MRs, then let PF have
162 * half and divide the rest among VFs, as for the other
163 * resource types.
164 */
165 if (rdev->qplib_ctx.mrw_count < BNXT_RE_MAX_MRW_COUNT_64K)
166 vf_mrws = rdev->qplib_ctx.mrw_count * vf_pct / num_vfs;
167 else
168 vf_mrws = (rdev->qplib_ctx.mrw_count -
169 BNXT_RE_RESVD_MR_FOR_PF) / rdev->num_vfs;
170 vf_gids = BNXT_RE_MAX_GID_PER_VF;
171 }
172 rdev->qplib_ctx.vf_res.max_mrw_per_vf = vf_mrws;
173 rdev->qplib_ctx.vf_res.max_gid_per_vf = vf_gids;
174 rdev->qplib_ctx.vf_res.max_qp_per_vf = vf_qps;
175 rdev->qplib_ctx.vf_res.max_srq_per_vf = vf_srqs;
176 rdev->qplib_ctx.vf_res.max_cq_per_vf = vf_cqs;
177 }
178
179 /* for handling bnxt_en callbacks later */
bnxt_re_stop(void * p)180 static void bnxt_re_stop(void *p)
181 {
182 }
183
bnxt_re_start(void * p)184 static void bnxt_re_start(void *p)
185 {
186 }
187
bnxt_re_sriov_config(void * p,int num_vfs)188 static void bnxt_re_sriov_config(void *p, int num_vfs)
189 {
190 struct bnxt_re_dev *rdev = p;
191
192 if (!rdev)
193 return;
194
195 rdev->num_vfs = num_vfs;
196 bnxt_re_set_resource_limits(rdev);
197 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
198 &rdev->qplib_ctx);
199 }
200
bnxt_re_shutdown(void * p)201 static void bnxt_re_shutdown(void *p)
202 {
203 struct bnxt_re_dev *rdev = p;
204
205 if (!rdev)
206 return;
207
208 bnxt_re_ib_unreg(rdev);
209 }
210
bnxt_re_stop_irq(void * handle)211 static void bnxt_re_stop_irq(void *handle)
212 {
213 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
214 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
215 struct bnxt_qplib_nq *nq;
216 int indx;
217
218 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) {
219 nq = &rdev->nq[indx - 1];
220 bnxt_qplib_nq_stop_irq(nq, false);
221 }
222
223 bnxt_qplib_rcfw_stop_irq(rcfw, false);
224 }
225
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)226 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
227 {
228 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
229 struct bnxt_msix_entry *msix_ent = rdev->msix_entries;
230 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
231 struct bnxt_qplib_nq *nq;
232 int indx, rc;
233
234 if (!ent) {
235 /* Not setting the f/w timeout bit in rcfw.
236 * During the driver unload the first command
237 * to f/w will timeout and that will set the
238 * timeout bit.
239 */
240 dev_err(rdev_to_dev(rdev), "Failed to re-start IRQs\n");
241 return;
242 }
243
244 /* Vectors may change after restart, so update with new vectors
245 * in device sctructure.
246 */
247 for (indx = 0; indx < rdev->num_msix; indx++)
248 rdev->msix_entries[indx].vector = ent[indx].vector;
249
250 bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
251 false);
252 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) {
253 nq = &rdev->nq[indx - 1];
254 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
255 msix_ent[indx].vector, false);
256 if (rc)
257 dev_warn(rdev_to_dev(rdev),
258 "Failed to reinit NQ index %d\n", indx - 1);
259 }
260 }
261
262 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
263 .ulp_async_notifier = NULL,
264 .ulp_stop = bnxt_re_stop,
265 .ulp_start = bnxt_re_start,
266 .ulp_sriov_config = bnxt_re_sriov_config,
267 .ulp_shutdown = bnxt_re_shutdown,
268 .ulp_irq_stop = bnxt_re_stop_irq,
269 .ulp_irq_restart = bnxt_re_start_irq
270 };
271
272 /* RoCE -> Net driver */
273
274 /* Driver registration routines used to let the networking driver (bnxt_en)
275 * to know that the RoCE driver is now installed
276 */
bnxt_re_unregister_netdev(struct bnxt_re_dev * rdev)277 static int bnxt_re_unregister_netdev(struct bnxt_re_dev *rdev)
278 {
279 struct bnxt_en_dev *en_dev;
280 int rc;
281
282 if (!rdev)
283 return -EINVAL;
284
285 en_dev = rdev->en_dev;
286
287 rc = en_dev->en_ops->bnxt_unregister_device(rdev->en_dev,
288 BNXT_ROCE_ULP);
289 return rc;
290 }
291
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)292 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
293 {
294 struct bnxt_en_dev *en_dev;
295 int rc = 0;
296
297 if (!rdev)
298 return -EINVAL;
299
300 en_dev = rdev->en_dev;
301
302 rc = en_dev->en_ops->bnxt_register_device(en_dev, BNXT_ROCE_ULP,
303 &bnxt_re_ulp_ops, rdev);
304 rdev->qplib_res.pdev = rdev->en_dev->pdev;
305 return rc;
306 }
307
bnxt_re_free_msix(struct bnxt_re_dev * rdev)308 static int bnxt_re_free_msix(struct bnxt_re_dev *rdev)
309 {
310 struct bnxt_en_dev *en_dev;
311 int rc;
312
313 if (!rdev)
314 return -EINVAL;
315
316 en_dev = rdev->en_dev;
317
318
319 rc = en_dev->en_ops->bnxt_free_msix(rdev->en_dev, BNXT_ROCE_ULP);
320
321 return rc;
322 }
323
bnxt_re_request_msix(struct bnxt_re_dev * rdev)324 static int bnxt_re_request_msix(struct bnxt_re_dev *rdev)
325 {
326 int rc = 0, num_msix_want = BNXT_RE_MAX_MSIX, num_msix_got;
327 struct bnxt_en_dev *en_dev;
328
329 if (!rdev)
330 return -EINVAL;
331
332 en_dev = rdev->en_dev;
333
334 num_msix_want = min_t(u32, BNXT_RE_MAX_MSIX, num_online_cpus());
335
336 num_msix_got = en_dev->en_ops->bnxt_request_msix(en_dev, BNXT_ROCE_ULP,
337 rdev->msix_entries,
338 num_msix_want);
339 if (num_msix_got < BNXT_RE_MIN_MSIX) {
340 rc = -EINVAL;
341 goto done;
342 }
343 if (num_msix_got != num_msix_want) {
344 dev_warn(rdev_to_dev(rdev),
345 "Requested %d MSI-X vectors, got %d\n",
346 num_msix_want, num_msix_got);
347 }
348 rdev->num_msix = num_msix_got;
349 done:
350 return rc;
351 }
352
bnxt_re_init_hwrm_hdr(struct bnxt_re_dev * rdev,struct input * hdr,u16 opcd,u16 crid,u16 trid)353 static void bnxt_re_init_hwrm_hdr(struct bnxt_re_dev *rdev, struct input *hdr,
354 u16 opcd, u16 crid, u16 trid)
355 {
356 hdr->req_type = cpu_to_le16(opcd);
357 hdr->cmpl_ring = cpu_to_le16(crid);
358 hdr->target_id = cpu_to_le16(trid);
359 }
360
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)361 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
362 int msg_len, void *resp, int resp_max_len,
363 int timeout)
364 {
365 fw_msg->msg = msg;
366 fw_msg->msg_len = msg_len;
367 fw_msg->resp = resp;
368 fw_msg->resp_max_len = resp_max_len;
369 fw_msg->timeout = timeout;
370 }
371
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)372 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
373 u16 fw_ring_id, int type)
374 {
375 struct bnxt_en_dev *en_dev = rdev->en_dev;
376 struct hwrm_ring_free_input req = {0};
377 struct hwrm_ring_free_output resp;
378 struct bnxt_fw_msg fw_msg;
379 int rc = -EINVAL;
380
381 if (!en_dev)
382 return rc;
383
384 memset(&fw_msg, 0, sizeof(fw_msg));
385
386 bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_RING_FREE, -1, -1);
387 req.ring_type = type;
388 req.ring_id = cpu_to_le16(fw_ring_id);
389 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
390 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
391 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
392 if (rc)
393 dev_err(rdev_to_dev(rdev),
394 "Failed to free HW ring:%d :%#x", req.ring_id, rc);
395 return rc;
396 }
397
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,dma_addr_t * dma_arr,int pages,int type,u32 ring_mask,u32 map_index,u16 * fw_ring_id)398 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, dma_addr_t *dma_arr,
399 int pages, int type, u32 ring_mask,
400 u32 map_index, u16 *fw_ring_id)
401 {
402 struct bnxt_en_dev *en_dev = rdev->en_dev;
403 struct hwrm_ring_alloc_input req = {0};
404 struct hwrm_ring_alloc_output resp;
405 struct bnxt_fw_msg fw_msg;
406 int rc = -EINVAL;
407
408 if (!en_dev)
409 return rc;
410
411 memset(&fw_msg, 0, sizeof(fw_msg));
412 bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_RING_ALLOC, -1, -1);
413 req.enables = 0;
414 req.page_tbl_addr = cpu_to_le64(dma_arr[0]);
415 if (pages > 1) {
416 /* Page size is in log2 units */
417 req.page_size = BNXT_PAGE_SHIFT;
418 req.page_tbl_depth = 1;
419 }
420 req.fbo = 0;
421 /* Association of ring index with doorbell index and MSIX number */
422 req.logical_id = cpu_to_le16(map_index);
423 req.length = cpu_to_le32(ring_mask + 1);
424 req.ring_type = type;
425 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
426 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
427 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
428 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
429 if (!rc)
430 *fw_ring_id = le16_to_cpu(resp.ring_id);
431
432 return rc;
433 }
434
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)435 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
436 u32 fw_stats_ctx_id)
437 {
438 struct bnxt_en_dev *en_dev = rdev->en_dev;
439 struct hwrm_stat_ctx_free_input req = {0};
440 struct bnxt_fw_msg fw_msg;
441 int rc = -EINVAL;
442
443 if (!en_dev)
444 return rc;
445
446 memset(&fw_msg, 0, sizeof(fw_msg));
447
448 bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_FREE, -1, -1);
449 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
450 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&req,
451 sizeof(req), DFLT_HWRM_CMD_TIMEOUT);
452 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
453 if (rc)
454 dev_err(rdev_to_dev(rdev),
455 "Failed to free HW stats context %#x", rc);
456
457 return rc;
458 }
459
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,dma_addr_t dma_map,u32 * fw_stats_ctx_id)460 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
461 dma_addr_t dma_map,
462 u32 *fw_stats_ctx_id)
463 {
464 struct hwrm_stat_ctx_alloc_output resp = {0};
465 struct hwrm_stat_ctx_alloc_input req = {0};
466 struct bnxt_en_dev *en_dev = rdev->en_dev;
467 struct bnxt_fw_msg fw_msg;
468 int rc = -EINVAL;
469
470 *fw_stats_ctx_id = INVALID_STATS_CTX_ID;
471
472 if (!en_dev)
473 return rc;
474
475 memset(&fw_msg, 0, sizeof(fw_msg));
476
477 bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_ALLOC, -1, -1);
478 req.update_period_ms = cpu_to_le32(1000);
479 req.stats_dma_addr = cpu_to_le64(dma_map);
480 req.stats_dma_length = cpu_to_le16(sizeof(struct ctx_hw_stats_ext));
481 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
482 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
483 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
484 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
485 if (!rc)
486 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
487
488 return rc;
489 }
490
491 /* Device */
492
is_bnxt_re_dev(struct net_device * netdev)493 static bool is_bnxt_re_dev(struct net_device *netdev)
494 {
495 struct ethtool_drvinfo drvinfo;
496
497 if (netdev->ethtool_ops && netdev->ethtool_ops->get_drvinfo) {
498 memset(&drvinfo, 0, sizeof(drvinfo));
499 netdev->ethtool_ops->get_drvinfo(netdev, &drvinfo);
500
501 if (strcmp(drvinfo.driver, "bnxt_en"))
502 return false;
503 return true;
504 }
505 return false;
506 }
507
bnxt_re_from_netdev(struct net_device * netdev)508 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
509 {
510 struct bnxt_re_dev *rdev;
511
512 rcu_read_lock();
513 list_for_each_entry_rcu(rdev, &bnxt_re_dev_list, list) {
514 if (rdev->netdev == netdev) {
515 rcu_read_unlock();
516 return rdev;
517 }
518 }
519 rcu_read_unlock();
520 return NULL;
521 }
522
bnxt_re_dev_unprobe(struct net_device * netdev,struct bnxt_en_dev * en_dev)523 static void bnxt_re_dev_unprobe(struct net_device *netdev,
524 struct bnxt_en_dev *en_dev)
525 {
526 dev_put(netdev);
527 module_put(en_dev->pdev->driver->driver.owner);
528 }
529
bnxt_re_dev_probe(struct net_device * netdev)530 static struct bnxt_en_dev *bnxt_re_dev_probe(struct net_device *netdev)
531 {
532 struct bnxt *bp = netdev_priv(netdev);
533 struct bnxt_en_dev *en_dev;
534 struct pci_dev *pdev;
535
536 /* Call bnxt_en's RoCE probe via indirect API */
537 if (!bp->ulp_probe)
538 return ERR_PTR(-EINVAL);
539
540 en_dev = bp->ulp_probe(netdev);
541 if (IS_ERR(en_dev))
542 return en_dev;
543
544 pdev = en_dev->pdev;
545 if (!pdev)
546 return ERR_PTR(-EINVAL);
547
548 if (!(en_dev->flags & BNXT_EN_FLAG_ROCE_CAP)) {
549 dev_info(&pdev->dev,
550 "%s: probe error: RoCE is not supported on this device",
551 ROCE_DRV_MODULE_NAME);
552 return ERR_PTR(-ENODEV);
553 }
554
555 /* Bump net device reference count */
556 if (!try_module_get(pdev->driver->driver.owner))
557 return ERR_PTR(-ENODEV);
558
559 dev_hold(netdev);
560
561 return en_dev;
562 }
563
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)564 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
565 char *buf)
566 {
567 struct bnxt_re_dev *rdev =
568 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
569
570 return scnprintf(buf, PAGE_SIZE, "0x%x\n", rdev->en_dev->pdev->vendor);
571 }
572 static DEVICE_ATTR_RO(hw_rev);
573
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)574 static ssize_t hca_type_show(struct device *device,
575 struct device_attribute *attr, char *buf)
576 {
577 struct bnxt_re_dev *rdev =
578 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
579
580 return scnprintf(buf, PAGE_SIZE, "%s\n", rdev->ibdev.node_desc);
581 }
582 static DEVICE_ATTR_RO(hca_type);
583
584 static struct attribute *bnxt_re_attributes[] = {
585 &dev_attr_hw_rev.attr,
586 &dev_attr_hca_type.attr,
587 NULL
588 };
589
590 static const struct attribute_group bnxt_re_dev_attr_group = {
591 .attrs = bnxt_re_attributes,
592 };
593
bnxt_re_unregister_ib(struct bnxt_re_dev * rdev)594 static void bnxt_re_unregister_ib(struct bnxt_re_dev *rdev)
595 {
596 ib_unregister_device(&rdev->ibdev);
597 }
598
599 static const struct ib_device_ops bnxt_re_dev_ops = {
600 .owner = THIS_MODULE,
601 .driver_id = RDMA_DRIVER_BNXT_RE,
602 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
603
604 .add_gid = bnxt_re_add_gid,
605 .alloc_hw_stats = bnxt_re_ib_alloc_hw_stats,
606 .alloc_mr = bnxt_re_alloc_mr,
607 .alloc_pd = bnxt_re_alloc_pd,
608 .alloc_ucontext = bnxt_re_alloc_ucontext,
609 .create_ah = bnxt_re_create_ah,
610 .create_cq = bnxt_re_create_cq,
611 .create_qp = bnxt_re_create_qp,
612 .create_srq = bnxt_re_create_srq,
613 .dealloc_pd = bnxt_re_dealloc_pd,
614 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
615 .del_gid = bnxt_re_del_gid,
616 .dereg_mr = bnxt_re_dereg_mr,
617 .destroy_ah = bnxt_re_destroy_ah,
618 .destroy_cq = bnxt_re_destroy_cq,
619 .destroy_qp = bnxt_re_destroy_qp,
620 .destroy_srq = bnxt_re_destroy_srq,
621 .get_dev_fw_str = bnxt_re_query_fw_str,
622 .get_dma_mr = bnxt_re_get_dma_mr,
623 .get_hw_stats = bnxt_re_ib_get_hw_stats,
624 .get_link_layer = bnxt_re_get_link_layer,
625 .get_port_immutable = bnxt_re_get_port_immutable,
626 .map_mr_sg = bnxt_re_map_mr_sg,
627 .mmap = bnxt_re_mmap,
628 .modify_ah = bnxt_re_modify_ah,
629 .modify_device = bnxt_re_modify_device,
630 .modify_qp = bnxt_re_modify_qp,
631 .modify_srq = bnxt_re_modify_srq,
632 .poll_cq = bnxt_re_poll_cq,
633 .post_recv = bnxt_re_post_recv,
634 .post_send = bnxt_re_post_send,
635 .post_srq_recv = bnxt_re_post_srq_recv,
636 .query_ah = bnxt_re_query_ah,
637 .query_device = bnxt_re_query_device,
638 .query_pkey = bnxt_re_query_pkey,
639 .query_port = bnxt_re_query_port,
640 .query_qp = bnxt_re_query_qp,
641 .query_srq = bnxt_re_query_srq,
642 .reg_user_mr = bnxt_re_reg_user_mr,
643 .req_notify_cq = bnxt_re_req_notify_cq,
644 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
645 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
646 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
647 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
648 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
649 };
650
bnxt_re_register_ib(struct bnxt_re_dev * rdev)651 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
652 {
653 struct ib_device *ibdev = &rdev->ibdev;
654 int ret;
655
656 /* ib device init */
657 ibdev->node_type = RDMA_NODE_IB_CA;
658 strlcpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
659 strlen(BNXT_RE_DESC) + 5);
660 ibdev->phys_port_cnt = 1;
661
662 bnxt_qplib_get_guid(rdev->netdev->dev_addr, (u8 *)&ibdev->node_guid);
663
664 ibdev->num_comp_vectors = 1;
665 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
666 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
667
668 /* User space */
669 ibdev->uverbs_cmd_mask =
670 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
671 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
672 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
673 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
674 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
675 (1ull << IB_USER_VERBS_CMD_REG_MR) |
676 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
677 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
678 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
679 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
680 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
681 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
682 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
683 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
684 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
685 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
686 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
687 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
688 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
689 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
690 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
691 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
692 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
693 (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
694 /* POLL_CQ and REQ_NOTIFY_CQ is directly handled in libbnxt_re */
695
696
697 rdma_set_device_sysfs_group(ibdev, &bnxt_re_dev_attr_group);
698 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
699 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
700 if (ret)
701 return ret;
702
703 return ib_register_device(ibdev, "bnxt_re%d");
704 }
705
bnxt_re_dev_remove(struct bnxt_re_dev * rdev)706 static void bnxt_re_dev_remove(struct bnxt_re_dev *rdev)
707 {
708 dev_put(rdev->netdev);
709 rdev->netdev = NULL;
710
711 mutex_lock(&bnxt_re_dev_lock);
712 list_del_rcu(&rdev->list);
713 mutex_unlock(&bnxt_re_dev_lock);
714
715 synchronize_rcu();
716
717 ib_dealloc_device(&rdev->ibdev);
718 /* rdev is gone */
719 }
720
bnxt_re_dev_add(struct net_device * netdev,struct bnxt_en_dev * en_dev)721 static struct bnxt_re_dev *bnxt_re_dev_add(struct net_device *netdev,
722 struct bnxt_en_dev *en_dev)
723 {
724 struct bnxt_re_dev *rdev;
725
726 /* Allocate bnxt_re_dev instance here */
727 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
728 if (!rdev) {
729 dev_err(NULL, "%s: bnxt_re_dev allocation failure!",
730 ROCE_DRV_MODULE_NAME);
731 return NULL;
732 }
733 /* Default values */
734 rdev->netdev = netdev;
735 dev_hold(rdev->netdev);
736 rdev->en_dev = en_dev;
737 rdev->id = rdev->en_dev->pdev->devfn;
738 INIT_LIST_HEAD(&rdev->qp_list);
739 mutex_init(&rdev->qp_lock);
740 atomic_set(&rdev->qp_count, 0);
741 atomic_set(&rdev->cq_count, 0);
742 atomic_set(&rdev->srq_count, 0);
743 atomic_set(&rdev->mr_count, 0);
744 atomic_set(&rdev->mw_count, 0);
745 rdev->cosq[0] = 0xFFFF;
746 rdev->cosq[1] = 0xFFFF;
747
748 mutex_lock(&bnxt_re_dev_lock);
749 list_add_tail_rcu(&rdev->list, &bnxt_re_dev_list);
750 mutex_unlock(&bnxt_re_dev_lock);
751 return rdev;
752 }
753
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)754 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
755 *unaffi_async)
756 {
757 switch (unaffi_async->event) {
758 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
759 break;
760 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
761 break;
762 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
763 break;
764 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
765 break;
766 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
767 break;
768 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
769 break;
770 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
771 break;
772 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
773 break;
774 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
775 break;
776 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
777 break;
778 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
779 break;
780 default:
781 return -EINVAL;
782 }
783 return 0;
784 }
785
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)786 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
787 struct bnxt_re_qp *qp)
788 {
789 struct ib_event event;
790 unsigned int flags;
791
792 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
793 flags = bnxt_re_lock_cqs(qp);
794 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
795 bnxt_re_unlock_cqs(qp, flags);
796 }
797
798 memset(&event, 0, sizeof(event));
799 if (qp->qplib_qp.srq) {
800 event.device = &qp->rdev->ibdev;
801 event.element.qp = &qp->ib_qp;
802 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
803 }
804
805 if (event.device && qp->ib_qp.event_handler)
806 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
807
808 return 0;
809 }
810
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)811 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
812 void *obj)
813 {
814 int rc = 0;
815 u8 event;
816
817 if (!obj)
818 return rc; /* QP was already dead, still return success */
819
820 event = affi_async->event;
821 if (event == CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION) {
822 struct bnxt_qplib_qp *lib_qp = obj;
823 struct bnxt_re_qp *qp = container_of(lib_qp, struct bnxt_re_qp,
824 qplib_qp);
825 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
826 }
827 return rc;
828 }
829
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)830 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
831 void *aeqe, void *obj)
832 {
833 struct creq_qp_event *affi_async;
834 struct creq_func_event *unaffi_async;
835 u8 type;
836 int rc;
837
838 type = ((struct creq_base *)aeqe)->type;
839 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
840 unaffi_async = aeqe;
841 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
842 } else {
843 affi_async = aeqe;
844 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
845 }
846
847 return rc;
848 }
849
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)850 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
851 struct bnxt_qplib_srq *handle, u8 event)
852 {
853 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
854 qplib_srq);
855 struct ib_event ib_event;
856 int rc = 0;
857
858 if (!srq) {
859 dev_err(NULL, "%s: SRQ is NULL, SRQN not handled",
860 ROCE_DRV_MODULE_NAME);
861 rc = -EINVAL;
862 goto done;
863 }
864 ib_event.device = &srq->rdev->ibdev;
865 ib_event.element.srq = &srq->ib_srq;
866 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
867 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
868 else
869 ib_event.event = IB_EVENT_SRQ_ERR;
870
871 if (srq->ib_srq.event_handler) {
872 /* Lock event_handler? */
873 (*srq->ib_srq.event_handler)(&ib_event,
874 srq->ib_srq.srq_context);
875 }
876 done:
877 return rc;
878 }
879
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)880 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
881 struct bnxt_qplib_cq *handle)
882 {
883 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
884 qplib_cq);
885
886 if (!cq) {
887 dev_err(NULL, "%s: CQ is NULL, CQN not handled",
888 ROCE_DRV_MODULE_NAME);
889 return -EINVAL;
890 }
891 if (cq->ib_cq.comp_handler) {
892 /* Lock comp_handler? */
893 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
894 }
895
896 return 0;
897 }
898
bnxt_re_get_nqdb_offset(struct bnxt_re_dev * rdev,u16 indx)899 static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)
900 {
901 return bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ?
902 0x10000 : rdev->msix_entries[indx].db_offset;
903 }
904
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)905 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
906 {
907 int i;
908
909 for (i = 1; i < rdev->num_msix; i++)
910 bnxt_qplib_disable_nq(&rdev->nq[i - 1]);
911
912 if (rdev->qplib_res.rcfw)
913 bnxt_qplib_cleanup_res(&rdev->qplib_res);
914 }
915
bnxt_re_init_res(struct bnxt_re_dev * rdev)916 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
917 {
918 int num_vec_enabled = 0;
919 int rc = 0, i;
920 u32 db_offt;
921
922 bnxt_qplib_init_res(&rdev->qplib_res);
923
924 for (i = 1; i < rdev->num_msix ; i++) {
925 db_offt = bnxt_re_get_nqdb_offset(rdev, i);
926 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
927 i - 1, rdev->msix_entries[i].vector,
928 db_offt, &bnxt_re_cqn_handler,
929 &bnxt_re_srqn_handler);
930 if (rc) {
931 dev_err(rdev_to_dev(rdev),
932 "Failed to enable NQ with rc = 0x%x", rc);
933 goto fail;
934 }
935 num_vec_enabled++;
936 }
937 return 0;
938 fail:
939 for (i = num_vec_enabled; i >= 0; i--)
940 bnxt_qplib_disable_nq(&rdev->nq[i]);
941 return rc;
942 }
943
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)944 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
945 {
946 u8 type;
947 int i;
948
949 for (i = 0; i < rdev->num_msix - 1; i++) {
950 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
951 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
952 rdev->nq[i].res = NULL;
953 bnxt_qplib_free_nq(&rdev->nq[i]);
954 }
955 }
956
bnxt_re_free_res(struct bnxt_re_dev * rdev)957 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
958 {
959 bnxt_re_free_nq_res(rdev);
960
961 if (rdev->qplib_res.dpi_tbl.max) {
962 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
963 &rdev->qplib_res.dpi_tbl,
964 &rdev->dpi_privileged);
965 }
966 if (rdev->qplib_res.rcfw) {
967 bnxt_qplib_free_res(&rdev->qplib_res);
968 rdev->qplib_res.rcfw = NULL;
969 }
970 }
971
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)972 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
973 {
974 int num_vec_created = 0;
975 dma_addr_t *pg_map;
976 int rc = 0, i;
977 int pages;
978 u8 type;
979
980 /* Configure and allocate resources for qplib */
981 rdev->qplib_res.rcfw = &rdev->rcfw;
982 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr,
983 rdev->is_virtfn);
984 if (rc)
985 goto fail;
986
987 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev,
988 rdev->netdev, &rdev->dev_attr);
989 if (rc)
990 goto fail;
991
992 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
993 &rdev->dpi_privileged,
994 rdev);
995 if (rc)
996 goto dealloc_res;
997
998 for (i = 0; i < rdev->num_msix - 1; i++) {
999 rdev->nq[i].res = &rdev->qplib_res;
1000 rdev->nq[i].hwq.max_elements = BNXT_RE_MAX_CQ_COUNT +
1001 BNXT_RE_MAX_SRQC_COUNT + 2;
1002 rc = bnxt_qplib_alloc_nq(rdev->en_dev->pdev, &rdev->nq[i]);
1003 if (rc) {
1004 dev_err(rdev_to_dev(rdev), "Alloc Failed NQ%d rc:%#x",
1005 i, rc);
1006 goto free_nq;
1007 }
1008 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
1009 pg_map = rdev->nq[i].hwq.pbl[PBL_LVL_0].pg_map_arr;
1010 pages = rdev->nq[i].hwq.pbl[rdev->nq[i].hwq.level].pg_count;
1011 rc = bnxt_re_net_ring_alloc(rdev, pg_map, pages, type,
1012 BNXT_QPLIB_NQE_MAX_CNT - 1,
1013 rdev->msix_entries[i + 1].ring_idx,
1014 &rdev->nq[i].ring_id);
1015 if (rc) {
1016 dev_err(rdev_to_dev(rdev),
1017 "Failed to allocate NQ fw id with rc = 0x%x",
1018 rc);
1019 bnxt_qplib_free_nq(&rdev->nq[i]);
1020 goto free_nq;
1021 }
1022 num_vec_created++;
1023 }
1024 return 0;
1025 free_nq:
1026 for (i = num_vec_created; i >= 0; i--) {
1027 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
1028 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
1029 bnxt_qplib_free_nq(&rdev->nq[i]);
1030 }
1031 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1032 &rdev->qplib_res.dpi_tbl,
1033 &rdev->dpi_privileged);
1034 dealloc_res:
1035 bnxt_qplib_free_res(&rdev->qplib_res);
1036
1037 fail:
1038 rdev->qplib_res.rcfw = NULL;
1039 return rc;
1040 }
1041
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1042 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1043 u8 port_num, enum ib_event_type event)
1044 {
1045 struct ib_event ib_event;
1046
1047 ib_event.device = ibdev;
1048 if (qp) {
1049 ib_event.element.qp = qp;
1050 ib_event.event = event;
1051 if (qp->event_handler)
1052 qp->event_handler(&ib_event, qp->qp_context);
1053
1054 } else {
1055 ib_event.element.port_num = port_num;
1056 ib_event.event = event;
1057 ib_dispatch_event(&ib_event);
1058 }
1059 }
1060
1061 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN 0x02
bnxt_re_query_hwrm_pri2cos(struct bnxt_re_dev * rdev,u8 dir,u64 * cid_map)1062 static int bnxt_re_query_hwrm_pri2cos(struct bnxt_re_dev *rdev, u8 dir,
1063 u64 *cid_map)
1064 {
1065 struct hwrm_queue_pri2cos_qcfg_input req = {0};
1066 struct bnxt *bp = netdev_priv(rdev->netdev);
1067 struct hwrm_queue_pri2cos_qcfg_output resp;
1068 struct bnxt_en_dev *en_dev = rdev->en_dev;
1069 struct bnxt_fw_msg fw_msg;
1070 u32 flags = 0;
1071 u8 *qcfgmap, *tmp_map;
1072 int rc = 0, i;
1073
1074 if (!cid_map)
1075 return -EINVAL;
1076
1077 memset(&fw_msg, 0, sizeof(fw_msg));
1078 bnxt_re_init_hwrm_hdr(rdev, (void *)&req,
1079 HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
1080 flags |= (dir & 0x01);
1081 flags |= HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN;
1082 req.flags = cpu_to_le32(flags);
1083 req.port_id = bp->pf.port_id;
1084
1085 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1086 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1087 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
1088 if (rc)
1089 return rc;
1090
1091 if (resp.queue_cfg_info) {
1092 dev_warn(rdev_to_dev(rdev),
1093 "Asymmetric cos queue configuration detected");
1094 dev_warn(rdev_to_dev(rdev),
1095 " on device, QoS may not be fully functional\n");
1096 }
1097 qcfgmap = &resp.pri0_cos_queue_id;
1098 tmp_map = (u8 *)cid_map;
1099 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1100 tmp_map[i] = qcfgmap[i];
1101
1102 return rc;
1103 }
1104
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1105 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1106 struct bnxt_re_qp *qp)
1107 {
1108 return (qp->ib_qp.qp_type == IB_QPT_GSI) || (qp == rdev->qp1_sqp);
1109 }
1110
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1111 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1112 {
1113 int mask = IB_QP_STATE;
1114 struct ib_qp_attr qp_attr;
1115 struct bnxt_re_qp *qp;
1116
1117 qp_attr.qp_state = IB_QPS_ERR;
1118 mutex_lock(&rdev->qp_lock);
1119 list_for_each_entry(qp, &rdev->qp_list, list) {
1120 /* Modify the state of all QPs except QP1/Shadow QP */
1121 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1122 if (qp->qplib_qp.state !=
1123 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1124 qp->qplib_qp.state !=
1125 CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1126 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1127 1, IB_EVENT_QP_FATAL);
1128 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask,
1129 NULL);
1130 }
1131 }
1132 }
1133 mutex_unlock(&rdev->qp_lock);
1134 }
1135
bnxt_re_update_gid(struct bnxt_re_dev * rdev)1136 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
1137 {
1138 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1139 struct bnxt_qplib_gid gid;
1140 u16 gid_idx, index;
1141 int rc = 0;
1142
1143 if (!test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
1144 return 0;
1145
1146 if (!sgid_tbl) {
1147 dev_err(rdev_to_dev(rdev), "QPLIB: SGID table not allocated");
1148 return -EINVAL;
1149 }
1150
1151 for (index = 0; index < sgid_tbl->active; index++) {
1152 gid_idx = sgid_tbl->hw_id[index];
1153
1154 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1155 sizeof(bnxt_qplib_gid_zero)))
1156 continue;
1157 /* need to modify the VLAN enable setting of non VLAN GID only
1158 * as setting is done for VLAN GID while adding GID
1159 */
1160 if (sgid_tbl->vlan[index])
1161 continue;
1162
1163 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1164
1165 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1166 rdev->qplib_res.netdev->dev_addr);
1167 }
1168
1169 return rc;
1170 }
1171
bnxt_re_get_priority_mask(struct bnxt_re_dev * rdev)1172 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1173 {
1174 u32 prio_map = 0, tmp_map = 0;
1175 struct net_device *netdev;
1176 struct dcb_app app;
1177
1178 netdev = rdev->netdev;
1179
1180 memset(&app, 0, sizeof(app));
1181 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1182 app.protocol = ETH_P_IBOE;
1183 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1184 prio_map = tmp_map;
1185
1186 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1187 app.protocol = ROCE_V2_UDP_DPORT;
1188 tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1189 prio_map |= tmp_map;
1190
1191 return prio_map;
1192 }
1193
bnxt_re_parse_cid_map(u8 prio_map,u8 * cid_map,u16 * cosq)1194 static void bnxt_re_parse_cid_map(u8 prio_map, u8 *cid_map, u16 *cosq)
1195 {
1196 u16 prio;
1197 u8 id;
1198
1199 for (prio = 0, id = 0; prio < 8; prio++) {
1200 if (prio_map & (1 << prio)) {
1201 cosq[id] = cid_map[prio];
1202 id++;
1203 if (id == 2) /* Max 2 tcs supported */
1204 break;
1205 }
1206 }
1207 }
1208
bnxt_re_setup_qos(struct bnxt_re_dev * rdev)1209 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1210 {
1211 u8 prio_map = 0;
1212 u64 cid_map;
1213 int rc;
1214
1215 /* Get priority for roce */
1216 prio_map = bnxt_re_get_priority_mask(rdev);
1217
1218 if (prio_map == rdev->cur_prio_map)
1219 return 0;
1220 rdev->cur_prio_map = prio_map;
1221 /* Get cosq id for this priority */
1222 rc = bnxt_re_query_hwrm_pri2cos(rdev, 0, &cid_map);
1223 if (rc) {
1224 dev_warn(rdev_to_dev(rdev), "no cos for p_mask %x\n", prio_map);
1225 return rc;
1226 }
1227 /* Parse CoS IDs for app priority */
1228 bnxt_re_parse_cid_map(prio_map, (u8 *)&cid_map, rdev->cosq);
1229
1230 /* Config BONO. */
1231 rc = bnxt_qplib_map_tc2cos(&rdev->qplib_res, rdev->cosq);
1232 if (rc) {
1233 dev_warn(rdev_to_dev(rdev), "no tc for cos{%x, %x}\n",
1234 rdev->cosq[0], rdev->cosq[1]);
1235 return rc;
1236 }
1237
1238 /* Actual priorities are not programmed as they are already
1239 * done by L2 driver; just enable or disable priority vlan tagging
1240 */
1241 if ((prio_map == 0 && rdev->qplib_res.prio) ||
1242 (prio_map != 0 && !rdev->qplib_res.prio)) {
1243 rdev->qplib_res.prio = prio_map ? true : false;
1244
1245 bnxt_re_update_gid(rdev);
1246 }
1247
1248 return 0;
1249 }
1250
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1251 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1252 {
1253 struct bnxt_en_dev *en_dev = rdev->en_dev;
1254 struct hwrm_ver_get_output resp = {0};
1255 struct hwrm_ver_get_input req = {0};
1256 struct bnxt_fw_msg fw_msg;
1257 int rc = 0;
1258
1259 memset(&fw_msg, 0, sizeof(fw_msg));
1260 bnxt_re_init_hwrm_hdr(rdev, (void *)&req,
1261 HWRM_VER_GET, -1, -1);
1262 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1263 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1264 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1265 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1266 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1267 rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
1268 if (rc) {
1269 dev_err(rdev_to_dev(rdev),
1270 "Failed to query HW version, rc = 0x%x", rc);
1271 return;
1272 }
1273 rdev->qplib_ctx.hwrm_intf_ver =
1274 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1275 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1276 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1277 le16_to_cpu(resp.hwrm_intf_patch);
1278 }
1279
bnxt_re_ib_unreg(struct bnxt_re_dev * rdev)1280 static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev)
1281 {
1282 u8 type;
1283 int rc;
1284
1285 if (test_and_clear_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags)) {
1286 /* Cleanup ib dev */
1287 bnxt_re_unregister_ib(rdev);
1288 }
1289 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1290 cancel_delayed_work_sync(&rdev->worker);
1291
1292 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1293 &rdev->flags))
1294 bnxt_re_cleanup_res(rdev);
1295 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1296 bnxt_re_free_res(rdev);
1297
1298 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1299 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1300 if (rc)
1301 dev_warn(rdev_to_dev(rdev),
1302 "Failed to deinitialize RCFW: %#x", rc);
1303 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1304 bnxt_qplib_free_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx);
1305 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1306 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
1307 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id, type);
1308 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1309 }
1310 if (test_and_clear_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags)) {
1311 rc = bnxt_re_free_msix(rdev);
1312 if (rc)
1313 dev_warn(rdev_to_dev(rdev),
1314 "Failed to free MSI-X vectors: %#x", rc);
1315 }
1316
1317 bnxt_re_destroy_chip_ctx(rdev);
1318 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) {
1319 rc = bnxt_re_unregister_netdev(rdev);
1320 if (rc)
1321 dev_warn(rdev_to_dev(rdev),
1322 "Failed to unregister with netdev: %#x", rc);
1323 }
1324 }
1325
1326 /* worker thread for polling periodic events. Now used for QoS programming*/
bnxt_re_worker(struct work_struct * work)1327 static void bnxt_re_worker(struct work_struct *work)
1328 {
1329 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1330 worker.work);
1331
1332 bnxt_re_setup_qos(rdev);
1333 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1334 }
1335
bnxt_re_ib_reg(struct bnxt_re_dev * rdev)1336 static int bnxt_re_ib_reg(struct bnxt_re_dev *rdev)
1337 {
1338 dma_addr_t *pg_map;
1339 u32 db_offt, ridx;
1340 int pages, vid;
1341 bool locked;
1342 u8 type;
1343 int rc;
1344
1345 /* Acquire rtnl lock through out this function */
1346 rtnl_lock();
1347 locked = true;
1348
1349 /* Registered a new RoCE device instance to netdev */
1350 rc = bnxt_re_register_netdev(rdev);
1351 if (rc) {
1352 rtnl_unlock();
1353 pr_err("Failed to register with netedev: %#x\n", rc);
1354 return -EINVAL;
1355 }
1356 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1357
1358 rc = bnxt_re_setup_chip_ctx(rdev);
1359 if (rc) {
1360 dev_err(rdev_to_dev(rdev), "Failed to get chip context\n");
1361 return -EINVAL;
1362 }
1363
1364 /* Check whether VF or PF */
1365 bnxt_re_get_sriov_func_type(rdev);
1366
1367 rc = bnxt_re_request_msix(rdev);
1368 if (rc) {
1369 pr_err("Failed to get MSI-X vectors: %#x\n", rc);
1370 rc = -EINVAL;
1371 goto fail;
1372 }
1373 set_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags);
1374
1375 bnxt_re_query_hwrm_intf_version(rdev);
1376
1377 /* Establish RCFW Communication Channel to initialize the context
1378 * memory for the function and all child VFs
1379 */
1380 rc = bnxt_qplib_alloc_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw,
1381 &rdev->qplib_ctx,
1382 BNXT_RE_MAX_QPC_COUNT);
1383 if (rc) {
1384 pr_err("Failed to allocate RCFW Channel: %#x\n", rc);
1385 goto fail;
1386 }
1387 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
1388 pg_map = rdev->rcfw.creq.pbl[PBL_LVL_0].pg_map_arr;
1389 pages = rdev->rcfw.creq.pbl[rdev->rcfw.creq.level].pg_count;
1390 ridx = rdev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1391 rc = bnxt_re_net_ring_alloc(rdev, pg_map, pages, type,
1392 BNXT_QPLIB_CREQE_MAX_CNT - 1,
1393 ridx, &rdev->rcfw.creq_ring_id);
1394 if (rc) {
1395 pr_err("Failed to allocate CREQ: %#x\n", rc);
1396 goto free_rcfw;
1397 }
1398 db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);
1399 vid = rdev->msix_entries[BNXT_RE_AEQ_IDX].vector;
1400 rc = bnxt_qplib_enable_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw,
1401 vid, db_offt, rdev->is_virtfn,
1402 &bnxt_re_aeq_handler);
1403 if (rc) {
1404 pr_err("Failed to enable RCFW channel: %#x\n", rc);
1405 goto free_ring;
1406 }
1407
1408 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr,
1409 rdev->is_virtfn);
1410 if (rc)
1411 goto disable_rcfw;
1412 if (!rdev->is_virtfn)
1413 bnxt_re_set_resource_limits(rdev);
1414
1415 rc = bnxt_qplib_alloc_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx, 0,
1416 bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx));
1417 if (rc) {
1418 pr_err("Failed to allocate QPLIB context: %#x\n", rc);
1419 goto disable_rcfw;
1420 }
1421 rc = bnxt_re_net_stats_ctx_alloc(rdev,
1422 rdev->qplib_ctx.stats.dma_map,
1423 &rdev->qplib_ctx.stats.fw_id);
1424 if (rc) {
1425 pr_err("Failed to allocate stats context: %#x\n", rc);
1426 goto free_ctx;
1427 }
1428
1429 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1430 rdev->is_virtfn);
1431 if (rc) {
1432 pr_err("Failed to initialize RCFW: %#x\n", rc);
1433 goto free_sctx;
1434 }
1435 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1436
1437 /* Resources based on the 'new' device caps */
1438 rc = bnxt_re_alloc_res(rdev);
1439 if (rc) {
1440 pr_err("Failed to allocate resources: %#x\n", rc);
1441 goto fail;
1442 }
1443 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1444 rc = bnxt_re_init_res(rdev);
1445 if (rc) {
1446 pr_err("Failed to initialize resources: %#x\n", rc);
1447 goto fail;
1448 }
1449
1450 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1451
1452 if (!rdev->is_virtfn) {
1453 rc = bnxt_re_setup_qos(rdev);
1454 if (rc)
1455 pr_info("RoCE priority not yet configured\n");
1456
1457 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1458 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1459 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1460 }
1461
1462 rtnl_unlock();
1463 locked = false;
1464
1465 /* Register ib dev */
1466 rc = bnxt_re_register_ib(rdev);
1467 if (rc) {
1468 pr_err("Failed to register with IB: %#x\n", rc);
1469 goto fail;
1470 }
1471 set_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags);
1472 dev_info(rdev_to_dev(rdev), "Device registered successfully");
1473 ib_get_eth_speed(&rdev->ibdev, 1, &rdev->active_speed,
1474 &rdev->active_width);
1475 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1476 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, IB_EVENT_PORT_ACTIVE);
1477
1478 return 0;
1479 free_sctx:
1480 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1481 free_ctx:
1482 bnxt_qplib_free_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx);
1483 disable_rcfw:
1484 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1485 free_ring:
1486 type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
1487 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id, type);
1488 free_rcfw:
1489 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1490 fail:
1491 if (!locked)
1492 rtnl_lock();
1493 bnxt_re_ib_unreg(rdev);
1494 rtnl_unlock();
1495
1496 return rc;
1497 }
1498
bnxt_re_dev_unreg(struct bnxt_re_dev * rdev)1499 static void bnxt_re_dev_unreg(struct bnxt_re_dev *rdev)
1500 {
1501 struct bnxt_en_dev *en_dev = rdev->en_dev;
1502 struct net_device *netdev = rdev->netdev;
1503
1504 bnxt_re_dev_remove(rdev);
1505
1506 if (netdev)
1507 bnxt_re_dev_unprobe(netdev, en_dev);
1508 }
1509
bnxt_re_dev_reg(struct bnxt_re_dev ** rdev,struct net_device * netdev)1510 static int bnxt_re_dev_reg(struct bnxt_re_dev **rdev, struct net_device *netdev)
1511 {
1512 struct bnxt_en_dev *en_dev;
1513 int rc = 0;
1514
1515 if (!is_bnxt_re_dev(netdev))
1516 return -ENODEV;
1517
1518 en_dev = bnxt_re_dev_probe(netdev);
1519 if (IS_ERR(en_dev)) {
1520 if (en_dev != ERR_PTR(-ENODEV))
1521 pr_err("%s: Failed to probe\n", ROCE_DRV_MODULE_NAME);
1522 rc = PTR_ERR(en_dev);
1523 goto exit;
1524 }
1525 *rdev = bnxt_re_dev_add(netdev, en_dev);
1526 if (!*rdev) {
1527 rc = -ENOMEM;
1528 bnxt_re_dev_unprobe(netdev, en_dev);
1529 goto exit;
1530 }
1531 exit:
1532 return rc;
1533 }
1534
bnxt_re_remove_one(struct bnxt_re_dev * rdev)1535 static void bnxt_re_remove_one(struct bnxt_re_dev *rdev)
1536 {
1537 pci_dev_put(rdev->en_dev->pdev);
1538 }
1539
1540 /* Handle all deferred netevents tasks */
bnxt_re_task(struct work_struct * work)1541 static void bnxt_re_task(struct work_struct *work)
1542 {
1543 struct bnxt_re_work *re_work;
1544 struct bnxt_re_dev *rdev;
1545 int rc = 0;
1546
1547 re_work = container_of(work, struct bnxt_re_work, work);
1548 rdev = re_work->rdev;
1549
1550 if (re_work->event != NETDEV_REGISTER &&
1551 !test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
1552 return;
1553
1554 switch (re_work->event) {
1555 case NETDEV_REGISTER:
1556 rc = bnxt_re_ib_reg(rdev);
1557 if (rc) {
1558 dev_err(rdev_to_dev(rdev),
1559 "Failed to register with IB: %#x", rc);
1560 bnxt_re_remove_one(rdev);
1561 bnxt_re_dev_unreg(rdev);
1562 goto exit;
1563 }
1564 break;
1565 case NETDEV_UP:
1566 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1567 IB_EVENT_PORT_ACTIVE);
1568 break;
1569 case NETDEV_DOWN:
1570 bnxt_re_dev_stop(rdev);
1571 break;
1572 case NETDEV_CHANGE:
1573 if (!netif_carrier_ok(rdev->netdev))
1574 bnxt_re_dev_stop(rdev);
1575 else if (netif_carrier_ok(rdev->netdev))
1576 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1577 IB_EVENT_PORT_ACTIVE);
1578 ib_get_eth_speed(&rdev->ibdev, 1, &rdev->active_speed,
1579 &rdev->active_width);
1580 break;
1581 default:
1582 break;
1583 }
1584 smp_mb__before_atomic();
1585 atomic_dec(&rdev->sched_count);
1586 exit:
1587 kfree(re_work);
1588 }
1589
bnxt_re_init_one(struct bnxt_re_dev * rdev)1590 static void bnxt_re_init_one(struct bnxt_re_dev *rdev)
1591 {
1592 pci_dev_get(rdev->en_dev->pdev);
1593 }
1594
1595 /*
1596 * "Notifier chain callback can be invoked for the same chain from
1597 * different CPUs at the same time".
1598 *
1599 * For cases when the netdev is already present, our call to the
1600 * register_netdevice_notifier() will actually get the rtnl_lock()
1601 * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1602 * events.
1603 *
1604 * But for cases when the netdev is not already present, the notifier
1605 * chain is subjected to be invoked from different CPUs simultaneously.
1606 *
1607 * This is protected by the netdev_mutex.
1608 */
bnxt_re_netdev_event(struct notifier_block * notifier,unsigned long event,void * ptr)1609 static int bnxt_re_netdev_event(struct notifier_block *notifier,
1610 unsigned long event, void *ptr)
1611 {
1612 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1613 struct bnxt_re_work *re_work;
1614 struct bnxt_re_dev *rdev;
1615 int rc = 0;
1616 bool sch_work = false;
1617
1618 real_dev = rdma_vlan_dev_real_dev(netdev);
1619 if (!real_dev)
1620 real_dev = netdev;
1621
1622 rdev = bnxt_re_from_netdev(real_dev);
1623 if (!rdev && event != NETDEV_REGISTER)
1624 goto exit;
1625 if (real_dev != netdev)
1626 goto exit;
1627
1628 switch (event) {
1629 case NETDEV_REGISTER:
1630 if (rdev)
1631 break;
1632 rc = bnxt_re_dev_reg(&rdev, real_dev);
1633 if (rc == -ENODEV)
1634 break;
1635 if (rc) {
1636 pr_err("Failed to register with the device %s: %#x\n",
1637 real_dev->name, rc);
1638 break;
1639 }
1640 bnxt_re_init_one(rdev);
1641 sch_work = true;
1642 break;
1643
1644 case NETDEV_UNREGISTER:
1645 /* netdev notifier will call NETDEV_UNREGISTER again later since
1646 * we are still holding the reference to the netdev
1647 */
1648 if (atomic_read(&rdev->sched_count) > 0)
1649 goto exit;
1650 bnxt_re_ib_unreg(rdev);
1651 bnxt_re_remove_one(rdev);
1652 bnxt_re_dev_unreg(rdev);
1653 break;
1654
1655 default:
1656 sch_work = true;
1657 break;
1658 }
1659 if (sch_work) {
1660 /* Allocate for the deferred task */
1661 re_work = kzalloc(sizeof(*re_work), GFP_ATOMIC);
1662 if (re_work) {
1663 re_work->rdev = rdev;
1664 re_work->event = event;
1665 re_work->vlan_dev = (real_dev == netdev ?
1666 NULL : netdev);
1667 INIT_WORK(&re_work->work, bnxt_re_task);
1668 atomic_inc(&rdev->sched_count);
1669 queue_work(bnxt_re_wq, &re_work->work);
1670 }
1671 }
1672
1673 exit:
1674 return NOTIFY_DONE;
1675 }
1676
1677 static struct notifier_block bnxt_re_netdev_notifier = {
1678 .notifier_call = bnxt_re_netdev_event
1679 };
1680
bnxt_re_mod_init(void)1681 static int __init bnxt_re_mod_init(void)
1682 {
1683 int rc = 0;
1684
1685 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
1686
1687 bnxt_re_wq = create_singlethread_workqueue("bnxt_re");
1688 if (!bnxt_re_wq)
1689 return -ENOMEM;
1690
1691 INIT_LIST_HEAD(&bnxt_re_dev_list);
1692
1693 rc = register_netdevice_notifier(&bnxt_re_netdev_notifier);
1694 if (rc) {
1695 pr_err("%s: Cannot register to netdevice_notifier",
1696 ROCE_DRV_MODULE_NAME);
1697 goto err_netdev;
1698 }
1699 return 0;
1700
1701 err_netdev:
1702 destroy_workqueue(bnxt_re_wq);
1703
1704 return rc;
1705 }
1706
bnxt_re_mod_exit(void)1707 static void __exit bnxt_re_mod_exit(void)
1708 {
1709 struct bnxt_re_dev *rdev, *next;
1710 LIST_HEAD(to_be_deleted);
1711
1712 mutex_lock(&bnxt_re_dev_lock);
1713 /* Free all adapter allocated resources */
1714 if (!list_empty(&bnxt_re_dev_list))
1715 list_splice_init(&bnxt_re_dev_list, &to_be_deleted);
1716 mutex_unlock(&bnxt_re_dev_lock);
1717 /*
1718 * Cleanup the devices in reverse order so that the VF device
1719 * cleanup is done before PF cleanup
1720 */
1721 list_for_each_entry_safe_reverse(rdev, next, &to_be_deleted, list) {
1722 dev_info(rdev_to_dev(rdev), "Unregistering Device");
1723 /*
1724 * Flush out any scheduled tasks before destroying the
1725 * resources
1726 */
1727 flush_workqueue(bnxt_re_wq);
1728 bnxt_re_dev_stop(rdev);
1729 /* Acquire the rtnl_lock as the L2 resources are freed here */
1730 rtnl_lock();
1731 bnxt_re_ib_unreg(rdev);
1732 rtnl_unlock();
1733 bnxt_re_remove_one(rdev);
1734 bnxt_re_dev_unreg(rdev);
1735 }
1736 unregister_netdevice_notifier(&bnxt_re_netdev_notifier);
1737 if (bnxt_re_wq)
1738 destroy_workqueue(bnxt_re_wq);
1739 }
1740
1741 module_init(bnxt_re_mod_init);
1742 module_exit(bnxt_re_mod_exit);
1743