1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * H8S interrupt controller driver
4 *
5 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6 */
7
8 #include <linux/irq.h>
9 #include <linux/irqchip.h>
10 #include <linux/of_address.h>
11 #include <linux/of_irq.h>
12 #include <asm/io.h>
13
14 static void *intc_baseaddr;
15 #define IPRA (intc_baseaddr)
16
17 static const unsigned char ipr_table[] = {
18 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
19 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
20 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
21 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
22 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
23 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
24 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
25 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
26 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
27 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
28 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
29 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
30 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
31 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
32 };
33
h8s_disable_irq(struct irq_data * data)34 static void h8s_disable_irq(struct irq_data *data)
35 {
36 int pos;
37 void __iomem *addr;
38 unsigned short pri;
39 int irq = data->irq;
40
41 addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
42 pos = (ipr_table[irq - 16] & 0x0f) * 4;
43 pri = ~(0x000f << pos);
44 pri &= readw(addr);
45 writew(pri, addr);
46 }
47
h8s_enable_irq(struct irq_data * data)48 static void h8s_enable_irq(struct irq_data *data)
49 {
50 int pos;
51 void __iomem *addr;
52 unsigned short pri;
53 int irq = data->irq;
54
55 addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
56 pos = (ipr_table[irq - 16] & 0x0f) * 4;
57 pri = ~(0x000f << pos);
58 pri &= readw(addr);
59 pri |= 1 << pos;
60 writew(pri, addr);
61 }
62
63 struct irq_chip h8s_irq_chip = {
64 .name = "H8S-INTC",
65 .irq_enable = h8s_enable_irq,
66 .irq_disable = h8s_disable_irq,
67 };
68
irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw_irq_num)69 static __init int irq_map(struct irq_domain *h, unsigned int virq,
70 irq_hw_number_t hw_irq_num)
71 {
72 irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
73
74 return 0;
75 }
76
77 static const struct irq_domain_ops irq_ops = {
78 .map = irq_map,
79 .xlate = irq_domain_xlate_onecell,
80 };
81
h8s_intc_of_init(struct device_node * intc,struct device_node * parent)82 static int __init h8s_intc_of_init(struct device_node *intc,
83 struct device_node *parent)
84 {
85 struct irq_domain *domain;
86 int n;
87
88 intc_baseaddr = of_iomap(intc, 0);
89 BUG_ON(!intc_baseaddr);
90
91 /* All interrupt priority is 0 (disable) */
92 /* IPRA to IPRK */
93 for (n = 0; n <= 'k' - 'a'; n++)
94 writew(0x0000, IPRA + (n * 2));
95
96 domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
97 BUG_ON(!domain);
98 irq_set_default_host(domain);
99 return 0;
100 }
101
102 IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);
103