1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <soc/mediatek/smi.h>
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18
19 /* mt8173 */
20 #define SMI_LARB_MMU_EN 0xf00
21
22 /* mt2701 */
23 #define REG_SMI_SECUR_CON_BASE 0x5c0
24
25 /* every register control 8 port, register offset 0x4 */
26 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
27 #define REG_SMI_SECUR_CON_ADDR(id) \
28 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
29
30 /*
31 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
32 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
33 * or non-security.
34 */
35 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
36 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
37 /* mt2701 domain should be set to 3 */
38 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
39
40 /* mt2712 */
41 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
42 #define F_MMU_EN BIT(0)
43
44 /* SMI COMMON */
45 #define SMI_BUS_SEL 0x220
46 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
47 /* All are MMU0 defaultly. Only specialize mmu1 here. */
48 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
49
50 enum mtk_smi_gen {
51 MTK_SMI_GEN1,
52 MTK_SMI_GEN2
53 };
54
55 struct mtk_smi_common_plat {
56 enum mtk_smi_gen gen;
57 bool has_gals;
58 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
59 };
60
61 struct mtk_smi_larb_gen {
62 int port_in_larb[MTK_LARB_NR_MAX + 1];
63 void (*config_port)(struct device *);
64 unsigned int larb_direct_to_common_mask;
65 bool has_gals;
66 };
67
68 struct mtk_smi {
69 struct device *dev;
70 struct clk *clk_apb, *clk_smi;
71 struct clk *clk_gals0, *clk_gals1;
72 struct clk *clk_async; /*only needed by mt2701*/
73 union {
74 void __iomem *smi_ao_base; /* only for gen1 */
75 void __iomem *base; /* only for gen2 */
76 };
77 const struct mtk_smi_common_plat *plat;
78 };
79
80 struct mtk_smi_larb { /* larb: local arbiter */
81 struct mtk_smi smi;
82 void __iomem *base;
83 struct device *smi_common_dev;
84 const struct mtk_smi_larb_gen *larb_gen;
85 int larbid;
86 u32 *mmu;
87 };
88
mtk_smi_clk_enable(const struct mtk_smi * smi)89 static int mtk_smi_clk_enable(const struct mtk_smi *smi)
90 {
91 int ret;
92
93 ret = clk_prepare_enable(smi->clk_apb);
94 if (ret)
95 return ret;
96
97 ret = clk_prepare_enable(smi->clk_smi);
98 if (ret)
99 goto err_disable_apb;
100
101 ret = clk_prepare_enable(smi->clk_gals0);
102 if (ret)
103 goto err_disable_smi;
104
105 ret = clk_prepare_enable(smi->clk_gals1);
106 if (ret)
107 goto err_disable_gals0;
108
109 return 0;
110
111 err_disable_gals0:
112 clk_disable_unprepare(smi->clk_gals0);
113 err_disable_smi:
114 clk_disable_unprepare(smi->clk_smi);
115 err_disable_apb:
116 clk_disable_unprepare(smi->clk_apb);
117 return ret;
118 }
119
mtk_smi_clk_disable(const struct mtk_smi * smi)120 static void mtk_smi_clk_disable(const struct mtk_smi *smi)
121 {
122 clk_disable_unprepare(smi->clk_gals1);
123 clk_disable_unprepare(smi->clk_gals0);
124 clk_disable_unprepare(smi->clk_smi);
125 clk_disable_unprepare(smi->clk_apb);
126 }
127
mtk_smi_larb_get(struct device * larbdev)128 int mtk_smi_larb_get(struct device *larbdev)
129 {
130 int ret = pm_runtime_get_sync(larbdev);
131
132 return (ret < 0) ? ret : 0;
133 }
134 EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
135
mtk_smi_larb_put(struct device * larbdev)136 void mtk_smi_larb_put(struct device *larbdev)
137 {
138 pm_runtime_put_sync(larbdev);
139 }
140 EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
141
142 static int
mtk_smi_larb_bind(struct device * dev,struct device * master,void * data)143 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
144 {
145 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
146 struct mtk_smi_larb_iommu *larb_mmu = data;
147 unsigned int i;
148
149 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
150 if (dev == larb_mmu[i].dev) {
151 larb->larbid = i;
152 larb->mmu = &larb_mmu[i].mmu;
153 return 0;
154 }
155 }
156 return -ENODEV;
157 }
158
mtk_smi_larb_config_port_gen2_general(struct device * dev)159 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
160 {
161 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
162 u32 reg;
163 int i;
164
165 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
166 return;
167
168 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
169 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
170 reg |= F_MMU_EN;
171 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
172 }
173 }
174
mtk_smi_larb_config_port_mt8173(struct device * dev)175 static void mtk_smi_larb_config_port_mt8173(struct device *dev)
176 {
177 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
178
179 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
180 }
181
mtk_smi_larb_config_port_gen1(struct device * dev)182 static void mtk_smi_larb_config_port_gen1(struct device *dev)
183 {
184 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
185 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
186 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
187 int i, m4u_port_id, larb_port_num;
188 u32 sec_con_val, reg_val;
189
190 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
191 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
192 - larb_gen->port_in_larb[larb->larbid];
193
194 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
195 if (*larb->mmu & BIT(i)) {
196 /* bit[port + 3] controls the virtual or physical */
197 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
198 } else {
199 /* do not need to enable m4u for this port */
200 continue;
201 }
202 reg_val = readl(common->smi_ao_base
203 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
204 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
205 reg_val |= sec_con_val;
206 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
207 writel(reg_val,
208 common->smi_ao_base
209 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
210 }
211 }
212
213 static void
mtk_smi_larb_unbind(struct device * dev,struct device * master,void * data)214 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
215 {
216 /* Do nothing as the iommu is always enabled. */
217 }
218
219 static const struct component_ops mtk_smi_larb_component_ops = {
220 .bind = mtk_smi_larb_bind,
221 .unbind = mtk_smi_larb_unbind,
222 };
223
224 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
225 /* mt8173 do not need the port in larb */
226 .config_port = mtk_smi_larb_config_port_mt8173,
227 };
228
229 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
230 .port_in_larb = {
231 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
232 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
233 },
234 .config_port = mtk_smi_larb_config_port_gen1,
235 };
236
237 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
238 .config_port = mtk_smi_larb_config_port_gen2_general,
239 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
240 };
241
242 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
243 .has_gals = true,
244 .config_port = mtk_smi_larb_config_port_gen2_general,
245 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
246 /* IPU0 | IPU1 | CCU */
247 };
248
249 static const struct of_device_id mtk_smi_larb_of_ids[] = {
250 {
251 .compatible = "mediatek,mt8173-smi-larb",
252 .data = &mtk_smi_larb_mt8173
253 },
254 {
255 .compatible = "mediatek,mt2701-smi-larb",
256 .data = &mtk_smi_larb_mt2701
257 },
258 {
259 .compatible = "mediatek,mt2712-smi-larb",
260 .data = &mtk_smi_larb_mt2712
261 },
262 {
263 .compatible = "mediatek,mt8183-smi-larb",
264 .data = &mtk_smi_larb_mt8183
265 },
266 {}
267 };
268
mtk_smi_larb_probe(struct platform_device * pdev)269 static int mtk_smi_larb_probe(struct platform_device *pdev)
270 {
271 struct mtk_smi_larb *larb;
272 struct resource *res;
273 struct device *dev = &pdev->dev;
274 struct device_node *smi_node;
275 struct platform_device *smi_pdev;
276
277 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
278 if (!larb)
279 return -ENOMEM;
280
281 larb->larb_gen = of_device_get_match_data(dev);
282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283 larb->base = devm_ioremap_resource(dev, res);
284 if (IS_ERR(larb->base))
285 return PTR_ERR(larb->base);
286
287 larb->smi.clk_apb = devm_clk_get(dev, "apb");
288 if (IS_ERR(larb->smi.clk_apb))
289 return PTR_ERR(larb->smi.clk_apb);
290
291 larb->smi.clk_smi = devm_clk_get(dev, "smi");
292 if (IS_ERR(larb->smi.clk_smi))
293 return PTR_ERR(larb->smi.clk_smi);
294
295 if (larb->larb_gen->has_gals) {
296 /* The larbs may still haven't gals even if the SoC support.*/
297 larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
298 if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
299 larb->smi.clk_gals0 = NULL;
300 else if (IS_ERR(larb->smi.clk_gals0))
301 return PTR_ERR(larb->smi.clk_gals0);
302 }
303 larb->smi.dev = dev;
304
305 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
306 if (!smi_node)
307 return -EINVAL;
308
309 smi_pdev = of_find_device_by_node(smi_node);
310 of_node_put(smi_node);
311 if (smi_pdev) {
312 if (!platform_get_drvdata(smi_pdev))
313 return -EPROBE_DEFER;
314 larb->smi_common_dev = &smi_pdev->dev;
315 } else {
316 dev_err(dev, "Failed to get the smi_common device\n");
317 return -EINVAL;
318 }
319
320 pm_runtime_enable(dev);
321 platform_set_drvdata(pdev, larb);
322 return component_add(dev, &mtk_smi_larb_component_ops);
323 }
324
mtk_smi_larb_remove(struct platform_device * pdev)325 static int mtk_smi_larb_remove(struct platform_device *pdev)
326 {
327 pm_runtime_disable(&pdev->dev);
328 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
329 return 0;
330 }
331
mtk_smi_larb_resume(struct device * dev)332 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
333 {
334 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
335 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
336 int ret;
337
338 /* Power on smi-common. */
339 ret = pm_runtime_get_sync(larb->smi_common_dev);
340 if (ret < 0) {
341 dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
342 return ret;
343 }
344
345 ret = mtk_smi_clk_enable(&larb->smi);
346 if (ret < 0) {
347 dev_err(dev, "Failed to enable clock(%d).\n", ret);
348 pm_runtime_put_sync(larb->smi_common_dev);
349 return ret;
350 }
351
352 /* Configure the basic setting for this larb */
353 larb_gen->config_port(dev);
354
355 return 0;
356 }
357
mtk_smi_larb_suspend(struct device * dev)358 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
359 {
360 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
361
362 mtk_smi_clk_disable(&larb->smi);
363 pm_runtime_put_sync(larb->smi_common_dev);
364 return 0;
365 }
366
367 static const struct dev_pm_ops smi_larb_pm_ops = {
368 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
369 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
370 pm_runtime_force_resume)
371 };
372
373 static struct platform_driver mtk_smi_larb_driver = {
374 .probe = mtk_smi_larb_probe,
375 .remove = mtk_smi_larb_remove,
376 .driver = {
377 .name = "mtk-smi-larb",
378 .of_match_table = mtk_smi_larb_of_ids,
379 .pm = &smi_larb_pm_ops,
380 }
381 };
382
383 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
384 .gen = MTK_SMI_GEN1,
385 };
386
387 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
388 .gen = MTK_SMI_GEN2,
389 };
390
391 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
392 .gen = MTK_SMI_GEN2,
393 .has_gals = true,
394 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
395 F_MMU1_LARB(7),
396 };
397
398 static const struct of_device_id mtk_smi_common_of_ids[] = {
399 {
400 .compatible = "mediatek,mt8173-smi-common",
401 .data = &mtk_smi_common_gen2,
402 },
403 {
404 .compatible = "mediatek,mt2701-smi-common",
405 .data = &mtk_smi_common_gen1,
406 },
407 {
408 .compatible = "mediatek,mt2712-smi-common",
409 .data = &mtk_smi_common_gen2,
410 },
411 {
412 .compatible = "mediatek,mt8183-smi-common",
413 .data = &mtk_smi_common_mt8183,
414 },
415 {}
416 };
417
mtk_smi_common_probe(struct platform_device * pdev)418 static int mtk_smi_common_probe(struct platform_device *pdev)
419 {
420 struct device *dev = &pdev->dev;
421 struct mtk_smi *common;
422 struct resource *res;
423 int ret;
424
425 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
426 if (!common)
427 return -ENOMEM;
428 common->dev = dev;
429 common->plat = of_device_get_match_data(dev);
430
431 common->clk_apb = devm_clk_get(dev, "apb");
432 if (IS_ERR(common->clk_apb))
433 return PTR_ERR(common->clk_apb);
434
435 common->clk_smi = devm_clk_get(dev, "smi");
436 if (IS_ERR(common->clk_smi))
437 return PTR_ERR(common->clk_smi);
438
439 if (common->plat->has_gals) {
440 common->clk_gals0 = devm_clk_get(dev, "gals0");
441 if (IS_ERR(common->clk_gals0))
442 return PTR_ERR(common->clk_gals0);
443
444 common->clk_gals1 = devm_clk_get(dev, "gals1");
445 if (IS_ERR(common->clk_gals1))
446 return PTR_ERR(common->clk_gals1);
447 }
448
449 /*
450 * for mtk smi gen 1, we need to get the ao(always on) base to config
451 * m4u port, and we need to enable the aync clock for transform the smi
452 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
453 * base.
454 */
455 if (common->plat->gen == MTK_SMI_GEN1) {
456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 common->smi_ao_base = devm_ioremap_resource(dev, res);
458 if (IS_ERR(common->smi_ao_base))
459 return PTR_ERR(common->smi_ao_base);
460
461 common->clk_async = devm_clk_get(dev, "async");
462 if (IS_ERR(common->clk_async))
463 return PTR_ERR(common->clk_async);
464
465 ret = clk_prepare_enable(common->clk_async);
466 if (ret)
467 return ret;
468 } else {
469 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
470 common->base = devm_ioremap_resource(dev, res);
471 if (IS_ERR(common->base))
472 return PTR_ERR(common->base);
473 }
474 pm_runtime_enable(dev);
475 platform_set_drvdata(pdev, common);
476 return 0;
477 }
478
mtk_smi_common_remove(struct platform_device * pdev)479 static int mtk_smi_common_remove(struct platform_device *pdev)
480 {
481 pm_runtime_disable(&pdev->dev);
482 return 0;
483 }
484
mtk_smi_common_resume(struct device * dev)485 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
486 {
487 struct mtk_smi *common = dev_get_drvdata(dev);
488 u32 bus_sel = common->plat->bus_sel;
489 int ret;
490
491 ret = mtk_smi_clk_enable(common);
492 if (ret) {
493 dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
494 return ret;
495 }
496
497 if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
498 writel(bus_sel, common->base + SMI_BUS_SEL);
499 return 0;
500 }
501
mtk_smi_common_suspend(struct device * dev)502 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
503 {
504 struct mtk_smi *common = dev_get_drvdata(dev);
505
506 mtk_smi_clk_disable(common);
507 return 0;
508 }
509
510 static const struct dev_pm_ops smi_common_pm_ops = {
511 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
512 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
513 pm_runtime_force_resume)
514 };
515
516 static struct platform_driver mtk_smi_common_driver = {
517 .probe = mtk_smi_common_probe,
518 .remove = mtk_smi_common_remove,
519 .driver = {
520 .name = "mtk-smi-common",
521 .of_match_table = mtk_smi_common_of_ids,
522 .pm = &smi_common_pm_ops,
523 }
524 };
525
mtk_smi_init(void)526 static int __init mtk_smi_init(void)
527 {
528 int ret;
529
530 ret = platform_driver_register(&mtk_smi_common_driver);
531 if (ret != 0) {
532 pr_err("Failed to register SMI driver\n");
533 return ret;
534 }
535
536 ret = platform_driver_register(&mtk_smi_larb_driver);
537 if (ret != 0) {
538 pr_err("Failed to register SMI-LARB driver\n");
539 goto err_unreg_smi;
540 }
541 return ret;
542
543 err_unreg_smi:
544 platform_driver_unregister(&mtk_smi_common_driver);
545 return ret;
546 }
547
548 module_init(mtk_smi_init);
549