1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #include <linux/module.h>
8 #include <linux/moduleparam.h>
9 #include <linux/kernel.h>
10 #include <linux/device.h>
11 #include <linux/fs.h>
12 #include <linux/errno.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/pci.h>
16 #include <linux/poll.h>
17 #include <linux/ioctl.h>
18 #include <linux/cdev.h>
19 #include <linux/sched.h>
20 #include <linux/uuid.h>
21 #include <linux/compat.h>
22 #include <linux/jiffies.h>
23 #include <linux/interrupt.h>
24
25 #include <linux/pm_domain.h>
26 #include <linux/pm_runtime.h>
27
28 #include <linux/mei.h>
29
30 #include "mei_dev.h"
31 #include "client.h"
32 #include "hw-me-regs.h"
33 #include "hw-me.h"
34
35 /* mei_pci_tbl - PCI Device ID Table */
36 static const struct pci_device_id mei_me_pci_tbl[] = {
37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
48
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
58
59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
63
64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
77
78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
86
87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
88
89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
90
91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
93
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
101 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
102 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)},
108
109 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
110 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
111
112 /* required last entry */
113 {0, }
114 };
115
116 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
117
118 #ifdef CONFIG_PM
119 static inline void mei_me_set_pm_domain(struct mei_device *dev);
120 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
121 #else
mei_me_set_pm_domain(struct mei_device * dev)122 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)123 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
124 #endif /* CONFIG_PM */
125
126 /**
127 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
128 *
129 * @pdev: PCI device structure
130 * @cfg: per generation config
131 *
132 * Return: true if ME Interface is valid, false otherwise
133 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)134 static bool mei_me_quirk_probe(struct pci_dev *pdev,
135 const struct mei_cfg *cfg)
136 {
137 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
138 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
139 return false;
140 }
141
142 return true;
143 }
144
145 /**
146 * mei_me_probe - Device Initialization Routine
147 *
148 * @pdev: PCI device structure
149 * @ent: entry in kcs_pci_tbl
150 *
151 * Return: 0 on success, <0 on failure.
152 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)153 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
154 {
155 const struct mei_cfg *cfg;
156 struct mei_device *dev;
157 struct mei_me_hw *hw;
158 unsigned int irqflags;
159 int err;
160
161 cfg = mei_me_get_cfg(ent->driver_data);
162 if (!cfg)
163 return -ENODEV;
164
165 if (!mei_me_quirk_probe(pdev, cfg))
166 return -ENODEV;
167
168 /* enable pci dev */
169 err = pcim_enable_device(pdev);
170 if (err) {
171 dev_err(&pdev->dev, "failed to enable pci device.\n");
172 goto end;
173 }
174 /* set PCI host mastering */
175 pci_set_master(pdev);
176 /* pci request regions and mapping IO device memory for mei driver */
177 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
178 if (err) {
179 dev_err(&pdev->dev, "failed to get pci regions.\n");
180 goto end;
181 }
182
183 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
184 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
185
186 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
187 if (err)
188 err = dma_set_coherent_mask(&pdev->dev,
189 DMA_BIT_MASK(32));
190 }
191 if (err) {
192 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
193 goto end;
194 }
195
196 /* allocates and initializes the mei dev structure */
197 dev = mei_me_dev_init(pdev, cfg);
198 if (!dev) {
199 err = -ENOMEM;
200 goto end;
201 }
202 hw = to_me_hw(dev);
203 hw->mem_addr = pcim_iomap_table(pdev)[0];
204
205 pci_enable_msi(pdev);
206
207 /* request and enable interrupt */
208 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
209
210 err = request_threaded_irq(pdev->irq,
211 mei_me_irq_quick_handler,
212 mei_me_irq_thread_handler,
213 irqflags, KBUILD_MODNAME, dev);
214 if (err) {
215 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
216 pdev->irq);
217 goto end;
218 }
219
220 if (mei_start(dev)) {
221 dev_err(&pdev->dev, "init hw failure.\n");
222 err = -ENODEV;
223 goto release_irq;
224 }
225
226 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
227 pm_runtime_use_autosuspend(&pdev->dev);
228
229 err = mei_register(dev, &pdev->dev);
230 if (err)
231 goto stop;
232
233 pci_set_drvdata(pdev, dev);
234
235 /*
236 * MEI requires to resume from runtime suspend mode
237 * in order to perform link reset flow upon system suspend.
238 */
239 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
240
241 /*
242 * ME maps runtime suspend/resume to D0i states,
243 * hence we need to go around native PCI runtime service which
244 * eventually brings the device into D3cold/hot state,
245 * but the mei device cannot wake up from D3 unlike from D0i3.
246 * To get around the PCI device native runtime pm,
247 * ME uses runtime pm domain handlers which take precedence
248 * over the driver's pm handlers.
249 */
250 mei_me_set_pm_domain(dev);
251
252 if (mei_pg_is_enabled(dev)) {
253 pm_runtime_put_noidle(&pdev->dev);
254 if (hw->d0i3_supported)
255 pm_runtime_allow(&pdev->dev);
256 }
257
258 dev_dbg(&pdev->dev, "initialization successful.\n");
259
260 return 0;
261
262 stop:
263 mei_stop(dev);
264 release_irq:
265 mei_cancel_work(dev);
266 mei_disable_interrupts(dev);
267 free_irq(pdev->irq, dev);
268 end:
269 dev_err(&pdev->dev, "initialization failed.\n");
270 return err;
271 }
272
273 /**
274 * mei_me_shutdown - Device Removal Routine
275 *
276 * @pdev: PCI device structure
277 *
278 * mei_me_shutdown is called from the reboot notifier
279 * it's a simplified version of remove so we go down
280 * faster.
281 */
mei_me_shutdown(struct pci_dev * pdev)282 static void mei_me_shutdown(struct pci_dev *pdev)
283 {
284 struct mei_device *dev;
285
286 dev = pci_get_drvdata(pdev);
287 if (!dev)
288 return;
289
290 dev_dbg(&pdev->dev, "shutdown\n");
291 mei_stop(dev);
292
293 mei_me_unset_pm_domain(dev);
294
295 mei_disable_interrupts(dev);
296 free_irq(pdev->irq, dev);
297 }
298
299 /**
300 * mei_me_remove - Device Removal Routine
301 *
302 * @pdev: PCI device structure
303 *
304 * mei_me_remove is called by the PCI subsystem to alert the driver
305 * that it should release a PCI device.
306 */
mei_me_remove(struct pci_dev * pdev)307 static void mei_me_remove(struct pci_dev *pdev)
308 {
309 struct mei_device *dev;
310
311 dev = pci_get_drvdata(pdev);
312 if (!dev)
313 return;
314
315 if (mei_pg_is_enabled(dev))
316 pm_runtime_get_noresume(&pdev->dev);
317
318 dev_dbg(&pdev->dev, "stop\n");
319 mei_stop(dev);
320
321 mei_me_unset_pm_domain(dev);
322
323 mei_disable_interrupts(dev);
324
325 free_irq(pdev->irq, dev);
326
327 mei_deregister(dev);
328 }
329
330 #ifdef CONFIG_PM_SLEEP
mei_me_pci_suspend(struct device * device)331 static int mei_me_pci_suspend(struct device *device)
332 {
333 struct pci_dev *pdev = to_pci_dev(device);
334 struct mei_device *dev = pci_get_drvdata(pdev);
335
336 if (!dev)
337 return -ENODEV;
338
339 dev_dbg(&pdev->dev, "suspend\n");
340
341 mei_stop(dev);
342
343 mei_disable_interrupts(dev);
344
345 free_irq(pdev->irq, dev);
346 pci_disable_msi(pdev);
347
348 return 0;
349 }
350
mei_me_pci_resume(struct device * device)351 static int mei_me_pci_resume(struct device *device)
352 {
353 struct pci_dev *pdev = to_pci_dev(device);
354 struct mei_device *dev;
355 unsigned int irqflags;
356 int err;
357
358 dev = pci_get_drvdata(pdev);
359 if (!dev)
360 return -ENODEV;
361
362 pci_enable_msi(pdev);
363
364 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
365
366 /* request and enable interrupt */
367 err = request_threaded_irq(pdev->irq,
368 mei_me_irq_quick_handler,
369 mei_me_irq_thread_handler,
370 irqflags, KBUILD_MODNAME, dev);
371
372 if (err) {
373 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
374 pdev->irq);
375 return err;
376 }
377
378 err = mei_restart(dev);
379 if (err)
380 return err;
381
382 /* Start timer if stopped in suspend */
383 schedule_delayed_work(&dev->timer_work, HZ);
384
385 return 0;
386 }
387 #endif /* CONFIG_PM_SLEEP */
388
389 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)390 static int mei_me_pm_runtime_idle(struct device *device)
391 {
392 struct mei_device *dev;
393
394 dev_dbg(device, "rpm: me: runtime_idle\n");
395
396 dev = dev_get_drvdata(device);
397 if (!dev)
398 return -ENODEV;
399 if (mei_write_is_idle(dev))
400 pm_runtime_autosuspend(device);
401
402 return -EBUSY;
403 }
404
mei_me_pm_runtime_suspend(struct device * device)405 static int mei_me_pm_runtime_suspend(struct device *device)
406 {
407 struct mei_device *dev;
408 int ret;
409
410 dev_dbg(device, "rpm: me: runtime suspend\n");
411
412 dev = dev_get_drvdata(device);
413 if (!dev)
414 return -ENODEV;
415
416 mutex_lock(&dev->device_lock);
417
418 if (mei_write_is_idle(dev))
419 ret = mei_me_pg_enter_sync(dev);
420 else
421 ret = -EAGAIN;
422
423 mutex_unlock(&dev->device_lock);
424
425 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
426
427 if (ret && ret != -EAGAIN)
428 schedule_work(&dev->reset_work);
429
430 return ret;
431 }
432
mei_me_pm_runtime_resume(struct device * device)433 static int mei_me_pm_runtime_resume(struct device *device)
434 {
435 struct mei_device *dev;
436 int ret;
437
438 dev_dbg(device, "rpm: me: runtime resume\n");
439
440 dev = dev_get_drvdata(device);
441 if (!dev)
442 return -ENODEV;
443
444 mutex_lock(&dev->device_lock);
445
446 ret = mei_me_pg_exit_sync(dev);
447
448 mutex_unlock(&dev->device_lock);
449
450 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
451
452 if (ret)
453 schedule_work(&dev->reset_work);
454
455 return ret;
456 }
457
458 /**
459 * mei_me_set_pm_domain - fill and set pm domain structure for device
460 *
461 * @dev: mei_device
462 */
mei_me_set_pm_domain(struct mei_device * dev)463 static inline void mei_me_set_pm_domain(struct mei_device *dev)
464 {
465 struct pci_dev *pdev = to_pci_dev(dev->dev);
466
467 if (pdev->dev.bus && pdev->dev.bus->pm) {
468 dev->pg_domain.ops = *pdev->dev.bus->pm;
469
470 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
471 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
472 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
473
474 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
475 }
476 }
477
478 /**
479 * mei_me_unset_pm_domain - clean pm domain structure for device
480 *
481 * @dev: mei_device
482 */
mei_me_unset_pm_domain(struct mei_device * dev)483 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
484 {
485 /* stop using pm callbacks if any */
486 dev_pm_domain_set(dev->dev, NULL);
487 }
488
489 static const struct dev_pm_ops mei_me_pm_ops = {
490 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
491 mei_me_pci_resume)
492 SET_RUNTIME_PM_OPS(
493 mei_me_pm_runtime_suspend,
494 mei_me_pm_runtime_resume,
495 mei_me_pm_runtime_idle)
496 };
497
498 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
499 #else
500 #define MEI_ME_PM_OPS NULL
501 #endif /* CONFIG_PM */
502 /*
503 * PCI driver structure
504 */
505 static struct pci_driver mei_me_driver = {
506 .name = KBUILD_MODNAME,
507 .id_table = mei_me_pci_tbl,
508 .probe = mei_me_probe,
509 .remove = mei_me_remove,
510 .shutdown = mei_me_shutdown,
511 .driver.pm = MEI_ME_PM_OPS,
512 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
513 };
514
515 module_pci_driver(mei_me_driver);
516
517 MODULE_AUTHOR("Intel Corporation");
518 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
519 MODULE_LICENSE("GPL v2");
520