1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
17 *
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
19 *
20 * This code is GPL
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <asm/io.h>
28 #include <asm/byteorder.h>
29
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
35 #include <linux/of.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_RETRIES 3
46
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
51
52 /*
53 * Status Register bit description. Used by flash devices that don't
54 * support DQ polling (e.g. HyperFlash)
55 */
56 #define CFI_SR_DRB BIT(7)
57 #define CFI_SR_ESB BIT(5)
58 #define CFI_SR_PSB BIT(4)
59 #define CFI_SR_WBASB BIT(3)
60 #define CFI_SR_SLSB BIT(1)
61
62 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
64 #if !FORCE_WORD_WRITE
65 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
66 #endif
67 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
68 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
69 static void cfi_amdstd_sync (struct mtd_info *);
70 static int cfi_amdstd_suspend (struct mtd_info *);
71 static void cfi_amdstd_resume (struct mtd_info *);
72 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
73 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
74 size_t *, struct otp_info *);
75 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
76 size_t *, struct otp_info *);
77 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
78 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
79 size_t *, u_char *);
80 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
81 size_t *, u_char *);
82 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
83 size_t *, u_char *);
84 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
85
86 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
87 size_t *retlen, const u_char *buf);
88
89 static void cfi_amdstd_destroy(struct mtd_info *);
90
91 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
92 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
93
94 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
95 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
96 #include "fwh_lock.h"
97
98 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
99 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
100
101 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
102 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
103 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
104
105 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
106 .probe = NULL, /* Not usable directly */
107 .destroy = cfi_amdstd_destroy,
108 .name = "cfi_cmdset_0002",
109 .module = THIS_MODULE
110 };
111
112 /*
113 * Use status register to poll for Erase/write completion when DQ is not
114 * supported. This is indicated by Bit[1:0] of SoftwareFeatures field in
115 * CFI Primary Vendor-Specific Extended Query table 1.5
116 */
cfi_use_status_reg(struct cfi_private * cfi)117 static int cfi_use_status_reg(struct cfi_private *cfi)
118 {
119 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
120 u8 poll_mask = CFI_POLL_STATUS_REG | CFI_POLL_DQ;
121
122 return extp->MinorVersion >= '5' &&
123 (extp->SoftwareFeatures & poll_mask) == CFI_POLL_STATUS_REG;
124 }
125
cfi_check_err_status(struct map_info * map,struct flchip * chip,unsigned long adr)126 static int cfi_check_err_status(struct map_info *map, struct flchip *chip,
127 unsigned long adr)
128 {
129 struct cfi_private *cfi = map->fldrv_priv;
130 map_word status;
131
132 if (!cfi_use_status_reg(cfi))
133 return 0;
134
135 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
136 cfi->device_type, NULL);
137 status = map_read(map, adr);
138
139 /* The error bits are invalid while the chip's busy */
140 if (!map_word_bitsset(map, status, CMD(CFI_SR_DRB)))
141 return 0;
142
143 if (map_word_bitsset(map, status, CMD(0x3a))) {
144 unsigned long chipstatus = MERGESTATUS(status);
145
146 if (chipstatus & CFI_SR_ESB)
147 pr_err("%s erase operation failed, status %lx\n",
148 map->name, chipstatus);
149 if (chipstatus & CFI_SR_PSB)
150 pr_err("%s program operation failed, status %lx\n",
151 map->name, chipstatus);
152 if (chipstatus & CFI_SR_WBASB)
153 pr_err("%s buffer program command aborted, status %lx\n",
154 map->name, chipstatus);
155 if (chipstatus & CFI_SR_SLSB)
156 pr_err("%s sector write protected, status %lx\n",
157 map->name, chipstatus);
158
159 /* Erase/Program status bits are set on the operation failure */
160 if (chipstatus & (CFI_SR_ESB | CFI_SR_PSB))
161 return 1;
162 }
163 return 0;
164 }
165
166 /* #define DEBUG_CFI_FEATURES */
167
168
169 #ifdef DEBUG_CFI_FEATURES
cfi_tell_features(struct cfi_pri_amdstd * extp)170 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
171 {
172 const char* erase_suspend[3] = {
173 "Not supported", "Read only", "Read/write"
174 };
175 const char* top_bottom[6] = {
176 "No WP", "8x8KiB sectors at top & bottom, no WP",
177 "Bottom boot", "Top boot",
178 "Uniform, Bottom WP", "Uniform, Top WP"
179 };
180
181 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
182 printk(" Address sensitive unlock: %s\n",
183 (extp->SiliconRevision & 1) ? "Not required" : "Required");
184
185 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
186 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
187 else
188 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
189
190 if (extp->BlkProt == 0)
191 printk(" Block protection: Not supported\n");
192 else
193 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
194
195
196 printk(" Temporary block unprotect: %s\n",
197 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
198 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
199 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
200 printk(" Burst mode: %s\n",
201 extp->BurstMode ? "Supported" : "Not supported");
202 if (extp->PageMode == 0)
203 printk(" Page mode: Not supported\n");
204 else
205 printk(" Page mode: %d word page\n", extp->PageMode << 2);
206
207 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
208 extp->VppMin >> 4, extp->VppMin & 0xf);
209 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
210 extp->VppMax >> 4, extp->VppMax & 0xf);
211
212 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
213 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
214 else
215 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
216 }
217 #endif
218
219 #ifdef AMD_BOOTLOC_BUG
220 /* Wheee. Bring me the head of someone at AMD. */
fixup_amd_bootblock(struct mtd_info * mtd)221 static void fixup_amd_bootblock(struct mtd_info *mtd)
222 {
223 struct map_info *map = mtd->priv;
224 struct cfi_private *cfi = map->fldrv_priv;
225 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
226 __u8 major = extp->MajorVersion;
227 __u8 minor = extp->MinorVersion;
228
229 if (((major << 8) | minor) < 0x3131) {
230 /* CFI version 1.0 => don't trust bootloc */
231
232 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
233 map->name, cfi->mfr, cfi->id);
234
235 /* AFAICS all 29LV400 with a bottom boot block have a device ID
236 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
237 * These were badly detected as they have the 0x80 bit set
238 * so treat them as a special case.
239 */
240 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
241
242 /* Macronix added CFI to their 2nd generation
243 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
244 * Fujitsu, Spansion, EON, ESI and older Macronix)
245 * has CFI.
246 *
247 * Therefore also check the manufacturer.
248 * This reduces the risk of false detection due to
249 * the 8-bit device ID.
250 */
251 (cfi->mfr == CFI_MFR_MACRONIX)) {
252 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
253 " detected\n", map->name);
254 extp->TopBottom = 2; /* bottom boot */
255 } else
256 if (cfi->id & 0x80) {
257 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
258 extp->TopBottom = 3; /* top boot */
259 } else {
260 extp->TopBottom = 2; /* bottom boot */
261 }
262
263 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
264 " deduced %s from Device ID\n", map->name, major, minor,
265 extp->TopBottom == 2 ? "bottom" : "top");
266 }
267 }
268 #endif
269
270 #if !FORCE_WORD_WRITE
fixup_use_write_buffers(struct mtd_info * mtd)271 static void fixup_use_write_buffers(struct mtd_info *mtd)
272 {
273 struct map_info *map = mtd->priv;
274 struct cfi_private *cfi = map->fldrv_priv;
275 if (cfi->cfiq->BufWriteTimeoutTyp) {
276 pr_debug("Using buffer write method\n");
277 mtd->_write = cfi_amdstd_write_buffers;
278 }
279 }
280 #endif /* !FORCE_WORD_WRITE */
281
282 /* Atmel chips don't use the same PRI format as AMD chips */
fixup_convert_atmel_pri(struct mtd_info * mtd)283 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
284 {
285 struct map_info *map = mtd->priv;
286 struct cfi_private *cfi = map->fldrv_priv;
287 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
288 struct cfi_pri_atmel atmel_pri;
289
290 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
291 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
292
293 if (atmel_pri.Features & 0x02)
294 extp->EraseSuspend = 2;
295
296 /* Some chips got it backwards... */
297 if (cfi->id == AT49BV6416) {
298 if (atmel_pri.BottomBoot)
299 extp->TopBottom = 3;
300 else
301 extp->TopBottom = 2;
302 } else {
303 if (atmel_pri.BottomBoot)
304 extp->TopBottom = 2;
305 else
306 extp->TopBottom = 3;
307 }
308
309 /* burst write mode not supported */
310 cfi->cfiq->BufWriteTimeoutTyp = 0;
311 cfi->cfiq->BufWriteTimeoutMax = 0;
312 }
313
fixup_use_secsi(struct mtd_info * mtd)314 static void fixup_use_secsi(struct mtd_info *mtd)
315 {
316 /* Setup for chips with a secsi area */
317 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
318 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
319 }
320
fixup_use_erase_chip(struct mtd_info * mtd)321 static void fixup_use_erase_chip(struct mtd_info *mtd)
322 {
323 struct map_info *map = mtd->priv;
324 struct cfi_private *cfi = map->fldrv_priv;
325 if ((cfi->cfiq->NumEraseRegions == 1) &&
326 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
327 mtd->_erase = cfi_amdstd_erase_chip;
328 }
329
330 }
331
332 /*
333 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
334 * locked by default.
335 */
fixup_use_atmel_lock(struct mtd_info * mtd)336 static void fixup_use_atmel_lock(struct mtd_info *mtd)
337 {
338 mtd->_lock = cfi_atmel_lock;
339 mtd->_unlock = cfi_atmel_unlock;
340 mtd->flags |= MTD_POWERUP_LOCK;
341 }
342
fixup_old_sst_eraseregion(struct mtd_info * mtd)343 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
344 {
345 struct map_info *map = mtd->priv;
346 struct cfi_private *cfi = map->fldrv_priv;
347
348 /*
349 * These flashes report two separate eraseblock regions based on the
350 * sector_erase-size and block_erase-size, although they both operate on the
351 * same memory. This is not allowed according to CFI, so we just pick the
352 * sector_erase-size.
353 */
354 cfi->cfiq->NumEraseRegions = 1;
355 }
356
fixup_sst39vf(struct mtd_info * mtd)357 static void fixup_sst39vf(struct mtd_info *mtd)
358 {
359 struct map_info *map = mtd->priv;
360 struct cfi_private *cfi = map->fldrv_priv;
361
362 fixup_old_sst_eraseregion(mtd);
363
364 cfi->addr_unlock1 = 0x5555;
365 cfi->addr_unlock2 = 0x2AAA;
366 }
367
fixup_sst39vf_rev_b(struct mtd_info * mtd)368 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
369 {
370 struct map_info *map = mtd->priv;
371 struct cfi_private *cfi = map->fldrv_priv;
372
373 fixup_old_sst_eraseregion(mtd);
374
375 cfi->addr_unlock1 = 0x555;
376 cfi->addr_unlock2 = 0x2AA;
377
378 cfi->sector_erase_cmd = CMD(0x50);
379 }
380
fixup_sst38vf640x_sectorsize(struct mtd_info * mtd)381 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
382 {
383 struct map_info *map = mtd->priv;
384 struct cfi_private *cfi = map->fldrv_priv;
385
386 fixup_sst39vf_rev_b(mtd);
387
388 /*
389 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
390 * it should report a size of 8KBytes (0x0020*256).
391 */
392 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
393 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
394 mtd->name);
395 }
396
fixup_s29gl064n_sectors(struct mtd_info * mtd)397 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
398 {
399 struct map_info *map = mtd->priv;
400 struct cfi_private *cfi = map->fldrv_priv;
401
402 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
403 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
404 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
405 mtd->name);
406 }
407 }
408
fixup_s29gl032n_sectors(struct mtd_info * mtd)409 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
410 {
411 struct map_info *map = mtd->priv;
412 struct cfi_private *cfi = map->fldrv_priv;
413
414 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
415 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
416 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
417 mtd->name);
418 }
419 }
420
fixup_s29ns512p_sectors(struct mtd_info * mtd)421 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
422 {
423 struct map_info *map = mtd->priv;
424 struct cfi_private *cfi = map->fldrv_priv;
425
426 /*
427 * S29NS512P flash uses more than 8bits to report number of sectors,
428 * which is not permitted by CFI.
429 */
430 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
431 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
432 mtd->name);
433 }
434
435 /* Used to fix CFI-Tables of chips without Extended Query Tables */
436 static struct cfi_fixup cfi_nopri_fixup_table[] = {
437 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
438 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
439 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
440 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
441 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
442 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
443 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
444 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
445 { 0, 0, NULL }
446 };
447
448 static struct cfi_fixup cfi_fixup_table[] = {
449 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
450 #ifdef AMD_BOOTLOC_BUG
451 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
452 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
453 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
454 #endif
455 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
456 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
457 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
458 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
459 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
460 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
461 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
462 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
463 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
464 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
465 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
466 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
467 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
468 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
469 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
470 #if !FORCE_WORD_WRITE
471 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
472 #endif
473 { 0, 0, NULL }
474 };
475 static struct cfi_fixup jedec_fixup_table[] = {
476 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
477 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
478 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
479 { 0, 0, NULL }
480 };
481
482 static struct cfi_fixup fixup_table[] = {
483 /* The CFI vendor ids and the JEDEC vendor IDs appear
484 * to be common. It is like the devices id's are as
485 * well. This table is to pick all cases where
486 * we know that is the case.
487 */
488 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
489 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
490 { 0, 0, NULL }
491 };
492
493
cfi_fixup_major_minor(struct cfi_private * cfi,struct cfi_pri_amdstd * extp)494 static void cfi_fixup_major_minor(struct cfi_private *cfi,
495 struct cfi_pri_amdstd *extp)
496 {
497 if (cfi->mfr == CFI_MFR_SAMSUNG) {
498 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
499 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
500 /*
501 * Samsung K8P2815UQB and K8D6x16UxM chips
502 * report major=0 / minor=0.
503 * K8D3x16UxC chips report major=3 / minor=3.
504 */
505 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
506 " Extended Query version to 1.%c\n",
507 extp->MinorVersion);
508 extp->MajorVersion = '1';
509 }
510 }
511
512 /*
513 * SST 38VF640x chips report major=0xFF / minor=0xFF.
514 */
515 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
516 extp->MajorVersion = '1';
517 extp->MinorVersion = '0';
518 }
519 }
520
is_m29ew(struct cfi_private * cfi)521 static int is_m29ew(struct cfi_private *cfi)
522 {
523 if (cfi->mfr == CFI_MFR_INTEL &&
524 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
525 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
526 return 1;
527 return 0;
528 }
529
530 /*
531 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
532 * Some revisions of the M29EW suffer from erase suspend hang ups. In
533 * particular, it can occur when the sequence
534 * Erase Confirm -> Suspend -> Program -> Resume
535 * causes a lockup due to internal timing issues. The consequence is that the
536 * erase cannot be resumed without inserting a dummy command after programming
537 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
538 * that writes an F0 command code before the RESUME command.
539 */
cfi_fixup_m29ew_erase_suspend(struct map_info * map,unsigned long adr)540 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
541 unsigned long adr)
542 {
543 struct cfi_private *cfi = map->fldrv_priv;
544 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
545 if (is_m29ew(cfi))
546 map_write(map, CMD(0xF0), adr);
547 }
548
549 /*
550 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
551 *
552 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
553 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
554 * command is issued after an ERASE RESUME operation without waiting for a
555 * minimum delay. The result is that once the ERASE seems to be completed
556 * (no bits are toggling), the contents of the Flash memory block on which
557 * the erase was ongoing could be inconsistent with the expected values
558 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
559 * values), causing a consequent failure of the ERASE operation.
560 * The occurrence of this issue could be high, especially when file system
561 * operations on the Flash are intensive. As a result, it is recommended
562 * that a patch be applied. Intensive file system operations can cause many
563 * calls to the garbage routine to free Flash space (also by erasing physical
564 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
565 * commands can occur. The problem disappears when a delay is inserted after
566 * the RESUME command by using the udelay() function available in Linux.
567 * The DELAY value must be tuned based on the customer's platform.
568 * The maximum value that fixes the problem in all cases is 500us.
569 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
570 * in most cases.
571 * We have chosen 500µs because this latency is acceptable.
572 */
cfi_fixup_m29ew_delay_after_resume(struct cfi_private * cfi)573 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
574 {
575 /*
576 * Resolving the Delay After Resume Issue see Micron TN-13-07
577 * Worst case delay must be 500µs but 30-50µs should be ok as well
578 */
579 if (is_m29ew(cfi))
580 cfi_udelay(500);
581 }
582
cfi_cmdset_0002(struct map_info * map,int primary)583 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
584 {
585 struct cfi_private *cfi = map->fldrv_priv;
586 struct device_node __maybe_unused *np = map->device_node;
587 struct mtd_info *mtd;
588 int i;
589
590 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
591 if (!mtd)
592 return NULL;
593 mtd->priv = map;
594 mtd->type = MTD_NORFLASH;
595
596 /* Fill in the default mtd operations */
597 mtd->_erase = cfi_amdstd_erase_varsize;
598 mtd->_write = cfi_amdstd_write_words;
599 mtd->_read = cfi_amdstd_read;
600 mtd->_sync = cfi_amdstd_sync;
601 mtd->_suspend = cfi_amdstd_suspend;
602 mtd->_resume = cfi_amdstd_resume;
603 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
604 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
605 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
606 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
607 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
608 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
609 mtd->flags = MTD_CAP_NORFLASH;
610 mtd->name = map->name;
611 mtd->writesize = 1;
612 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
613
614 pr_debug("MTD %s(): write buffer size %d\n", __func__,
615 mtd->writebufsize);
616
617 mtd->_panic_write = cfi_amdstd_panic_write;
618 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
619
620 if (cfi->cfi_mode==CFI_MODE_CFI){
621 unsigned char bootloc;
622 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
623 struct cfi_pri_amdstd *extp;
624
625 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
626 if (extp) {
627 /*
628 * It's a real CFI chip, not one for which the probe
629 * routine faked a CFI structure.
630 */
631 cfi_fixup_major_minor(cfi, extp);
632
633 /*
634 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
635 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
636 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
637 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
638 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
639 */
640 if (extp->MajorVersion != '1' ||
641 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
642 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
643 "version %c.%c (%#02x/%#02x).\n",
644 extp->MajorVersion, extp->MinorVersion,
645 extp->MajorVersion, extp->MinorVersion);
646 kfree(extp);
647 kfree(mtd);
648 return NULL;
649 }
650
651 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
652 extp->MajorVersion, extp->MinorVersion);
653
654 /* Install our own private info structure */
655 cfi->cmdset_priv = extp;
656
657 /* Apply cfi device specific fixups */
658 cfi_fixup(mtd, cfi_fixup_table);
659
660 #ifdef DEBUG_CFI_FEATURES
661 /* Tell the user about it in lots of lovely detail */
662 cfi_tell_features(extp);
663 #endif
664
665 #ifdef CONFIG_OF
666 if (np && of_property_read_bool(
667 np, "use-advanced-sector-protection")
668 && extp->BlkProtUnprot == 8) {
669 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
670 mtd->_lock = cfi_ppb_lock;
671 mtd->_unlock = cfi_ppb_unlock;
672 mtd->_is_locked = cfi_ppb_is_locked;
673 }
674 #endif
675
676 bootloc = extp->TopBottom;
677 if ((bootloc < 2) || (bootloc > 5)) {
678 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
679 "bank location (%d). Assuming bottom.\n",
680 map->name, bootloc);
681 bootloc = 2;
682 }
683
684 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
685 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
686
687 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
688 int j = (cfi->cfiq->NumEraseRegions-1)-i;
689
690 swap(cfi->cfiq->EraseRegionInfo[i],
691 cfi->cfiq->EraseRegionInfo[j]);
692 }
693 }
694 /* Set the default CFI lock/unlock addresses */
695 cfi->addr_unlock1 = 0x555;
696 cfi->addr_unlock2 = 0x2aa;
697 }
698 cfi_fixup(mtd, cfi_nopri_fixup_table);
699
700 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
701 kfree(mtd);
702 return NULL;
703 }
704
705 } /* CFI mode */
706 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
707 /* Apply jedec specific fixups */
708 cfi_fixup(mtd, jedec_fixup_table);
709 }
710 /* Apply generic fixups */
711 cfi_fixup(mtd, fixup_table);
712
713 for (i=0; i< cfi->numchips; i++) {
714 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
715 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
716 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
717 /*
718 * First calculate the timeout max according to timeout field
719 * of struct cfi_ident that probed from chip's CFI aera, if
720 * available. Specify a minimum of 2000us, in case the CFI data
721 * is wrong.
722 */
723 if (cfi->cfiq->BufWriteTimeoutTyp &&
724 cfi->cfiq->BufWriteTimeoutMax)
725 cfi->chips[i].buffer_write_time_max =
726 1 << (cfi->cfiq->BufWriteTimeoutTyp +
727 cfi->cfiq->BufWriteTimeoutMax);
728 else
729 cfi->chips[i].buffer_write_time_max = 0;
730
731 cfi->chips[i].buffer_write_time_max =
732 max(cfi->chips[i].buffer_write_time_max, 2000);
733
734 cfi->chips[i].ref_point_counter = 0;
735 init_waitqueue_head(&(cfi->chips[i].wq));
736 }
737
738 map->fldrv = &cfi_amdstd_chipdrv;
739
740 return cfi_amdstd_setup(mtd);
741 }
742 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
743 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
744 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
745 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
746 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
747
cfi_amdstd_setup(struct mtd_info * mtd)748 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
749 {
750 struct map_info *map = mtd->priv;
751 struct cfi_private *cfi = map->fldrv_priv;
752 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
753 unsigned long offset = 0;
754 int i,j;
755
756 printk(KERN_NOTICE "number of %s chips: %d\n",
757 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
758 /* Select the correct geometry setup */
759 mtd->size = devsize * cfi->numchips;
760
761 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
762 mtd->eraseregions = kmalloc_array(mtd->numeraseregions,
763 sizeof(struct mtd_erase_region_info),
764 GFP_KERNEL);
765 if (!mtd->eraseregions)
766 goto setup_err;
767
768 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
769 unsigned long ernum, ersize;
770 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
771 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
772
773 if (mtd->erasesize < ersize) {
774 mtd->erasesize = ersize;
775 }
776 for (j=0; j<cfi->numchips; j++) {
777 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
778 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
779 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
780 }
781 offset += (ersize * ernum);
782 }
783 if (offset != devsize) {
784 /* Argh */
785 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
786 goto setup_err;
787 }
788
789 __module_get(THIS_MODULE);
790 register_reboot_notifier(&mtd->reboot_notifier);
791 return mtd;
792
793 setup_err:
794 kfree(mtd->eraseregions);
795 kfree(mtd);
796 kfree(cfi->cmdset_priv);
797 kfree(cfi->cfiq);
798 return NULL;
799 }
800
801 /*
802 * Return true if the chip is ready.
803 *
804 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
805 * non-suspended sector) and is indicated by no toggle bits toggling.
806 *
807 * Note that anything more complicated than checking if no bits are toggling
808 * (including checking DQ5 for an error status) is tricky to get working
809 * correctly and is therefore not done (particularly with interleaved chips
810 * as each chip must be checked independently of the others).
811 */
chip_ready(struct map_info * map,struct flchip * chip,unsigned long addr)812 static int __xipram chip_ready(struct map_info *map, struct flchip *chip,
813 unsigned long addr)
814 {
815 struct cfi_private *cfi = map->fldrv_priv;
816 map_word d, t;
817
818 if (cfi_use_status_reg(cfi)) {
819 map_word ready = CMD(CFI_SR_DRB);
820 /*
821 * For chips that support status register, check device
822 * ready bit
823 */
824 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
825 cfi->device_type, NULL);
826 d = map_read(map, addr);
827
828 return map_word_andequal(map, d, ready, ready);
829 }
830
831 d = map_read(map, addr);
832 t = map_read(map, addr);
833
834 return map_word_equal(map, d, t);
835 }
836
837 /*
838 * Return true if the chip is ready and has the correct value.
839 *
840 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
841 * non-suspended sector) and it is indicated by no bits toggling.
842 *
843 * Error are indicated by toggling bits or bits held with the wrong value,
844 * or with bits toggling.
845 *
846 * Note that anything more complicated than checking if no bits are toggling
847 * (including checking DQ5 for an error status) is tricky to get working
848 * correctly and is therefore not done (particularly with interleaved chips
849 * as each chip must be checked independently of the others).
850 *
851 */
chip_good(struct map_info * map,struct flchip * chip,unsigned long addr,map_word expected)852 static int __xipram chip_good(struct map_info *map, struct flchip *chip,
853 unsigned long addr, map_word expected)
854 {
855 struct cfi_private *cfi = map->fldrv_priv;
856 map_word oldd, curd;
857
858 if (cfi_use_status_reg(cfi)) {
859 map_word ready = CMD(CFI_SR_DRB);
860
861 /*
862 * For chips that support status register, check device
863 * ready bit
864 */
865 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
866 cfi->device_type, NULL);
867 curd = map_read(map, addr);
868
869 return map_word_andequal(map, curd, ready, ready);
870 }
871
872 oldd = map_read(map, addr);
873 curd = map_read(map, addr);
874
875 return map_word_equal(map, oldd, curd) &&
876 map_word_equal(map, curd, expected);
877 }
878
get_chip(struct map_info * map,struct flchip * chip,unsigned long adr,int mode)879 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
880 {
881 DECLARE_WAITQUEUE(wait, current);
882 struct cfi_private *cfi = map->fldrv_priv;
883 unsigned long timeo;
884 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
885
886 resettime:
887 timeo = jiffies + HZ;
888 retry:
889 switch (chip->state) {
890
891 case FL_STATUS:
892 for (;;) {
893 if (chip_ready(map, chip, adr))
894 break;
895
896 if (time_after(jiffies, timeo)) {
897 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
898 return -EIO;
899 }
900 mutex_unlock(&chip->mutex);
901 cfi_udelay(1);
902 mutex_lock(&chip->mutex);
903 /* Someone else might have been playing with it. */
904 goto retry;
905 }
906
907 case FL_READY:
908 case FL_CFI_QUERY:
909 case FL_JEDEC_QUERY:
910 return 0;
911
912 case FL_ERASING:
913 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
914 !(mode == FL_READY || mode == FL_POINT ||
915 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
916 goto sleep;
917
918 /* Do not allow suspend iff read/write to EB address */
919 if ((adr & chip->in_progress_block_mask) ==
920 chip->in_progress_block_addr)
921 goto sleep;
922
923 /* Erase suspend */
924 /* It's harmless to issue the Erase-Suspend and Erase-Resume
925 * commands when the erase algorithm isn't in progress. */
926 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
927 chip->oldstate = FL_ERASING;
928 chip->state = FL_ERASE_SUSPENDING;
929 chip->erase_suspended = 1;
930 for (;;) {
931 if (chip_ready(map, chip, adr))
932 break;
933
934 if (time_after(jiffies, timeo)) {
935 /* Should have suspended the erase by now.
936 * Send an Erase-Resume command as either
937 * there was an error (so leave the erase
938 * routine to recover from it) or we trying to
939 * use the erase-in-progress sector. */
940 put_chip(map, chip, adr);
941 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
942 return -EIO;
943 }
944
945 mutex_unlock(&chip->mutex);
946 cfi_udelay(1);
947 mutex_lock(&chip->mutex);
948 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
949 So we can just loop here. */
950 }
951 chip->state = FL_READY;
952 return 0;
953
954 case FL_XIP_WHILE_ERASING:
955 if (mode != FL_READY && mode != FL_POINT &&
956 (!cfip || !(cfip->EraseSuspend&2)))
957 goto sleep;
958 chip->oldstate = chip->state;
959 chip->state = FL_READY;
960 return 0;
961
962 case FL_SHUTDOWN:
963 /* The machine is rebooting */
964 return -EIO;
965
966 case FL_POINT:
967 /* Only if there's no operation suspended... */
968 if (mode == FL_READY && chip->oldstate == FL_READY)
969 return 0;
970 /* fall through */
971
972 default:
973 sleep:
974 set_current_state(TASK_UNINTERRUPTIBLE);
975 add_wait_queue(&chip->wq, &wait);
976 mutex_unlock(&chip->mutex);
977 schedule();
978 remove_wait_queue(&chip->wq, &wait);
979 mutex_lock(&chip->mutex);
980 goto resettime;
981 }
982 }
983
984
put_chip(struct map_info * map,struct flchip * chip,unsigned long adr)985 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
986 {
987 struct cfi_private *cfi = map->fldrv_priv;
988
989 switch(chip->oldstate) {
990 case FL_ERASING:
991 cfi_fixup_m29ew_erase_suspend(map,
992 chip->in_progress_block_addr);
993 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
994 cfi_fixup_m29ew_delay_after_resume(cfi);
995 chip->oldstate = FL_READY;
996 chip->state = FL_ERASING;
997 break;
998
999 case FL_XIP_WHILE_ERASING:
1000 chip->state = chip->oldstate;
1001 chip->oldstate = FL_READY;
1002 break;
1003
1004 case FL_READY:
1005 case FL_STATUS:
1006 break;
1007 default:
1008 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
1009 }
1010 wake_up(&chip->wq);
1011 }
1012
1013 #ifdef CONFIG_MTD_XIP
1014
1015 /*
1016 * No interrupt what so ever can be serviced while the flash isn't in array
1017 * mode. This is ensured by the xip_disable() and xip_enable() functions
1018 * enclosing any code path where the flash is known not to be in array mode.
1019 * And within a XIP disabled code path, only functions marked with __xipram
1020 * may be called and nothing else (it's a good thing to inspect generated
1021 * assembly to make sure inline functions were actually inlined and that gcc
1022 * didn't emit calls to its own support functions). Also configuring MTD CFI
1023 * support to a single buswidth and a single interleave is also recommended.
1024 */
1025
xip_disable(struct map_info * map,struct flchip * chip,unsigned long adr)1026 static void xip_disable(struct map_info *map, struct flchip *chip,
1027 unsigned long adr)
1028 {
1029 /* TODO: chips with no XIP use should ignore and return */
1030 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
1031 local_irq_disable();
1032 }
1033
xip_enable(struct map_info * map,struct flchip * chip,unsigned long adr)1034 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
1035 unsigned long adr)
1036 {
1037 struct cfi_private *cfi = map->fldrv_priv;
1038
1039 if (chip->state != FL_POINT && chip->state != FL_READY) {
1040 map_write(map, CMD(0xf0), adr);
1041 chip->state = FL_READY;
1042 }
1043 (void) map_read(map, adr);
1044 xip_iprefetch();
1045 local_irq_enable();
1046 }
1047
1048 /*
1049 * When a delay is required for the flash operation to complete, the
1050 * xip_udelay() function is polling for both the given timeout and pending
1051 * (but still masked) hardware interrupts. Whenever there is an interrupt
1052 * pending then the flash erase operation is suspended, array mode restored
1053 * and interrupts unmasked. Task scheduling might also happen at that
1054 * point. The CPU eventually returns from the interrupt or the call to
1055 * schedule() and the suspended flash operation is resumed for the remaining
1056 * of the delay period.
1057 *
1058 * Warning: this function _will_ fool interrupt latency tracing tools.
1059 */
1060
xip_udelay(struct map_info * map,struct flchip * chip,unsigned long adr,int usec)1061 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
1062 unsigned long adr, int usec)
1063 {
1064 struct cfi_private *cfi = map->fldrv_priv;
1065 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
1066 map_word status, OK = CMD(0x80);
1067 unsigned long suspended, start = xip_currtime();
1068 flstate_t oldstate;
1069
1070 do {
1071 cpu_relax();
1072 if (xip_irqpending() && extp &&
1073 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
1074 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
1075 /*
1076 * Let's suspend the erase operation when supported.
1077 * Note that we currently don't try to suspend
1078 * interleaved chips if there is already another
1079 * operation suspended (imagine what happens
1080 * when one chip was already done with the current
1081 * operation while another chip suspended it, then
1082 * we resume the whole thing at once). Yes, it
1083 * can happen!
1084 */
1085 map_write(map, CMD(0xb0), adr);
1086 usec -= xip_elapsed_since(start);
1087 suspended = xip_currtime();
1088 do {
1089 if (xip_elapsed_since(suspended) > 100000) {
1090 /*
1091 * The chip doesn't want to suspend
1092 * after waiting for 100 msecs.
1093 * This is a critical error but there
1094 * is not much we can do here.
1095 */
1096 return;
1097 }
1098 status = map_read(map, adr);
1099 } while (!map_word_andequal(map, status, OK, OK));
1100
1101 /* Suspend succeeded */
1102 oldstate = chip->state;
1103 if (!map_word_bitsset(map, status, CMD(0x40)))
1104 break;
1105 chip->state = FL_XIP_WHILE_ERASING;
1106 chip->erase_suspended = 1;
1107 map_write(map, CMD(0xf0), adr);
1108 (void) map_read(map, adr);
1109 xip_iprefetch();
1110 local_irq_enable();
1111 mutex_unlock(&chip->mutex);
1112 xip_iprefetch();
1113 cond_resched();
1114
1115 /*
1116 * We're back. However someone else might have
1117 * decided to go write to the chip if we are in
1118 * a suspended erase state. If so let's wait
1119 * until it's done.
1120 */
1121 mutex_lock(&chip->mutex);
1122 while (chip->state != FL_XIP_WHILE_ERASING) {
1123 DECLARE_WAITQUEUE(wait, current);
1124 set_current_state(TASK_UNINTERRUPTIBLE);
1125 add_wait_queue(&chip->wq, &wait);
1126 mutex_unlock(&chip->mutex);
1127 schedule();
1128 remove_wait_queue(&chip->wq, &wait);
1129 mutex_lock(&chip->mutex);
1130 }
1131 /* Disallow XIP again */
1132 local_irq_disable();
1133
1134 /* Correct Erase Suspend Hangups for M29EW */
1135 cfi_fixup_m29ew_erase_suspend(map, adr);
1136 /* Resume the write or erase operation */
1137 map_write(map, cfi->sector_erase_cmd, adr);
1138 chip->state = oldstate;
1139 start = xip_currtime();
1140 } else if (usec >= 1000000/HZ) {
1141 /*
1142 * Try to save on CPU power when waiting delay
1143 * is at least a system timer tick period.
1144 * No need to be extremely accurate here.
1145 */
1146 xip_cpu_idle();
1147 }
1148 status = map_read(map, adr);
1149 } while (!map_word_andequal(map, status, OK, OK)
1150 && xip_elapsed_since(start) < usec);
1151 }
1152
1153 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1154
1155 /*
1156 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1157 * the flash is actively programming or erasing since we have to poll for
1158 * the operation to complete anyway. We can't do that in a generic way with
1159 * a XIP setup so do it before the actual flash operation in this case
1160 * and stub it out from INVALIDATE_CACHE_UDELAY.
1161 */
1162 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1163 INVALIDATE_CACHED_RANGE(map, from, size)
1164
1165 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1166 UDELAY(map, chip, adr, usec)
1167
1168 /*
1169 * Extra notes:
1170 *
1171 * Activating this XIP support changes the way the code works a bit. For
1172 * example the code to suspend the current process when concurrent access
1173 * happens is never executed because xip_udelay() will always return with the
1174 * same chip state as it was entered with. This is why there is no care for
1175 * the presence of add_wait_queue() or schedule() calls from within a couple
1176 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1177 * The queueing and scheduling are always happening within xip_udelay().
1178 *
1179 * Similarly, get_chip() and put_chip() just happen to always be executed
1180 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1181 * is in array mode, therefore never executing many cases therein and not
1182 * causing any problem with XIP.
1183 */
1184
1185 #else
1186
1187 #define xip_disable(map, chip, adr)
1188 #define xip_enable(map, chip, adr)
1189 #define XIP_INVAL_CACHED_RANGE(x...)
1190
1191 #define UDELAY(map, chip, adr, usec) \
1192 do { \
1193 mutex_unlock(&chip->mutex); \
1194 cfi_udelay(usec); \
1195 mutex_lock(&chip->mutex); \
1196 } while (0)
1197
1198 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1199 do { \
1200 mutex_unlock(&chip->mutex); \
1201 INVALIDATE_CACHED_RANGE(map, adr, len); \
1202 cfi_udelay(usec); \
1203 mutex_lock(&chip->mutex); \
1204 } while (0)
1205
1206 #endif
1207
do_read_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf)1208 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1209 {
1210 unsigned long cmd_addr;
1211 struct cfi_private *cfi = map->fldrv_priv;
1212 int ret;
1213
1214 adr += chip->start;
1215
1216 /* Ensure cmd read/writes are aligned. */
1217 cmd_addr = adr & ~(map_bankwidth(map)-1);
1218
1219 mutex_lock(&chip->mutex);
1220 ret = get_chip(map, chip, cmd_addr, FL_READY);
1221 if (ret) {
1222 mutex_unlock(&chip->mutex);
1223 return ret;
1224 }
1225
1226 if (chip->state != FL_POINT && chip->state != FL_READY) {
1227 map_write(map, CMD(0xf0), cmd_addr);
1228 chip->state = FL_READY;
1229 }
1230
1231 map_copy_from(map, buf, adr, len);
1232
1233 put_chip(map, chip, cmd_addr);
1234
1235 mutex_unlock(&chip->mutex);
1236 return 0;
1237 }
1238
1239
cfi_amdstd_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1240 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1241 {
1242 struct map_info *map = mtd->priv;
1243 struct cfi_private *cfi = map->fldrv_priv;
1244 unsigned long ofs;
1245 int chipnum;
1246 int ret = 0;
1247
1248 /* ofs: offset within the first chip that the first read should start */
1249 chipnum = (from >> cfi->chipshift);
1250 ofs = from - (chipnum << cfi->chipshift);
1251
1252 while (len) {
1253 unsigned long thislen;
1254
1255 if (chipnum >= cfi->numchips)
1256 break;
1257
1258 if ((len + ofs -1) >> cfi->chipshift)
1259 thislen = (1<<cfi->chipshift) - ofs;
1260 else
1261 thislen = len;
1262
1263 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1264 if (ret)
1265 break;
1266
1267 *retlen += thislen;
1268 len -= thislen;
1269 buf += thislen;
1270
1271 ofs = 0;
1272 chipnum++;
1273 }
1274 return ret;
1275 }
1276
1277 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1278 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1279
otp_enter(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1280 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1281 loff_t adr, size_t len)
1282 {
1283 struct cfi_private *cfi = map->fldrv_priv;
1284
1285 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1286 cfi->device_type, NULL);
1287 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1288 cfi->device_type, NULL);
1289 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1290 cfi->device_type, NULL);
1291
1292 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1293 }
1294
otp_exit(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1295 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1296 loff_t adr, size_t len)
1297 {
1298 struct cfi_private *cfi = map->fldrv_priv;
1299
1300 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1301 cfi->device_type, NULL);
1302 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1303 cfi->device_type, NULL);
1304 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1305 cfi->device_type, NULL);
1306 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1307 cfi->device_type, NULL);
1308
1309 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1310 }
1311
do_read_secsi_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1312 static inline int do_read_secsi_onechip(struct map_info *map,
1313 struct flchip *chip, loff_t adr,
1314 size_t len, u_char *buf,
1315 size_t grouplen)
1316 {
1317 DECLARE_WAITQUEUE(wait, current);
1318
1319 retry:
1320 mutex_lock(&chip->mutex);
1321
1322 if (chip->state != FL_READY){
1323 set_current_state(TASK_UNINTERRUPTIBLE);
1324 add_wait_queue(&chip->wq, &wait);
1325
1326 mutex_unlock(&chip->mutex);
1327
1328 schedule();
1329 remove_wait_queue(&chip->wq, &wait);
1330
1331 goto retry;
1332 }
1333
1334 adr += chip->start;
1335
1336 chip->state = FL_READY;
1337
1338 otp_enter(map, chip, adr, len);
1339 map_copy_from(map, buf, adr, len);
1340 otp_exit(map, chip, adr, len);
1341
1342 wake_up(&chip->wq);
1343 mutex_unlock(&chip->mutex);
1344
1345 return 0;
1346 }
1347
cfi_amdstd_secsi_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1348 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1349 {
1350 struct map_info *map = mtd->priv;
1351 struct cfi_private *cfi = map->fldrv_priv;
1352 unsigned long ofs;
1353 int chipnum;
1354 int ret = 0;
1355
1356 /* ofs: offset within the first chip that the first read should start */
1357 /* 8 secsi bytes per chip */
1358 chipnum=from>>3;
1359 ofs=from & 7;
1360
1361 while (len) {
1362 unsigned long thislen;
1363
1364 if (chipnum >= cfi->numchips)
1365 break;
1366
1367 if ((len + ofs -1) >> 3)
1368 thislen = (1<<3) - ofs;
1369 else
1370 thislen = len;
1371
1372 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1373 thislen, buf, 0);
1374 if (ret)
1375 break;
1376
1377 *retlen += thislen;
1378 len -= thislen;
1379 buf += thislen;
1380
1381 ofs = 0;
1382 chipnum++;
1383 }
1384 return ret;
1385 }
1386
1387 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1388 unsigned long adr, map_word datum,
1389 int mode);
1390
do_otp_write(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1391 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1392 size_t len, u_char *buf, size_t grouplen)
1393 {
1394 int ret;
1395 while (len) {
1396 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1397 int gap = adr - bus_ofs;
1398 int n = min_t(int, len, map_bankwidth(map) - gap);
1399 map_word datum = map_word_ff(map);
1400
1401 if (n != map_bankwidth(map)) {
1402 /* partial write of a word, load old contents */
1403 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1404 datum = map_read(map, bus_ofs);
1405 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1406 }
1407
1408 datum = map_word_load_partial(map, datum, buf, gap, n);
1409 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1410 if (ret)
1411 return ret;
1412
1413 adr += n;
1414 buf += n;
1415 len -= n;
1416 }
1417
1418 return 0;
1419 }
1420
do_otp_lock(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1421 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1422 size_t len, u_char *buf, size_t grouplen)
1423 {
1424 struct cfi_private *cfi = map->fldrv_priv;
1425 uint8_t lockreg;
1426 unsigned long timeo;
1427 int ret;
1428
1429 /* make sure area matches group boundaries */
1430 if ((adr != 0) || (len != grouplen))
1431 return -EINVAL;
1432
1433 mutex_lock(&chip->mutex);
1434 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1435 if (ret) {
1436 mutex_unlock(&chip->mutex);
1437 return ret;
1438 }
1439 chip->state = FL_LOCKING;
1440
1441 /* Enter lock register command */
1442 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1443 cfi->device_type, NULL);
1444 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1445 cfi->device_type, NULL);
1446 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1447 cfi->device_type, NULL);
1448
1449 /* read lock register */
1450 lockreg = cfi_read_query(map, 0);
1451
1452 /* set bit 0 to protect extended memory block */
1453 lockreg &= ~0x01;
1454
1455 /* set bit 0 to protect extended memory block */
1456 /* write lock register */
1457 map_write(map, CMD(0xA0), chip->start);
1458 map_write(map, CMD(lockreg), chip->start);
1459
1460 /* wait for chip to become ready */
1461 timeo = jiffies + msecs_to_jiffies(2);
1462 for (;;) {
1463 if (chip_ready(map, chip, adr))
1464 break;
1465
1466 if (time_after(jiffies, timeo)) {
1467 pr_err("Waiting for chip to be ready timed out.\n");
1468 ret = -EIO;
1469 break;
1470 }
1471 UDELAY(map, chip, 0, 1);
1472 }
1473
1474 /* exit protection commands */
1475 map_write(map, CMD(0x90), chip->start);
1476 map_write(map, CMD(0x00), chip->start);
1477
1478 chip->state = FL_READY;
1479 put_chip(map, chip, chip->start);
1480 mutex_unlock(&chip->mutex);
1481
1482 return ret;
1483 }
1484
cfi_amdstd_otp_walk(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf,otp_op_t action,int user_regs)1485 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1486 size_t *retlen, u_char *buf,
1487 otp_op_t action, int user_regs)
1488 {
1489 struct map_info *map = mtd->priv;
1490 struct cfi_private *cfi = map->fldrv_priv;
1491 int ofs_factor = cfi->interleave * cfi->device_type;
1492 unsigned long base;
1493 int chipnum;
1494 struct flchip *chip;
1495 uint8_t otp, lockreg;
1496 int ret;
1497
1498 size_t user_size, factory_size, otpsize;
1499 loff_t user_offset, factory_offset, otpoffset;
1500 int user_locked = 0, otplocked;
1501
1502 *retlen = 0;
1503
1504 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1505 chip = &cfi->chips[chipnum];
1506 factory_size = 0;
1507 user_size = 0;
1508
1509 /* Micron M29EW family */
1510 if (is_m29ew(cfi)) {
1511 base = chip->start;
1512
1513 /* check whether secsi area is factory locked
1514 or user lockable */
1515 mutex_lock(&chip->mutex);
1516 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1517 if (ret) {
1518 mutex_unlock(&chip->mutex);
1519 return ret;
1520 }
1521 cfi_qry_mode_on(base, map, cfi);
1522 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1523 cfi_qry_mode_off(base, map, cfi);
1524 put_chip(map, chip, base);
1525 mutex_unlock(&chip->mutex);
1526
1527 if (otp & 0x80) {
1528 /* factory locked */
1529 factory_offset = 0;
1530 factory_size = 0x100;
1531 } else {
1532 /* customer lockable */
1533 user_offset = 0;
1534 user_size = 0x100;
1535
1536 mutex_lock(&chip->mutex);
1537 ret = get_chip(map, chip, base, FL_LOCKING);
1538 if (ret) {
1539 mutex_unlock(&chip->mutex);
1540 return ret;
1541 }
1542
1543 /* Enter lock register command */
1544 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1545 chip->start, map, cfi,
1546 cfi->device_type, NULL);
1547 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1548 chip->start, map, cfi,
1549 cfi->device_type, NULL);
1550 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1551 chip->start, map, cfi,
1552 cfi->device_type, NULL);
1553 /* read lock register */
1554 lockreg = cfi_read_query(map, 0);
1555 /* exit protection commands */
1556 map_write(map, CMD(0x90), chip->start);
1557 map_write(map, CMD(0x00), chip->start);
1558 put_chip(map, chip, chip->start);
1559 mutex_unlock(&chip->mutex);
1560
1561 user_locked = ((lockreg & 0x01) == 0x00);
1562 }
1563 }
1564
1565 otpsize = user_regs ? user_size : factory_size;
1566 if (!otpsize)
1567 continue;
1568 otpoffset = user_regs ? user_offset : factory_offset;
1569 otplocked = user_regs ? user_locked : 1;
1570
1571 if (!action) {
1572 /* return otpinfo */
1573 struct otp_info *otpinfo;
1574 len -= sizeof(*otpinfo);
1575 if (len <= 0)
1576 return -ENOSPC;
1577 otpinfo = (struct otp_info *)buf;
1578 otpinfo->start = from;
1579 otpinfo->length = otpsize;
1580 otpinfo->locked = otplocked;
1581 buf += sizeof(*otpinfo);
1582 *retlen += sizeof(*otpinfo);
1583 from += otpsize;
1584 } else if ((from < otpsize) && (len > 0)) {
1585 size_t size;
1586 size = (len < otpsize - from) ? len : otpsize - from;
1587 ret = action(map, chip, otpoffset + from, size, buf,
1588 otpsize);
1589 if (ret < 0)
1590 return ret;
1591
1592 buf += size;
1593 len -= size;
1594 *retlen += size;
1595 from = 0;
1596 } else {
1597 from -= otpsize;
1598 }
1599 }
1600 return 0;
1601 }
1602
cfi_amdstd_get_fact_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1603 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1604 size_t *retlen, struct otp_info *buf)
1605 {
1606 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1607 NULL, 0);
1608 }
1609
cfi_amdstd_get_user_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1610 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1611 size_t *retlen, struct otp_info *buf)
1612 {
1613 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1614 NULL, 1);
1615 }
1616
cfi_amdstd_read_fact_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1617 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1618 size_t len, size_t *retlen,
1619 u_char *buf)
1620 {
1621 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1622 buf, do_read_secsi_onechip, 0);
1623 }
1624
cfi_amdstd_read_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1625 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1626 size_t len, size_t *retlen,
1627 u_char *buf)
1628 {
1629 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1630 buf, do_read_secsi_onechip, 1);
1631 }
1632
cfi_amdstd_write_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1633 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1634 size_t len, size_t *retlen,
1635 u_char *buf)
1636 {
1637 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1638 do_otp_write, 1);
1639 }
1640
cfi_amdstd_lock_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len)1641 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1642 size_t len)
1643 {
1644 size_t retlen;
1645 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1646 do_otp_lock, 1);
1647 }
1648
do_write_oneword_once(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum,int mode,struct cfi_private * cfi)1649 static int __xipram do_write_oneword_once(struct map_info *map,
1650 struct flchip *chip,
1651 unsigned long adr, map_word datum,
1652 int mode, struct cfi_private *cfi)
1653 {
1654 unsigned long timeo = jiffies + HZ;
1655 /*
1656 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1657 * have a max write time of a few hundreds usec). However, we should
1658 * use the maximum timeout value given by the chip at probe time
1659 * instead. Unfortunately, struct flchip does have a field for
1660 * maximum timeout, only for typical which can be far too short
1661 * depending of the conditions. The ' + 1' is to avoid having a
1662 * timeout of 0 jiffies if HZ is smaller than 1000.
1663 */
1664 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1665 int ret = 0;
1666
1667 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1668 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1669 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1670 map_write(map, datum, adr);
1671 chip->state = mode;
1672
1673 INVALIDATE_CACHE_UDELAY(map, chip,
1674 adr, map_bankwidth(map),
1675 chip->word_write_time);
1676
1677 /* See comment above for timeout value. */
1678 timeo = jiffies + uWriteTimeout;
1679 for (;;) {
1680 if (chip->state != mode) {
1681 /* Someone's suspended the write. Sleep */
1682 DECLARE_WAITQUEUE(wait, current);
1683
1684 set_current_state(TASK_UNINTERRUPTIBLE);
1685 add_wait_queue(&chip->wq, &wait);
1686 mutex_unlock(&chip->mutex);
1687 schedule();
1688 remove_wait_queue(&chip->wq, &wait);
1689 timeo = jiffies + (HZ / 2); /* FIXME */
1690 mutex_lock(&chip->mutex);
1691 continue;
1692 }
1693
1694 /*
1695 * We check "time_after" and "!chip_good" before checking
1696 * "chip_good" to avoid the failure due to scheduling.
1697 */
1698 if (time_after(jiffies, timeo) &&
1699 !chip_good(map, chip, adr, datum)) {
1700 xip_enable(map, chip, adr);
1701 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1702 xip_disable(map, chip, adr);
1703 ret = -EIO;
1704 break;
1705 }
1706
1707 if (chip_good(map, chip, adr, datum)) {
1708 if (cfi_check_err_status(map, chip, adr))
1709 ret = -EIO;
1710 break;
1711 }
1712
1713 /* Latency issues. Drop the lock, wait a while and retry */
1714 UDELAY(map, chip, adr, 1);
1715 }
1716
1717 return ret;
1718 }
1719
do_write_oneword_start(struct map_info * map,struct flchip * chip,unsigned long adr,int mode)1720 static int __xipram do_write_oneword_start(struct map_info *map,
1721 struct flchip *chip,
1722 unsigned long adr, int mode)
1723 {
1724 int ret = 0;
1725
1726 mutex_lock(&chip->mutex);
1727
1728 ret = get_chip(map, chip, adr, mode);
1729 if (ret) {
1730 mutex_unlock(&chip->mutex);
1731 return ret;
1732 }
1733
1734 if (mode == FL_OTP_WRITE)
1735 otp_enter(map, chip, adr, map_bankwidth(map));
1736
1737 return ret;
1738 }
1739
do_write_oneword_done(struct map_info * map,struct flchip * chip,unsigned long adr,int mode)1740 static void __xipram do_write_oneword_done(struct map_info *map,
1741 struct flchip *chip,
1742 unsigned long adr, int mode)
1743 {
1744 if (mode == FL_OTP_WRITE)
1745 otp_exit(map, chip, adr, map_bankwidth(map));
1746
1747 chip->state = FL_READY;
1748 DISABLE_VPP(map);
1749 put_chip(map, chip, adr);
1750
1751 mutex_unlock(&chip->mutex);
1752 }
1753
do_write_oneword_retry(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum,int mode)1754 static int __xipram do_write_oneword_retry(struct map_info *map,
1755 struct flchip *chip,
1756 unsigned long adr, map_word datum,
1757 int mode)
1758 {
1759 struct cfi_private *cfi = map->fldrv_priv;
1760 int ret = 0;
1761 map_word oldd;
1762 int retry_cnt = 0;
1763
1764 /*
1765 * Check for a NOP for the case when the datum to write is already
1766 * present - it saves time and works around buggy chips that corrupt
1767 * data at other locations when 0xff is written to a location that
1768 * already contains 0xff.
1769 */
1770 oldd = map_read(map, adr);
1771 if (map_word_equal(map, oldd, datum)) {
1772 pr_debug("MTD %s(): NOP\n", __func__);
1773 return ret;
1774 }
1775
1776 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1777 ENABLE_VPP(map);
1778 xip_disable(map, chip, adr);
1779
1780 retry:
1781 ret = do_write_oneword_once(map, chip, adr, datum, mode, cfi);
1782 if (ret) {
1783 /* reset on all failures. */
1784 map_write(map, CMD(0xF0), chip->start);
1785 /* FIXME - should have reset delay before continuing */
1786
1787 if (++retry_cnt <= MAX_RETRIES) {
1788 ret = 0;
1789 goto retry;
1790 }
1791 }
1792 xip_enable(map, chip, adr);
1793
1794 return ret;
1795 }
1796
do_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum,int mode)1797 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1798 unsigned long adr, map_word datum,
1799 int mode)
1800 {
1801 int ret = 0;
1802
1803 adr += chip->start;
1804
1805 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", __func__, adr,
1806 datum.x[0]);
1807
1808 ret = do_write_oneword_start(map, chip, adr, mode);
1809 if (ret)
1810 return ret;
1811
1812 ret = do_write_oneword_retry(map, chip, adr, datum, mode);
1813
1814 do_write_oneword_done(map, chip, adr, mode);
1815
1816 return ret;
1817 }
1818
1819
cfi_amdstd_write_words(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1820 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1821 size_t *retlen, const u_char *buf)
1822 {
1823 struct map_info *map = mtd->priv;
1824 struct cfi_private *cfi = map->fldrv_priv;
1825 int ret = 0;
1826 int chipnum;
1827 unsigned long ofs, chipstart;
1828 DECLARE_WAITQUEUE(wait, current);
1829
1830 chipnum = to >> cfi->chipshift;
1831 ofs = to - (chipnum << cfi->chipshift);
1832 chipstart = cfi->chips[chipnum].start;
1833
1834 /* If it's not bus-aligned, do the first byte write */
1835 if (ofs & (map_bankwidth(map)-1)) {
1836 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1837 int i = ofs - bus_ofs;
1838 int n = 0;
1839 map_word tmp_buf;
1840
1841 retry:
1842 mutex_lock(&cfi->chips[chipnum].mutex);
1843
1844 if (cfi->chips[chipnum].state != FL_READY) {
1845 set_current_state(TASK_UNINTERRUPTIBLE);
1846 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1847
1848 mutex_unlock(&cfi->chips[chipnum].mutex);
1849
1850 schedule();
1851 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1852 goto retry;
1853 }
1854
1855 /* Load 'tmp_buf' with old contents of flash */
1856 tmp_buf = map_read(map, bus_ofs+chipstart);
1857
1858 mutex_unlock(&cfi->chips[chipnum].mutex);
1859
1860 /* Number of bytes to copy from buffer */
1861 n = min_t(int, len, map_bankwidth(map)-i);
1862
1863 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1864
1865 ret = do_write_oneword(map, &cfi->chips[chipnum],
1866 bus_ofs, tmp_buf, FL_WRITING);
1867 if (ret)
1868 return ret;
1869
1870 ofs += n;
1871 buf += n;
1872 (*retlen) += n;
1873 len -= n;
1874
1875 if (ofs >> cfi->chipshift) {
1876 chipnum ++;
1877 ofs = 0;
1878 if (chipnum == cfi->numchips)
1879 return 0;
1880 }
1881 }
1882
1883 /* We are now aligned, write as much as possible */
1884 while(len >= map_bankwidth(map)) {
1885 map_word datum;
1886
1887 datum = map_word_load(map, buf);
1888
1889 ret = do_write_oneword(map, &cfi->chips[chipnum],
1890 ofs, datum, FL_WRITING);
1891 if (ret)
1892 return ret;
1893
1894 ofs += map_bankwidth(map);
1895 buf += map_bankwidth(map);
1896 (*retlen) += map_bankwidth(map);
1897 len -= map_bankwidth(map);
1898
1899 if (ofs >> cfi->chipshift) {
1900 chipnum ++;
1901 ofs = 0;
1902 if (chipnum == cfi->numchips)
1903 return 0;
1904 chipstart = cfi->chips[chipnum].start;
1905 }
1906 }
1907
1908 /* Write the trailing bytes if any */
1909 if (len & (map_bankwidth(map)-1)) {
1910 map_word tmp_buf;
1911
1912 retry1:
1913 mutex_lock(&cfi->chips[chipnum].mutex);
1914
1915 if (cfi->chips[chipnum].state != FL_READY) {
1916 set_current_state(TASK_UNINTERRUPTIBLE);
1917 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1918
1919 mutex_unlock(&cfi->chips[chipnum].mutex);
1920
1921 schedule();
1922 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1923 goto retry1;
1924 }
1925
1926 tmp_buf = map_read(map, ofs + chipstart);
1927
1928 mutex_unlock(&cfi->chips[chipnum].mutex);
1929
1930 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1931
1932 ret = do_write_oneword(map, &cfi->chips[chipnum],
1933 ofs, tmp_buf, FL_WRITING);
1934 if (ret)
1935 return ret;
1936
1937 (*retlen) += len;
1938 }
1939
1940 return 0;
1941 }
1942
1943 #if !FORCE_WORD_WRITE
do_write_buffer_wait(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum)1944 static int __xipram do_write_buffer_wait(struct map_info *map,
1945 struct flchip *chip, unsigned long adr,
1946 map_word datum)
1947 {
1948 unsigned long timeo;
1949 unsigned long u_write_timeout;
1950 int ret = 0;
1951
1952 /*
1953 * Timeout is calculated according to CFI data, if available.
1954 * See more comments in cfi_cmdset_0002().
1955 */
1956 u_write_timeout = usecs_to_jiffies(chip->buffer_write_time_max);
1957 timeo = jiffies + u_write_timeout;
1958
1959 for (;;) {
1960 if (chip->state != FL_WRITING) {
1961 /* Someone's suspended the write. Sleep */
1962 DECLARE_WAITQUEUE(wait, current);
1963
1964 set_current_state(TASK_UNINTERRUPTIBLE);
1965 add_wait_queue(&chip->wq, &wait);
1966 mutex_unlock(&chip->mutex);
1967 schedule();
1968 remove_wait_queue(&chip->wq, &wait);
1969 timeo = jiffies + (HZ / 2); /* FIXME */
1970 mutex_lock(&chip->mutex);
1971 continue;
1972 }
1973
1974 /*
1975 * We check "time_after" and "!chip_good" before checking
1976 * "chip_good" to avoid the failure due to scheduling.
1977 */
1978 if (time_after(jiffies, timeo) &&
1979 !chip_good(map, chip, adr, datum)) {
1980 pr_err("MTD %s(): software timeout, address:0x%.8lx.\n",
1981 __func__, adr);
1982 ret = -EIO;
1983 break;
1984 }
1985
1986 if (chip_good(map, chip, adr, datum)) {
1987 if (cfi_check_err_status(map, chip, adr))
1988 ret = -EIO;
1989 break;
1990 }
1991
1992 /* Latency issues. Drop the lock, wait a while and retry */
1993 UDELAY(map, chip, adr, 1);
1994 }
1995
1996 return ret;
1997 }
1998
do_write_buffer_reset(struct map_info * map,struct flchip * chip,struct cfi_private * cfi)1999 static void __xipram do_write_buffer_reset(struct map_info *map,
2000 struct flchip *chip,
2001 struct cfi_private *cfi)
2002 {
2003 /*
2004 * Recovery from write-buffer programming failures requires
2005 * the write-to-buffer-reset sequence. Since the last part
2006 * of the sequence also works as a normal reset, we can run
2007 * the same commands regardless of why we are here.
2008 * See e.g.
2009 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
2010 */
2011 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2012 cfi->device_type, NULL);
2013 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2014 cfi->device_type, NULL);
2015 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
2016 cfi->device_type, NULL);
2017
2018 /* FIXME - should have reset delay before continuing */
2019 }
2020
2021 /*
2022 * FIXME: interleaved mode not tested, and probably not supported!
2023 */
do_write_buffer(struct map_info * map,struct flchip * chip,unsigned long adr,const u_char * buf,int len)2024 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
2025 unsigned long adr, const u_char *buf,
2026 int len)
2027 {
2028 struct cfi_private *cfi = map->fldrv_priv;
2029 int ret = -EIO;
2030 unsigned long cmd_adr;
2031 int z, words;
2032 map_word datum;
2033
2034 adr += chip->start;
2035 cmd_adr = adr;
2036
2037 mutex_lock(&chip->mutex);
2038 ret = get_chip(map, chip, adr, FL_WRITING);
2039 if (ret) {
2040 mutex_unlock(&chip->mutex);
2041 return ret;
2042 }
2043
2044 datum = map_word_load(map, buf);
2045
2046 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
2047 __func__, adr, datum.x[0]);
2048
2049 XIP_INVAL_CACHED_RANGE(map, adr, len);
2050 ENABLE_VPP(map);
2051 xip_disable(map, chip, cmd_adr);
2052
2053 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2054 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2055
2056 /* Write Buffer Load */
2057 map_write(map, CMD(0x25), cmd_adr);
2058
2059 chip->state = FL_WRITING_TO_BUFFER;
2060
2061 /* Write length of data to come */
2062 words = len / map_bankwidth(map);
2063 map_write(map, CMD(words - 1), cmd_adr);
2064 /* Write data */
2065 z = 0;
2066 while(z < words * map_bankwidth(map)) {
2067 datum = map_word_load(map, buf);
2068 map_write(map, datum, adr + z);
2069
2070 z += map_bankwidth(map);
2071 buf += map_bankwidth(map);
2072 }
2073 z -= map_bankwidth(map);
2074
2075 adr += z;
2076
2077 /* Write Buffer Program Confirm: GO GO GO */
2078 map_write(map, CMD(0x29), cmd_adr);
2079 chip->state = FL_WRITING;
2080
2081 INVALIDATE_CACHE_UDELAY(map, chip,
2082 adr, map_bankwidth(map),
2083 chip->word_write_time);
2084
2085 ret = do_write_buffer_wait(map, chip, adr, datum);
2086 if (ret)
2087 do_write_buffer_reset(map, chip, cfi);
2088
2089 xip_enable(map, chip, adr);
2090
2091 chip->state = FL_READY;
2092 DISABLE_VPP(map);
2093 put_chip(map, chip, adr);
2094 mutex_unlock(&chip->mutex);
2095
2096 return ret;
2097 }
2098
2099
cfi_amdstd_write_buffers(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)2100 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
2101 size_t *retlen, const u_char *buf)
2102 {
2103 struct map_info *map = mtd->priv;
2104 struct cfi_private *cfi = map->fldrv_priv;
2105 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
2106 int ret = 0;
2107 int chipnum;
2108 unsigned long ofs;
2109
2110 chipnum = to >> cfi->chipshift;
2111 ofs = to - (chipnum << cfi->chipshift);
2112
2113 /* If it's not bus-aligned, do the first word write */
2114 if (ofs & (map_bankwidth(map)-1)) {
2115 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
2116 if (local_len > len)
2117 local_len = len;
2118 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2119 local_len, retlen, buf);
2120 if (ret)
2121 return ret;
2122 ofs += local_len;
2123 buf += local_len;
2124 len -= local_len;
2125
2126 if (ofs >> cfi->chipshift) {
2127 chipnum ++;
2128 ofs = 0;
2129 if (chipnum == cfi->numchips)
2130 return 0;
2131 }
2132 }
2133
2134 /* Write buffer is worth it only if more than one word to write... */
2135 while (len >= map_bankwidth(map) * 2) {
2136 /* We must not cross write block boundaries */
2137 int size = wbufsize - (ofs & (wbufsize-1));
2138
2139 if (size > len)
2140 size = len;
2141 if (size % map_bankwidth(map))
2142 size -= size % map_bankwidth(map);
2143
2144 ret = do_write_buffer(map, &cfi->chips[chipnum],
2145 ofs, buf, size);
2146 if (ret)
2147 return ret;
2148
2149 ofs += size;
2150 buf += size;
2151 (*retlen) += size;
2152 len -= size;
2153
2154 if (ofs >> cfi->chipshift) {
2155 chipnum ++;
2156 ofs = 0;
2157 if (chipnum == cfi->numchips)
2158 return 0;
2159 }
2160 }
2161
2162 if (len) {
2163 size_t retlen_dregs = 0;
2164
2165 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
2166 len, &retlen_dregs, buf);
2167
2168 *retlen += retlen_dregs;
2169 return ret;
2170 }
2171
2172 return 0;
2173 }
2174 #endif /* !FORCE_WORD_WRITE */
2175
2176 /*
2177 * Wait for the flash chip to become ready to write data
2178 *
2179 * This is only called during the panic_write() path. When panic_write()
2180 * is called, the kernel is in the process of a panic, and will soon be
2181 * dead. Therefore we don't take any locks, and attempt to get access
2182 * to the chip as soon as possible.
2183 */
cfi_amdstd_panic_wait(struct map_info * map,struct flchip * chip,unsigned long adr)2184 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2185 unsigned long adr)
2186 {
2187 struct cfi_private *cfi = map->fldrv_priv;
2188 int retries = 10;
2189 int i;
2190
2191 /*
2192 * If the driver thinks the chip is idle, and no toggle bits
2193 * are changing, then the chip is actually idle for sure.
2194 */
2195 if (chip->state == FL_READY && chip_ready(map, chip, adr))
2196 return 0;
2197
2198 /*
2199 * Try several times to reset the chip and then wait for it
2200 * to become idle. The upper limit of a few milliseconds of
2201 * delay isn't a big problem: the kernel is dying anyway. It
2202 * is more important to save the messages.
2203 */
2204 while (retries > 0) {
2205 const unsigned long timeo = (HZ / 1000) + 1;
2206
2207 /* send the reset command */
2208 map_write(map, CMD(0xF0), chip->start);
2209
2210 /* wait for the chip to become ready */
2211 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2212 if (chip_ready(map, chip, adr))
2213 return 0;
2214
2215 udelay(1);
2216 }
2217
2218 retries--;
2219 }
2220
2221 /* the chip never became ready */
2222 return -EBUSY;
2223 }
2224
2225 /*
2226 * Write out one word of data to a single flash chip during a kernel panic
2227 *
2228 * This is only called during the panic_write() path. When panic_write()
2229 * is called, the kernel is in the process of a panic, and will soon be
2230 * dead. Therefore we don't take any locks, and attempt to get access
2231 * to the chip as soon as possible.
2232 *
2233 * The implementation of this routine is intentionally similar to
2234 * do_write_oneword(), in order to ease code maintenance.
2235 */
do_panic_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum)2236 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2237 unsigned long adr, map_word datum)
2238 {
2239 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2240 struct cfi_private *cfi = map->fldrv_priv;
2241 int retry_cnt = 0;
2242 map_word oldd;
2243 int ret = 0;
2244 int i;
2245
2246 adr += chip->start;
2247
2248 ret = cfi_amdstd_panic_wait(map, chip, adr);
2249 if (ret)
2250 return ret;
2251
2252 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2253 __func__, adr, datum.x[0]);
2254
2255 /*
2256 * Check for a NOP for the case when the datum to write is already
2257 * present - it saves time and works around buggy chips that corrupt
2258 * data at other locations when 0xff is written to a location that
2259 * already contains 0xff.
2260 */
2261 oldd = map_read(map, adr);
2262 if (map_word_equal(map, oldd, datum)) {
2263 pr_debug("MTD %s(): NOP\n", __func__);
2264 goto op_done;
2265 }
2266
2267 ENABLE_VPP(map);
2268
2269 retry:
2270 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2271 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2272 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2273 map_write(map, datum, adr);
2274
2275 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2276 if (chip_ready(map, chip, adr))
2277 break;
2278
2279 udelay(1);
2280 }
2281
2282 if (!chip_good(map, chip, adr, datum) ||
2283 cfi_check_err_status(map, chip, adr)) {
2284 /* reset on all failures. */
2285 map_write(map, CMD(0xF0), chip->start);
2286 /* FIXME - should have reset delay before continuing */
2287
2288 if (++retry_cnt <= MAX_RETRIES)
2289 goto retry;
2290
2291 ret = -EIO;
2292 }
2293
2294 op_done:
2295 DISABLE_VPP(map);
2296 return ret;
2297 }
2298
2299 /*
2300 * Write out some data during a kernel panic
2301 *
2302 * This is used by the mtdoops driver to save the dying messages from a
2303 * kernel which has panic'd.
2304 *
2305 * This routine ignores all of the locking used throughout the rest of the
2306 * driver, in order to ensure that the data gets written out no matter what
2307 * state this driver (and the flash chip itself) was in when the kernel crashed.
2308 *
2309 * The implementation of this routine is intentionally similar to
2310 * cfi_amdstd_write_words(), in order to ease code maintenance.
2311 */
cfi_amdstd_panic_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)2312 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2313 size_t *retlen, const u_char *buf)
2314 {
2315 struct map_info *map = mtd->priv;
2316 struct cfi_private *cfi = map->fldrv_priv;
2317 unsigned long ofs, chipstart;
2318 int ret = 0;
2319 int chipnum;
2320
2321 chipnum = to >> cfi->chipshift;
2322 ofs = to - (chipnum << cfi->chipshift);
2323 chipstart = cfi->chips[chipnum].start;
2324
2325 /* If it's not bus aligned, do the first byte write */
2326 if (ofs & (map_bankwidth(map) - 1)) {
2327 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2328 int i = ofs - bus_ofs;
2329 int n = 0;
2330 map_word tmp_buf;
2331
2332 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2333 if (ret)
2334 return ret;
2335
2336 /* Load 'tmp_buf' with old contents of flash */
2337 tmp_buf = map_read(map, bus_ofs + chipstart);
2338
2339 /* Number of bytes to copy from buffer */
2340 n = min_t(int, len, map_bankwidth(map) - i);
2341
2342 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2343
2344 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2345 bus_ofs, tmp_buf);
2346 if (ret)
2347 return ret;
2348
2349 ofs += n;
2350 buf += n;
2351 (*retlen) += n;
2352 len -= n;
2353
2354 if (ofs >> cfi->chipshift) {
2355 chipnum++;
2356 ofs = 0;
2357 if (chipnum == cfi->numchips)
2358 return 0;
2359 }
2360 }
2361
2362 /* We are now aligned, write as much as possible */
2363 while (len >= map_bankwidth(map)) {
2364 map_word datum;
2365
2366 datum = map_word_load(map, buf);
2367
2368 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2369 ofs, datum);
2370 if (ret)
2371 return ret;
2372
2373 ofs += map_bankwidth(map);
2374 buf += map_bankwidth(map);
2375 (*retlen) += map_bankwidth(map);
2376 len -= map_bankwidth(map);
2377
2378 if (ofs >> cfi->chipshift) {
2379 chipnum++;
2380 ofs = 0;
2381 if (chipnum == cfi->numchips)
2382 return 0;
2383
2384 chipstart = cfi->chips[chipnum].start;
2385 }
2386 }
2387
2388 /* Write the trailing bytes if any */
2389 if (len & (map_bankwidth(map) - 1)) {
2390 map_word tmp_buf;
2391
2392 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2393 if (ret)
2394 return ret;
2395
2396 tmp_buf = map_read(map, ofs + chipstart);
2397
2398 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2399
2400 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2401 ofs, tmp_buf);
2402 if (ret)
2403 return ret;
2404
2405 (*retlen) += len;
2406 }
2407
2408 return 0;
2409 }
2410
2411
2412 /*
2413 * Handle devices with one erase region, that only implement
2414 * the chip erase command.
2415 */
do_erase_chip(struct map_info * map,struct flchip * chip)2416 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2417 {
2418 struct cfi_private *cfi = map->fldrv_priv;
2419 unsigned long timeo = jiffies + HZ;
2420 unsigned long int adr;
2421 DECLARE_WAITQUEUE(wait, current);
2422 int ret = 0;
2423 int retry_cnt = 0;
2424
2425 adr = cfi->addr_unlock1;
2426
2427 mutex_lock(&chip->mutex);
2428 ret = get_chip(map, chip, adr, FL_ERASING);
2429 if (ret) {
2430 mutex_unlock(&chip->mutex);
2431 return ret;
2432 }
2433
2434 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2435 __func__, chip->start);
2436
2437 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2438 ENABLE_VPP(map);
2439 xip_disable(map, chip, adr);
2440
2441 retry:
2442 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2443 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2444 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2445 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2446 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2447 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2448
2449 chip->state = FL_ERASING;
2450 chip->erase_suspended = 0;
2451 chip->in_progress_block_addr = adr;
2452 chip->in_progress_block_mask = ~(map->size - 1);
2453
2454 INVALIDATE_CACHE_UDELAY(map, chip,
2455 adr, map->size,
2456 chip->erase_time*500);
2457
2458 timeo = jiffies + (HZ*20);
2459
2460 for (;;) {
2461 if (chip->state != FL_ERASING) {
2462 /* Someone's suspended the erase. Sleep */
2463 set_current_state(TASK_UNINTERRUPTIBLE);
2464 add_wait_queue(&chip->wq, &wait);
2465 mutex_unlock(&chip->mutex);
2466 schedule();
2467 remove_wait_queue(&chip->wq, &wait);
2468 mutex_lock(&chip->mutex);
2469 continue;
2470 }
2471 if (chip->erase_suspended) {
2472 /* This erase was suspended and resumed.
2473 Adjust the timeout */
2474 timeo = jiffies + (HZ*20); /* FIXME */
2475 chip->erase_suspended = 0;
2476 }
2477
2478 if (chip_good(map, chip, adr, map_word_ff(map))) {
2479 if (cfi_check_err_status(map, chip, adr))
2480 ret = -EIO;
2481 break;
2482 }
2483
2484 if (time_after(jiffies, timeo)) {
2485 printk(KERN_WARNING "MTD %s(): software timeout\n",
2486 __func__);
2487 ret = -EIO;
2488 break;
2489 }
2490
2491 /* Latency issues. Drop the lock, wait a while and retry */
2492 UDELAY(map, chip, adr, 1000000/HZ);
2493 }
2494 /* Did we succeed? */
2495 if (ret) {
2496 /* reset on all failures. */
2497 map_write(map, CMD(0xF0), chip->start);
2498 /* FIXME - should have reset delay before continuing */
2499
2500 if (++retry_cnt <= MAX_RETRIES) {
2501 ret = 0;
2502 goto retry;
2503 }
2504 }
2505
2506 chip->state = FL_READY;
2507 xip_enable(map, chip, adr);
2508 DISABLE_VPP(map);
2509 put_chip(map, chip, adr);
2510 mutex_unlock(&chip->mutex);
2511
2512 return ret;
2513 }
2514
2515
do_erase_oneblock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2516 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2517 {
2518 struct cfi_private *cfi = map->fldrv_priv;
2519 unsigned long timeo = jiffies + HZ;
2520 DECLARE_WAITQUEUE(wait, current);
2521 int ret = 0;
2522 int retry_cnt = 0;
2523
2524 adr += chip->start;
2525
2526 mutex_lock(&chip->mutex);
2527 ret = get_chip(map, chip, adr, FL_ERASING);
2528 if (ret) {
2529 mutex_unlock(&chip->mutex);
2530 return ret;
2531 }
2532
2533 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2534 __func__, adr);
2535
2536 XIP_INVAL_CACHED_RANGE(map, adr, len);
2537 ENABLE_VPP(map);
2538 xip_disable(map, chip, adr);
2539
2540 retry:
2541 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2542 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2543 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2544 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2545 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2546 map_write(map, cfi->sector_erase_cmd, adr);
2547
2548 chip->state = FL_ERASING;
2549 chip->erase_suspended = 0;
2550 chip->in_progress_block_addr = adr;
2551 chip->in_progress_block_mask = ~(len - 1);
2552
2553 INVALIDATE_CACHE_UDELAY(map, chip,
2554 adr, len,
2555 chip->erase_time*500);
2556
2557 timeo = jiffies + (HZ*20);
2558
2559 for (;;) {
2560 if (chip->state != FL_ERASING) {
2561 /* Someone's suspended the erase. Sleep */
2562 set_current_state(TASK_UNINTERRUPTIBLE);
2563 add_wait_queue(&chip->wq, &wait);
2564 mutex_unlock(&chip->mutex);
2565 schedule();
2566 remove_wait_queue(&chip->wq, &wait);
2567 mutex_lock(&chip->mutex);
2568 continue;
2569 }
2570 if (chip->erase_suspended) {
2571 /* This erase was suspended and resumed.
2572 Adjust the timeout */
2573 timeo = jiffies + (HZ*20); /* FIXME */
2574 chip->erase_suspended = 0;
2575 }
2576
2577 if (chip_good(map, chip, adr, map_word_ff(map))) {
2578 if (cfi_check_err_status(map, chip, adr))
2579 ret = -EIO;
2580 break;
2581 }
2582
2583 if (time_after(jiffies, timeo)) {
2584 printk(KERN_WARNING "MTD %s(): software timeout\n",
2585 __func__);
2586 ret = -EIO;
2587 break;
2588 }
2589
2590 /* Latency issues. Drop the lock, wait a while and retry */
2591 UDELAY(map, chip, adr, 1000000/HZ);
2592 }
2593 /* Did we succeed? */
2594 if (ret) {
2595 /* reset on all failures. */
2596 map_write(map, CMD(0xF0), chip->start);
2597 /* FIXME - should have reset delay before continuing */
2598
2599 if (++retry_cnt <= MAX_RETRIES) {
2600 ret = 0;
2601 goto retry;
2602 }
2603 }
2604
2605 chip->state = FL_READY;
2606 xip_enable(map, chip, adr);
2607 DISABLE_VPP(map);
2608 put_chip(map, chip, adr);
2609 mutex_unlock(&chip->mutex);
2610 return ret;
2611 }
2612
2613
cfi_amdstd_erase_varsize(struct mtd_info * mtd,struct erase_info * instr)2614 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2615 {
2616 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2617 instr->len, NULL);
2618 }
2619
2620
cfi_amdstd_erase_chip(struct mtd_info * mtd,struct erase_info * instr)2621 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2622 {
2623 struct map_info *map = mtd->priv;
2624 struct cfi_private *cfi = map->fldrv_priv;
2625
2626 if (instr->addr != 0)
2627 return -EINVAL;
2628
2629 if (instr->len != mtd->size)
2630 return -EINVAL;
2631
2632 return do_erase_chip(map, &cfi->chips[0]);
2633 }
2634
do_atmel_lock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2635 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2636 unsigned long adr, int len, void *thunk)
2637 {
2638 struct cfi_private *cfi = map->fldrv_priv;
2639 int ret;
2640
2641 mutex_lock(&chip->mutex);
2642 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2643 if (ret)
2644 goto out_unlock;
2645 chip->state = FL_LOCKING;
2646
2647 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2648
2649 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2650 cfi->device_type, NULL);
2651 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2652 cfi->device_type, NULL);
2653 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2654 cfi->device_type, NULL);
2655 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2656 cfi->device_type, NULL);
2657 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2658 cfi->device_type, NULL);
2659 map_write(map, CMD(0x40), chip->start + adr);
2660
2661 chip->state = FL_READY;
2662 put_chip(map, chip, adr + chip->start);
2663 ret = 0;
2664
2665 out_unlock:
2666 mutex_unlock(&chip->mutex);
2667 return ret;
2668 }
2669
do_atmel_unlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2670 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2671 unsigned long adr, int len, void *thunk)
2672 {
2673 struct cfi_private *cfi = map->fldrv_priv;
2674 int ret;
2675
2676 mutex_lock(&chip->mutex);
2677 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2678 if (ret)
2679 goto out_unlock;
2680 chip->state = FL_UNLOCKING;
2681
2682 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2683
2684 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2685 cfi->device_type, NULL);
2686 map_write(map, CMD(0x70), adr);
2687
2688 chip->state = FL_READY;
2689 put_chip(map, chip, adr + chip->start);
2690 ret = 0;
2691
2692 out_unlock:
2693 mutex_unlock(&chip->mutex);
2694 return ret;
2695 }
2696
cfi_atmel_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2697 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2698 {
2699 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2700 }
2701
cfi_atmel_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2702 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2703 {
2704 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2705 }
2706
2707 /*
2708 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2709 */
2710
2711 struct ppb_lock {
2712 struct flchip *chip;
2713 unsigned long adr;
2714 int locked;
2715 };
2716
2717 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2718 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2719 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2720
do_ppb_xxlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2721 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2722 struct flchip *chip,
2723 unsigned long adr, int len, void *thunk)
2724 {
2725 struct cfi_private *cfi = map->fldrv_priv;
2726 unsigned long timeo;
2727 int ret;
2728
2729 adr += chip->start;
2730 mutex_lock(&chip->mutex);
2731 ret = get_chip(map, chip, adr, FL_LOCKING);
2732 if (ret) {
2733 mutex_unlock(&chip->mutex);
2734 return ret;
2735 }
2736
2737 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2738
2739 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2740 cfi->device_type, NULL);
2741 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2742 cfi->device_type, NULL);
2743 /* PPB entry command */
2744 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2745 cfi->device_type, NULL);
2746
2747 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2748 chip->state = FL_LOCKING;
2749 map_write(map, CMD(0xA0), adr);
2750 map_write(map, CMD(0x00), adr);
2751 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2752 /*
2753 * Unlocking of one specific sector is not supported, so we
2754 * have to unlock all sectors of this device instead
2755 */
2756 chip->state = FL_UNLOCKING;
2757 map_write(map, CMD(0x80), chip->start);
2758 map_write(map, CMD(0x30), chip->start);
2759 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2760 chip->state = FL_JEDEC_QUERY;
2761 /* Return locked status: 0->locked, 1->unlocked */
2762 ret = !cfi_read_query(map, adr);
2763 } else
2764 BUG();
2765
2766 /*
2767 * Wait for some time as unlocking of all sectors takes quite long
2768 */
2769 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2770 for (;;) {
2771 if (chip_ready(map, chip, adr))
2772 break;
2773
2774 if (time_after(jiffies, timeo)) {
2775 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2776 ret = -EIO;
2777 break;
2778 }
2779
2780 UDELAY(map, chip, adr, 1);
2781 }
2782
2783 /* Exit BC commands */
2784 map_write(map, CMD(0x90), chip->start);
2785 map_write(map, CMD(0x00), chip->start);
2786
2787 chip->state = FL_READY;
2788 put_chip(map, chip, adr);
2789 mutex_unlock(&chip->mutex);
2790
2791 return ret;
2792 }
2793
cfi_ppb_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2794 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2795 uint64_t len)
2796 {
2797 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2798 DO_XXLOCK_ONEBLOCK_LOCK);
2799 }
2800
cfi_ppb_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2801 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2802 uint64_t len)
2803 {
2804 struct mtd_erase_region_info *regions = mtd->eraseregions;
2805 struct map_info *map = mtd->priv;
2806 struct cfi_private *cfi = map->fldrv_priv;
2807 struct ppb_lock *sect;
2808 unsigned long adr;
2809 loff_t offset;
2810 uint64_t length;
2811 int chipnum;
2812 int i;
2813 int sectors;
2814 int ret;
2815 int max_sectors;
2816
2817 /*
2818 * PPB unlocking always unlocks all sectors of the flash chip.
2819 * We need to re-lock all previously locked sectors. So lets
2820 * first check the locking status of all sectors and save
2821 * it for future use.
2822 */
2823 max_sectors = 0;
2824 for (i = 0; i < mtd->numeraseregions; i++)
2825 max_sectors += regions[i].numblocks;
2826
2827 sect = kcalloc(max_sectors, sizeof(struct ppb_lock), GFP_KERNEL);
2828 if (!sect)
2829 return -ENOMEM;
2830
2831 /*
2832 * This code to walk all sectors is a slightly modified version
2833 * of the cfi_varsize_frob() code.
2834 */
2835 i = 0;
2836 chipnum = 0;
2837 adr = 0;
2838 sectors = 0;
2839 offset = 0;
2840 length = mtd->size;
2841
2842 while (length) {
2843 int size = regions[i].erasesize;
2844
2845 /*
2846 * Only test sectors that shall not be unlocked. The other
2847 * sectors shall be unlocked, so lets keep their locking
2848 * status at "unlocked" (locked=0) for the final re-locking.
2849 */
2850 if ((offset < ofs) || (offset >= (ofs + len))) {
2851 sect[sectors].chip = &cfi->chips[chipnum];
2852 sect[sectors].adr = adr;
2853 sect[sectors].locked = do_ppb_xxlock(
2854 map, &cfi->chips[chipnum], adr, 0,
2855 DO_XXLOCK_ONEBLOCK_GETLOCK);
2856 }
2857
2858 adr += size;
2859 offset += size;
2860 length -= size;
2861
2862 if (offset == regions[i].offset + size * regions[i].numblocks)
2863 i++;
2864
2865 if (adr >> cfi->chipshift) {
2866 if (offset >= (ofs + len))
2867 break;
2868 adr = 0;
2869 chipnum++;
2870
2871 if (chipnum >= cfi->numchips)
2872 break;
2873 }
2874
2875 sectors++;
2876 if (sectors >= max_sectors) {
2877 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2878 max_sectors);
2879 kfree(sect);
2880 return -EINVAL;
2881 }
2882 }
2883
2884 /* Now unlock the whole chip */
2885 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2886 DO_XXLOCK_ONEBLOCK_UNLOCK);
2887 if (ret) {
2888 kfree(sect);
2889 return ret;
2890 }
2891
2892 /*
2893 * PPB unlocking always unlocks all sectors of the flash chip.
2894 * We need to re-lock all previously locked sectors.
2895 */
2896 for (i = 0; i < sectors; i++) {
2897 if (sect[i].locked)
2898 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2899 DO_XXLOCK_ONEBLOCK_LOCK);
2900 }
2901
2902 kfree(sect);
2903 return ret;
2904 }
2905
cfi_ppb_is_locked(struct mtd_info * mtd,loff_t ofs,uint64_t len)2906 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2907 uint64_t len)
2908 {
2909 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2910 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2911 }
2912
cfi_amdstd_sync(struct mtd_info * mtd)2913 static void cfi_amdstd_sync (struct mtd_info *mtd)
2914 {
2915 struct map_info *map = mtd->priv;
2916 struct cfi_private *cfi = map->fldrv_priv;
2917 int i;
2918 struct flchip *chip;
2919 int ret = 0;
2920 DECLARE_WAITQUEUE(wait, current);
2921
2922 for (i=0; !ret && i<cfi->numchips; i++) {
2923 chip = &cfi->chips[i];
2924
2925 retry:
2926 mutex_lock(&chip->mutex);
2927
2928 switch(chip->state) {
2929 case FL_READY:
2930 case FL_STATUS:
2931 case FL_CFI_QUERY:
2932 case FL_JEDEC_QUERY:
2933 chip->oldstate = chip->state;
2934 chip->state = FL_SYNCING;
2935 /* No need to wake_up() on this state change -
2936 * as the whole point is that nobody can do anything
2937 * with the chip now anyway.
2938 */
2939 /* fall through */
2940 case FL_SYNCING:
2941 mutex_unlock(&chip->mutex);
2942 break;
2943
2944 default:
2945 /* Not an idle state */
2946 set_current_state(TASK_UNINTERRUPTIBLE);
2947 add_wait_queue(&chip->wq, &wait);
2948
2949 mutex_unlock(&chip->mutex);
2950
2951 schedule();
2952
2953 remove_wait_queue(&chip->wq, &wait);
2954
2955 goto retry;
2956 }
2957 }
2958
2959 /* Unlock the chips again */
2960
2961 for (i--; i >=0; i--) {
2962 chip = &cfi->chips[i];
2963
2964 mutex_lock(&chip->mutex);
2965
2966 if (chip->state == FL_SYNCING) {
2967 chip->state = chip->oldstate;
2968 wake_up(&chip->wq);
2969 }
2970 mutex_unlock(&chip->mutex);
2971 }
2972 }
2973
2974
cfi_amdstd_suspend(struct mtd_info * mtd)2975 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2976 {
2977 struct map_info *map = mtd->priv;
2978 struct cfi_private *cfi = map->fldrv_priv;
2979 int i;
2980 struct flchip *chip;
2981 int ret = 0;
2982
2983 for (i=0; !ret && i<cfi->numchips; i++) {
2984 chip = &cfi->chips[i];
2985
2986 mutex_lock(&chip->mutex);
2987
2988 switch(chip->state) {
2989 case FL_READY:
2990 case FL_STATUS:
2991 case FL_CFI_QUERY:
2992 case FL_JEDEC_QUERY:
2993 chip->oldstate = chip->state;
2994 chip->state = FL_PM_SUSPENDED;
2995 /* No need to wake_up() on this state change -
2996 * as the whole point is that nobody can do anything
2997 * with the chip now anyway.
2998 */
2999 case FL_PM_SUSPENDED:
3000 break;
3001
3002 default:
3003 ret = -EAGAIN;
3004 break;
3005 }
3006 mutex_unlock(&chip->mutex);
3007 }
3008
3009 /* Unlock the chips again */
3010
3011 if (ret) {
3012 for (i--; i >=0; i--) {
3013 chip = &cfi->chips[i];
3014
3015 mutex_lock(&chip->mutex);
3016
3017 if (chip->state == FL_PM_SUSPENDED) {
3018 chip->state = chip->oldstate;
3019 wake_up(&chip->wq);
3020 }
3021 mutex_unlock(&chip->mutex);
3022 }
3023 }
3024
3025 return ret;
3026 }
3027
3028
cfi_amdstd_resume(struct mtd_info * mtd)3029 static void cfi_amdstd_resume(struct mtd_info *mtd)
3030 {
3031 struct map_info *map = mtd->priv;
3032 struct cfi_private *cfi = map->fldrv_priv;
3033 int i;
3034 struct flchip *chip;
3035
3036 for (i=0; i<cfi->numchips; i++) {
3037
3038 chip = &cfi->chips[i];
3039
3040 mutex_lock(&chip->mutex);
3041
3042 if (chip->state == FL_PM_SUSPENDED) {
3043 chip->state = FL_READY;
3044 map_write(map, CMD(0xF0), chip->start);
3045 wake_up(&chip->wq);
3046 }
3047 else
3048 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
3049
3050 mutex_unlock(&chip->mutex);
3051 }
3052 }
3053
3054
3055 /*
3056 * Ensure that the flash device is put back into read array mode before
3057 * unloading the driver or rebooting. On some systems, rebooting while
3058 * the flash is in query/program/erase mode will prevent the CPU from
3059 * fetching the bootloader code, requiring a hard reset or power cycle.
3060 */
cfi_amdstd_reset(struct mtd_info * mtd)3061 static int cfi_amdstd_reset(struct mtd_info *mtd)
3062 {
3063 struct map_info *map = mtd->priv;
3064 struct cfi_private *cfi = map->fldrv_priv;
3065 int i, ret;
3066 struct flchip *chip;
3067
3068 for (i = 0; i < cfi->numchips; i++) {
3069
3070 chip = &cfi->chips[i];
3071
3072 mutex_lock(&chip->mutex);
3073
3074 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
3075 if (!ret) {
3076 map_write(map, CMD(0xF0), chip->start);
3077 chip->state = FL_SHUTDOWN;
3078 put_chip(map, chip, chip->start);
3079 }
3080
3081 mutex_unlock(&chip->mutex);
3082 }
3083
3084 return 0;
3085 }
3086
3087
cfi_amdstd_reboot(struct notifier_block * nb,unsigned long val,void * v)3088 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
3089 void *v)
3090 {
3091 struct mtd_info *mtd;
3092
3093 mtd = container_of(nb, struct mtd_info, reboot_notifier);
3094 cfi_amdstd_reset(mtd);
3095 return NOTIFY_DONE;
3096 }
3097
3098
cfi_amdstd_destroy(struct mtd_info * mtd)3099 static void cfi_amdstd_destroy(struct mtd_info *mtd)
3100 {
3101 struct map_info *map = mtd->priv;
3102 struct cfi_private *cfi = map->fldrv_priv;
3103
3104 cfi_amdstd_reset(mtd);
3105 unregister_reboot_notifier(&mtd->reboot_notifier);
3106 kfree(cfi->cmdset_priv);
3107 kfree(cfi->cfiq);
3108 kfree(cfi);
3109 kfree(mtd->eraseregions);
3110 }
3111
3112 MODULE_LICENSE("GPL");
3113 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
3114 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
3115 MODULE_ALIAS("cfi_cmdset_0006");
3116 MODULE_ALIAS("cfi_cmdset_0701");
3117