1 // SPDX-License-Identifier: GPL-2.0
2 // SPI to CAN driver for the Texas Instruments TCAN4x5x
3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
4
5 #include <linux/regmap.h>
6 #include <linux/spi/spi.h>
7
8 #include <linux/regulator/consumer.h>
9 #include <linux/gpio/consumer.h>
10
11 #include "m_can.h"
12
13 #define DEVICE_NAME "tcan4x5x"
14 #define TCAN4X5X_EXT_CLK_DEF 40000000
15
16 #define TCAN4X5X_DEV_ID0 0x00
17 #define TCAN4X5X_DEV_ID1 0x04
18 #define TCAN4X5X_REV 0x08
19 #define TCAN4X5X_STATUS 0x0C
20 #define TCAN4X5X_ERROR_STATUS 0x10
21 #define TCAN4X5X_CONTROL 0x14
22
23 #define TCAN4X5X_CONFIG 0x800
24 #define TCAN4X5X_TS_PRESCALE 0x804
25 #define TCAN4X5X_TEST_REG 0x808
26 #define TCAN4X5X_INT_FLAGS 0x820
27 #define TCAN4X5X_MCAN_INT_REG 0x824
28 #define TCAN4X5X_INT_EN 0x830
29
30 /* Interrupt bits */
31 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
32 #define TCAN4X5X_CANHCANL_INT_EN BIT(29)
33 #define TCAN4X5X_CANHBAT_INT_EN BIT(28)
34 #define TCAN4X5X_CANLGND_INT_EN BIT(27)
35 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
36 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
37 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
38 #define TCAN4X5X_UVSUP_INT_EN BIT(22)
39 #define TCAN4X5X_UVIO_INT_EN BIT(21)
40 #define TCAN4X5X_TSD_INT_EN BIT(19)
41 #define TCAN4X5X_ECCERR_INT_EN BIT(16)
42 #define TCAN4X5X_CANINT_INT_EN BIT(15)
43 #define TCAN4X5X_LWU_INT_EN BIT(14)
44 #define TCAN4X5X_CANSLNT_INT_EN BIT(10)
45 #define TCAN4X5X_CANDOM_INT_EN BIT(8)
46 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
47 #define TCAN4X5X_BUS_FAULT BIT(4)
48 #define TCAN4X5X_MCAN_INT BIT(1)
49 #define TCAN4X5X_ENABLE_TCAN_INT \
50 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
51 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
52
53 /* MCAN Interrupt bits */
54 #define TCAN4X5X_MCAN_IR_ARA BIT(29)
55 #define TCAN4X5X_MCAN_IR_PED BIT(28)
56 #define TCAN4X5X_MCAN_IR_PEA BIT(27)
57 #define TCAN4X5X_MCAN_IR_WD BIT(26)
58 #define TCAN4X5X_MCAN_IR_BO BIT(25)
59 #define TCAN4X5X_MCAN_IR_EW BIT(24)
60 #define TCAN4X5X_MCAN_IR_EP BIT(23)
61 #define TCAN4X5X_MCAN_IR_ELO BIT(22)
62 #define TCAN4X5X_MCAN_IR_BEU BIT(21)
63 #define TCAN4X5X_MCAN_IR_BEC BIT(20)
64 #define TCAN4X5X_MCAN_IR_DRX BIT(19)
65 #define TCAN4X5X_MCAN_IR_TOO BIT(18)
66 #define TCAN4X5X_MCAN_IR_MRAF BIT(17)
67 #define TCAN4X5X_MCAN_IR_TSW BIT(16)
68 #define TCAN4X5X_MCAN_IR_TEFL BIT(15)
69 #define TCAN4X5X_MCAN_IR_TEFF BIT(14)
70 #define TCAN4X5X_MCAN_IR_TEFW BIT(13)
71 #define TCAN4X5X_MCAN_IR_TEFN BIT(12)
72 #define TCAN4X5X_MCAN_IR_TFE BIT(11)
73 #define TCAN4X5X_MCAN_IR_TCF BIT(10)
74 #define TCAN4X5X_MCAN_IR_TC BIT(9)
75 #define TCAN4X5X_MCAN_IR_HPM BIT(8)
76 #define TCAN4X5X_MCAN_IR_RF1L BIT(7)
77 #define TCAN4X5X_MCAN_IR_RF1F BIT(6)
78 #define TCAN4X5X_MCAN_IR_RF1W BIT(5)
79 #define TCAN4X5X_MCAN_IR_RF1N BIT(4)
80 #define TCAN4X5X_MCAN_IR_RF0L BIT(3)
81 #define TCAN4X5X_MCAN_IR_RF0F BIT(2)
82 #define TCAN4X5X_MCAN_IR_RF0W BIT(1)
83 #define TCAN4X5X_MCAN_IR_RF0N BIT(0)
84 #define TCAN4X5X_ENABLE_MCAN_INT \
85 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
86 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
87 TCAN4X5X_MCAN_IR_RF1F)
88
89 #define TCAN4X5X_MRAM_START 0x8000
90 #define TCAN4X5X_MCAN_OFFSET 0x1000
91 #define TCAN4X5X_MAX_REGISTER 0x8fff
92
93 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
94 #define TCAN4X5X_SET_ALL_INT 0xffffffff
95
96 #define TCAN4X5X_WRITE_CMD (0x61 << 24)
97 #define TCAN4X5X_READ_CMD (0x41 << 24)
98
99 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
100 #define TCAN4X5X_MODE_SLEEP 0x00
101 #define TCAN4X5X_MODE_STANDBY BIT(6)
102 #define TCAN4X5X_MODE_NORMAL BIT(7)
103
104 #define TCAN4X5X_SW_RESET BIT(2)
105
106 #define TCAN4X5X_MCAN_CONFIGURED BIT(5)
107 #define TCAN4X5X_WATCHDOG_EN BIT(3)
108 #define TCAN4X5X_WD_60_MS_TIMER 0
109 #define TCAN4X5X_WD_600_MS_TIMER BIT(28)
110 #define TCAN4X5X_WD_3_S_TIMER BIT(29)
111 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
112
113 struct tcan4x5x_priv {
114 struct regmap *regmap;
115 struct spi_device *spi;
116
117 struct m_can_classdev *mcan_dev;
118
119 struct gpio_desc *reset_gpio;
120 struct gpio_desc *device_wake_gpio;
121 struct gpio_desc *device_state_gpio;
122 struct regulator *power;
123
124 /* Register based ip */
125 int mram_start;
126 int reg_offset;
127 };
128
129 static struct can_bittiming_const tcan4x5x_bittiming_const = {
130 .name = DEVICE_NAME,
131 .tseg1_min = 2,
132 .tseg1_max = 31,
133 .tseg2_min = 2,
134 .tseg2_max = 16,
135 .sjw_max = 16,
136 .brp_min = 1,
137 .brp_max = 32,
138 .brp_inc = 1,
139 };
140
141 static struct can_bittiming_const tcan4x5x_data_bittiming_const = {
142 .name = DEVICE_NAME,
143 .tseg1_min = 1,
144 .tseg1_max = 32,
145 .tseg2_min = 1,
146 .tseg2_max = 16,
147 .sjw_max = 16,
148 .brp_min = 1,
149 .brp_max = 32,
150 .brp_inc = 1,
151 };
152
tcan4x5x_check_wake(struct tcan4x5x_priv * priv)153 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
154 {
155 int wake_state = 0;
156
157 if (priv->device_state_gpio)
158 wake_state = gpiod_get_value(priv->device_state_gpio);
159
160 if (priv->device_wake_gpio && wake_state) {
161 gpiod_set_value(priv->device_wake_gpio, 0);
162 usleep_range(5, 50);
163 gpiod_set_value(priv->device_wake_gpio, 1);
164 }
165 }
166
tcan4x5x_reset(struct tcan4x5x_priv * priv)167 static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
168 {
169 int ret = 0;
170
171 if (priv->reset_gpio) {
172 gpiod_set_value(priv->reset_gpio, 1);
173
174 /* tpulse_width minimum 30us */
175 usleep_range(30, 100);
176 gpiod_set_value(priv->reset_gpio, 0);
177 } else {
178 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
179 TCAN4X5X_SW_RESET);
180 if (ret)
181 return ret;
182 }
183
184 usleep_range(700, 1000);
185
186 return ret;
187 }
188
regmap_spi_gather_write(void * context,const void * reg,size_t reg_len,const void * val,size_t val_len)189 static int regmap_spi_gather_write(void *context, const void *reg,
190 size_t reg_len, const void *val,
191 size_t val_len)
192 {
193 struct device *dev = context;
194 struct spi_device *spi = to_spi_device(dev);
195 struct spi_message m;
196 u32 addr;
197 struct spi_transfer t[2] = {
198 { .tx_buf = &addr, .len = reg_len, .cs_change = 0,},
199 { .tx_buf = val, .len = val_len, },
200 };
201
202 addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2;
203
204 spi_message_init(&m);
205 spi_message_add_tail(&t[0], &m);
206 spi_message_add_tail(&t[1], &m);
207
208 return spi_sync(spi, &m);
209 }
210
tcan4x5x_regmap_write(void * context,const void * data,size_t count)211 static int tcan4x5x_regmap_write(void *context, const void *data, size_t count)
212 {
213 u16 *reg = (u16 *)(data);
214 const u32 *val = data + 4;
215
216 return regmap_spi_gather_write(context, reg, 4, val, count - 4);
217 }
218
regmap_spi_async_write(void * context,const void * reg,size_t reg_len,const void * val,size_t val_len,struct regmap_async * a)219 static int regmap_spi_async_write(void *context,
220 const void *reg, size_t reg_len,
221 const void *val, size_t val_len,
222 struct regmap_async *a)
223 {
224 return -ENOTSUPP;
225 }
226
regmap_spi_async_alloc(void)227 static struct regmap_async *regmap_spi_async_alloc(void)
228 {
229 return NULL;
230 }
231
tcan4x5x_regmap_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)232 static int tcan4x5x_regmap_read(void *context,
233 const void *reg, size_t reg_size,
234 void *val, size_t val_size)
235 {
236 struct device *dev = context;
237 struct spi_device *spi = to_spi_device(dev);
238
239 u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2;
240
241 return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size);
242 }
243
244 static struct regmap_bus tcan4x5x_bus = {
245 .write = tcan4x5x_regmap_write,
246 .gather_write = regmap_spi_gather_write,
247 .async_write = regmap_spi_async_write,
248 .async_alloc = regmap_spi_async_alloc,
249 .read = tcan4x5x_regmap_read,
250 .read_flag_mask = 0x00,
251 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
252 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
253 };
254
tcan4x5x_read_reg(struct m_can_classdev * cdev,int reg)255 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
256 {
257 struct tcan4x5x_priv *priv = cdev->device_data;
258 u32 val;
259
260 regmap_read(priv->regmap, priv->reg_offset + reg, &val);
261
262 return val;
263 }
264
tcan4x5x_read_fifo(struct m_can_classdev * cdev,int addr_offset)265 static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
266 {
267 struct tcan4x5x_priv *priv = cdev->device_data;
268 u32 val;
269
270 regmap_read(priv->regmap, priv->mram_start + addr_offset, &val);
271
272 return val;
273 }
274
tcan4x5x_write_reg(struct m_can_classdev * cdev,int reg,int val)275 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
276 {
277 struct tcan4x5x_priv *priv = cdev->device_data;
278
279 return regmap_write(priv->regmap, priv->reg_offset + reg, val);
280 }
281
tcan4x5x_write_fifo(struct m_can_classdev * cdev,int addr_offset,int val)282 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
283 int addr_offset, int val)
284 {
285 struct tcan4x5x_priv *priv = cdev->device_data;
286
287 return regmap_write(priv->regmap, priv->mram_start + addr_offset, val);
288 }
289
tcan4x5x_power_enable(struct regulator * reg,int enable)290 static int tcan4x5x_power_enable(struct regulator *reg, int enable)
291 {
292 if (IS_ERR_OR_NULL(reg))
293 return 0;
294
295 if (enable)
296 return regulator_enable(reg);
297 else
298 return regulator_disable(reg);
299 }
300
tcan4x5x_write_tcan_reg(struct m_can_classdev * cdev,int reg,int val)301 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
302 int reg, int val)
303 {
304 struct tcan4x5x_priv *priv = cdev->device_data;
305
306 return regmap_write(priv->regmap, reg, val);
307 }
308
tcan4x5x_clear_interrupts(struct m_can_classdev * cdev)309 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
310 {
311 int ret;
312
313 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
314 TCAN4X5X_CLEAR_ALL_INT);
315 if (ret)
316 return ret;
317
318 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
319 TCAN4X5X_ENABLE_MCAN_INT);
320 if (ret)
321 return ret;
322
323 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
324 TCAN4X5X_CLEAR_ALL_INT);
325 if (ret)
326 return ret;
327
328 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
329 TCAN4X5X_CLEAR_ALL_INT);
330 if (ret)
331 return ret;
332
333 return ret;
334 }
335
tcan4x5x_init(struct m_can_classdev * cdev)336 static int tcan4x5x_init(struct m_can_classdev *cdev)
337 {
338 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
339 int ret;
340
341 tcan4x5x_check_wake(tcan4x5x);
342
343 ret = tcan4x5x_clear_interrupts(cdev);
344 if (ret)
345 return ret;
346
347 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
348 TCAN4X5X_ENABLE_TCAN_INT);
349 if (ret)
350 return ret;
351
352 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
353 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
354 if (ret)
355 return ret;
356
357 /* Zero out the MCAN buffers */
358 m_can_init_ram(cdev);
359
360 return ret;
361 }
362
tcan4x5x_parse_config(struct m_can_classdev * cdev)363 static int tcan4x5x_parse_config(struct m_can_classdev *cdev)
364 {
365 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
366 int ret;
367
368 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
369 GPIOD_OUT_HIGH);
370 if (IS_ERR(tcan4x5x->device_wake_gpio)) {
371 dev_err(cdev->dev, "device-wake gpio not defined\n");
372 return -EINVAL;
373 }
374
375 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
376 GPIOD_OUT_LOW);
377 if (IS_ERR(tcan4x5x->reset_gpio))
378 tcan4x5x->reset_gpio = NULL;
379
380 ret = tcan4x5x_reset(tcan4x5x);
381 if (ret)
382 return ret;
383
384 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
385 "device-state",
386 GPIOD_IN);
387 if (IS_ERR(tcan4x5x->device_state_gpio))
388 tcan4x5x->device_state_gpio = NULL;
389
390 tcan4x5x->power = devm_regulator_get_optional(cdev->dev,
391 "vsup");
392 if (PTR_ERR(tcan4x5x->power) == -EPROBE_DEFER)
393 return -EPROBE_DEFER;
394
395 return 0;
396 }
397
398 static const struct regmap_config tcan4x5x_regmap = {
399 .reg_bits = 32,
400 .val_bits = 32,
401 .cache_type = REGCACHE_NONE,
402 .max_register = TCAN4X5X_MAX_REGISTER,
403 };
404
405 static struct m_can_ops tcan4x5x_ops = {
406 .init = tcan4x5x_init,
407 .read_reg = tcan4x5x_read_reg,
408 .write_reg = tcan4x5x_write_reg,
409 .write_fifo = tcan4x5x_write_fifo,
410 .read_fifo = tcan4x5x_read_fifo,
411 .clear_interrupts = tcan4x5x_clear_interrupts,
412 };
413
tcan4x5x_can_probe(struct spi_device * spi)414 static int tcan4x5x_can_probe(struct spi_device *spi)
415 {
416 struct tcan4x5x_priv *priv;
417 struct m_can_classdev *mcan_class;
418 int freq, ret;
419
420 mcan_class = m_can_class_allocate_dev(&spi->dev);
421 if (!mcan_class)
422 return -ENOMEM;
423
424 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
425 if (!priv)
426 return -ENOMEM;
427
428 mcan_class->device_data = priv;
429
430 m_can_class_get_clocks(mcan_class);
431 if (IS_ERR(mcan_class->cclk)) {
432 dev_err(&spi->dev, "no CAN clock source defined\n");
433 freq = TCAN4X5X_EXT_CLK_DEF;
434 } else {
435 freq = clk_get_rate(mcan_class->cclk);
436 }
437
438 /* Sanity check */
439 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF)
440 return -ERANGE;
441
442 priv->reg_offset = TCAN4X5X_MCAN_OFFSET;
443 priv->mram_start = TCAN4X5X_MRAM_START;
444 priv->spi = spi;
445 priv->mcan_dev = mcan_class;
446
447 mcan_class->pm_clock_support = 0;
448 mcan_class->can.clock.freq = freq;
449 mcan_class->dev = &spi->dev;
450 mcan_class->ops = &tcan4x5x_ops;
451 mcan_class->is_peripheral = true;
452 mcan_class->bit_timing = &tcan4x5x_bittiming_const;
453 mcan_class->data_timing = &tcan4x5x_data_bittiming_const;
454 mcan_class->net->irq = spi->irq;
455
456 spi_set_drvdata(spi, priv);
457
458 ret = tcan4x5x_parse_config(mcan_class);
459 if (ret)
460 goto out_clk;
461
462 /* Configure the SPI bus */
463 spi->bits_per_word = 32;
464 ret = spi_setup(spi);
465 if (ret)
466 goto out_clk;
467
468 priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
469 &spi->dev, &tcan4x5x_regmap);
470
471 tcan4x5x_power_enable(priv->power, 1);
472
473 ret = tcan4x5x_init(mcan_class);
474 if (ret)
475 goto out_power;
476
477 ret = m_can_class_register(mcan_class);
478 if (ret)
479 goto out_power;
480
481 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
482 return 0;
483
484 out_power:
485 tcan4x5x_power_enable(priv->power, 0);
486 out_clk:
487 if (!IS_ERR(mcan_class->cclk)) {
488 clk_disable_unprepare(mcan_class->cclk);
489 clk_disable_unprepare(mcan_class->hclk);
490 }
491
492 dev_err(&spi->dev, "Probe failed, err=%d\n", ret);
493 return ret;
494 }
495
tcan4x5x_can_remove(struct spi_device * spi)496 static int tcan4x5x_can_remove(struct spi_device *spi)
497 {
498 struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
499
500 tcan4x5x_power_enable(priv->power, 0);
501
502 m_can_class_unregister(priv->mcan_dev);
503
504 return 0;
505 }
506
507 static const struct of_device_id tcan4x5x_of_match[] = {
508 { .compatible = "ti,tcan4x5x", },
509 { }
510 };
511 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
512
513 static const struct spi_device_id tcan4x5x_id_table[] = {
514 {
515 .name = "tcan4x5x",
516 .driver_data = 0,
517 },
518 { }
519 };
520 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
521
522 static struct spi_driver tcan4x5x_can_driver = {
523 .driver = {
524 .name = DEVICE_NAME,
525 .of_match_table = tcan4x5x_of_match,
526 .pm = NULL,
527 },
528 .id_table = tcan4x5x_id_table,
529 .probe = tcan4x5x_can_probe,
530 .remove = tcan4x5x_can_remove,
531 };
532 module_spi_driver(tcan4x5x_can_driver);
533
534 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
535 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
536 MODULE_LICENSE("GPL v2");
537