1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "pinctrl-intel.h"
28
29 /* memory mapped register offsets */
30 #define BYT_CONF0_REG 0x000
31 #define BYT_CONF1_REG 0x004
32 #define BYT_VAL_REG 0x008
33 #define BYT_DFT_REG 0x00c
34 #define BYT_INT_STAT_REG 0x800
35 #define BYT_DEBOUNCE_REG 0x9d0
36
37 /* BYT_CONF0_REG register bits */
38 #define BYT_IODEN BIT(31)
39 #define BYT_DIRECT_IRQ_EN BIT(27)
40 #define BYT_TRIG_MASK GENMASK(26, 24)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_DEBOUNCE_EN BIT(20)
45 #define BYT_GLITCH_FILTER_EN BIT(19)
46 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
47 #define BYT_GLITCH_F_FAST_CLK BIT(16)
48 #define BYT_PULL_STR_SHIFT 9
49 #define BYT_PULL_STR_MASK GENMASK(10, 9)
50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_ASSIGN_SHIFT 7
55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PIN_MUX GENMASK(2, 0)
59
60 /* BYT_VAL_REG register bits */
61 #define BYT_DIR_MASK GENMASK(2, 1)
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
65
66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68
69 /* BYT_DEBOUNCE_REG bits */
70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
71 #define BYT_DEBOUNCE_PULSE_375US 1
72 #define BYT_DEBOUNCE_PULSE_750US 2
73 #define BYT_DEBOUNCE_PULSE_1500US 3
74 #define BYT_DEBOUNCE_PULSE_3MS 4
75 #define BYT_DEBOUNCE_PULSE_6MS 5
76 #define BYT_DEBOUNCE_PULSE_12MS 6
77 #define BYT_DEBOUNCE_PULSE_24MS 7
78
79 #define BYT_NGPIO_SCORE 102
80 #define BYT_NGPIO_NCORE 28
81 #define BYT_NGPIO_SUS 44
82
83 #define BYT_SCORE_ACPI_UID "1"
84 #define BYT_NCORE_ACPI_UID "2"
85 #define BYT_SUS_ACPI_UID "3"
86
87 /*
88 * This is the function value most pins have for GPIO muxing. If the value
89 * differs from the default one, it must be explicitly mentioned. Otherwise, the
90 * pin control implementation will set the muxing value to default GPIO if it
91 * does not find a match for the requested function.
92 */
93 #define BYT_DEFAULT_GPIO_MUX 0
94 #define BYT_ALTER_GPIO_MUX 1
95
96 struct byt_gpio_pin_context {
97 u32 conf0;
98 u32 val;
99 };
100
101 #define COMMUNITY(p, n, map) \
102 { \
103 .pin_base = (p), \
104 .npins = (n), \
105 .pad_map = (map),\
106 }
107
108 struct byt_gpio {
109 struct gpio_chip chip;
110 struct platform_device *pdev;
111 struct pinctrl_dev *pctl_dev;
112 struct pinctrl_desc pctl_desc;
113 const struct intel_pinctrl_soc_data *soc_data;
114 struct intel_community *communities_copy;
115 struct byt_gpio_pin_context *saved_context;
116 };
117
118 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
119 static const struct pinctrl_pin_desc byt_score_pins[] = {
120 PINCTRL_PIN(0, "SATA_GP0"),
121 PINCTRL_PIN(1, "SATA_GP1"),
122 PINCTRL_PIN(2, "SATA_LED#"),
123 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
124 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
125 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
126 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
127 PINCTRL_PIN(7, "SD3_WP"),
128 PINCTRL_PIN(8, "HDA_RST"),
129 PINCTRL_PIN(9, "HDA_SYNC"),
130 PINCTRL_PIN(10, "HDA_CLK"),
131 PINCTRL_PIN(11, "HDA_SDO"),
132 PINCTRL_PIN(12, "HDA_SDI0"),
133 PINCTRL_PIN(13, "HDA_SDI1"),
134 PINCTRL_PIN(14, "GPIO_S0_SC14"),
135 PINCTRL_PIN(15, "GPIO_S0_SC15"),
136 PINCTRL_PIN(16, "MMC1_CLK"),
137 PINCTRL_PIN(17, "MMC1_D0"),
138 PINCTRL_PIN(18, "MMC1_D1"),
139 PINCTRL_PIN(19, "MMC1_D2"),
140 PINCTRL_PIN(20, "MMC1_D3"),
141 PINCTRL_PIN(21, "MMC1_D4"),
142 PINCTRL_PIN(22, "MMC1_D5"),
143 PINCTRL_PIN(23, "MMC1_D6"),
144 PINCTRL_PIN(24, "MMC1_D7"),
145 PINCTRL_PIN(25, "MMC1_CMD"),
146 PINCTRL_PIN(26, "MMC1_RST"),
147 PINCTRL_PIN(27, "SD2_CLK"),
148 PINCTRL_PIN(28, "SD2_D0"),
149 PINCTRL_PIN(29, "SD2_D1"),
150 PINCTRL_PIN(30, "SD2_D2"),
151 PINCTRL_PIN(31, "SD2_D3_CD"),
152 PINCTRL_PIN(32, "SD2_CMD"),
153 PINCTRL_PIN(33, "SD3_CLK"),
154 PINCTRL_PIN(34, "SD3_D0"),
155 PINCTRL_PIN(35, "SD3_D1"),
156 PINCTRL_PIN(36, "SD3_D2"),
157 PINCTRL_PIN(37, "SD3_D3"),
158 PINCTRL_PIN(38, "SD3_CD"),
159 PINCTRL_PIN(39, "SD3_CMD"),
160 PINCTRL_PIN(40, "SD3_1P8EN"),
161 PINCTRL_PIN(41, "SD3_PWREN#"),
162 PINCTRL_PIN(42, "ILB_LPC_AD0"),
163 PINCTRL_PIN(43, "ILB_LPC_AD1"),
164 PINCTRL_PIN(44, "ILB_LPC_AD2"),
165 PINCTRL_PIN(45, "ILB_LPC_AD3"),
166 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
167 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
168 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
169 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
170 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
171 PINCTRL_PIN(51, "PCU_SMB_DATA"),
172 PINCTRL_PIN(52, "PCU_SMB_CLK"),
173 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
174 PINCTRL_PIN(54, "ILB_8254_SPKR"),
175 PINCTRL_PIN(55, "GPIO_S0_SC55"),
176 PINCTRL_PIN(56, "GPIO_S0_SC56"),
177 PINCTRL_PIN(57, "GPIO_S0_SC57"),
178 PINCTRL_PIN(58, "GPIO_S0_SC58"),
179 PINCTRL_PIN(59, "GPIO_S0_SC59"),
180 PINCTRL_PIN(60, "GPIO_S0_SC60"),
181 PINCTRL_PIN(61, "GPIO_S0_SC61"),
182 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
183 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
184 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
185 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
186 PINCTRL_PIN(66, "SIO_SPI_CS"),
187 PINCTRL_PIN(67, "SIO_SPI_MISO"),
188 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
189 PINCTRL_PIN(69, "SIO_SPI_CLK"),
190 PINCTRL_PIN(70, "SIO_UART1_RXD"),
191 PINCTRL_PIN(71, "SIO_UART1_TXD"),
192 PINCTRL_PIN(72, "SIO_UART1_RTS"),
193 PINCTRL_PIN(73, "SIO_UART1_CTS"),
194 PINCTRL_PIN(74, "SIO_UART2_RXD"),
195 PINCTRL_PIN(75, "SIO_UART2_TXD"),
196 PINCTRL_PIN(76, "SIO_UART2_RTS"),
197 PINCTRL_PIN(77, "SIO_UART2_CTS"),
198 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
199 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
200 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
201 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
202 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
203 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
204 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
205 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
206 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
207 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
208 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
209 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
210 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
211 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
212 PINCTRL_PIN(92, "GPIO_S0_SC92"),
213 PINCTRL_PIN(93, "GPIO_S0_SC93"),
214 PINCTRL_PIN(94, "SIO_PWM0"),
215 PINCTRL_PIN(95, "SIO_PWM1"),
216 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
217 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
218 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
219 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
220 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
221 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
222 };
223
224 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
225 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
226 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
227 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
228 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
229 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
230 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
231 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
232 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
233 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
234 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
235 97, 100,
236 };
237
238 /* SCORE groups */
239 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
240 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
241
242 static const unsigned int byt_score_pwm0_pins[] = { 94 };
243 static const unsigned int byt_score_pwm1_pins[] = { 95 };
244
245 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
246
247 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
248 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
249 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
250 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
251 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
252 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
253 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
254
255 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
256 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
257 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
258
259 static const unsigned int byt_score_sdcard_pins[] = {
260 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
261 };
262 static const unsigned int byt_score_sdcard_mux_values[] = {
263 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
264 };
265
266 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
267
268 static const unsigned int byt_score_emmc_pins[] = {
269 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
270 };
271
272 static const unsigned int byt_score_ilb_lpc_pins[] = {
273 42, 43, 44, 45, 46, 47, 48, 49, 50,
274 };
275
276 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
277
278 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
279 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
280 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
281 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
282 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
283 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
284
285 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
286
287 static const struct intel_pingroup byt_score_groups[] = {
288 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
289 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
290 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
291 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
292 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
293 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
294 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
295 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
296 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
297 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
298 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
299 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
300 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
301 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
302 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
303 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
304 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
305 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
306 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
307 PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
308 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
309 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
310 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
311 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
312 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
313 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
314 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
315 };
316
317 static const char * const byt_score_uart_groups[] = {
318 "uart1_grp", "uart2_grp",
319 };
320 static const char * const byt_score_pwm_groups[] = {
321 "pwm0_grp", "pwm1_grp",
322 };
323 static const char * const byt_score_ssp_groups[] = {
324 "ssp0_grp", "ssp1_grp", "ssp2_grp",
325 };
326 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
327 static const char * const byt_score_i2c_groups[] = {
328 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
329 "i2c6_grp",
330 };
331 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
332 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
333 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
334 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
335 static const char * const byt_score_sata_groups[] = { "sata_grp" };
336 static const char * const byt_score_plt_clk_groups[] = {
337 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
338 "plt_clk4_grp", "plt_clk5_grp",
339 };
340 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
341 static const char * const byt_score_gpio_groups[] = {
342 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
343 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
344 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
345 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
346 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
347 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
348 };
349
350 static const struct intel_function byt_score_functions[] = {
351 FUNCTION("uart", byt_score_uart_groups),
352 FUNCTION("pwm", byt_score_pwm_groups),
353 FUNCTION("ssp", byt_score_ssp_groups),
354 FUNCTION("spi", byt_score_spi_groups),
355 FUNCTION("i2c", byt_score_i2c_groups),
356 FUNCTION("sdcard", byt_score_sdcard_groups),
357 FUNCTION("sdio", byt_score_sdio_groups),
358 FUNCTION("emmc", byt_score_emmc_groups),
359 FUNCTION("lpc", byt_score_lpc_groups),
360 FUNCTION("sata", byt_score_sata_groups),
361 FUNCTION("plt_clk", byt_score_plt_clk_groups),
362 FUNCTION("smbus", byt_score_smbus_groups),
363 FUNCTION("gpio", byt_score_gpio_groups),
364 };
365
366 static const struct intel_community byt_score_communities[] = {
367 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
368 };
369
370 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
371 .uid = BYT_SCORE_ACPI_UID,
372 .pins = byt_score_pins,
373 .npins = ARRAY_SIZE(byt_score_pins),
374 .groups = byt_score_groups,
375 .ngroups = ARRAY_SIZE(byt_score_groups),
376 .functions = byt_score_functions,
377 .nfunctions = ARRAY_SIZE(byt_score_functions),
378 .communities = byt_score_communities,
379 .ncommunities = ARRAY_SIZE(byt_score_communities),
380 };
381
382 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
383 static const struct pinctrl_pin_desc byt_sus_pins[] = {
384 PINCTRL_PIN(0, "GPIO_S50"),
385 PINCTRL_PIN(1, "GPIO_S51"),
386 PINCTRL_PIN(2, "GPIO_S52"),
387 PINCTRL_PIN(3, "GPIO_S53"),
388 PINCTRL_PIN(4, "GPIO_S54"),
389 PINCTRL_PIN(5, "GPIO_S55"),
390 PINCTRL_PIN(6, "GPIO_S56"),
391 PINCTRL_PIN(7, "GPIO_S57"),
392 PINCTRL_PIN(8, "GPIO_S58"),
393 PINCTRL_PIN(9, "GPIO_S59"),
394 PINCTRL_PIN(10, "GPIO_S510"),
395 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
396 PINCTRL_PIN(12, "PMC_SUSCLK0"),
397 PINCTRL_PIN(13, "GPIO_S513"),
398 PINCTRL_PIN(14, "USB_ULPI_RST"),
399 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
400 PINCTRL_PIN(16, "PMC_PWRBTN"),
401 PINCTRL_PIN(17, "GPIO_S517"),
402 PINCTRL_PIN(18, "PMC_SUS_STAT"),
403 PINCTRL_PIN(19, "USB_OC0"),
404 PINCTRL_PIN(20, "USB_OC1"),
405 PINCTRL_PIN(21, "PCU_SPI_CS1"),
406 PINCTRL_PIN(22, "GPIO_S522"),
407 PINCTRL_PIN(23, "GPIO_S523"),
408 PINCTRL_PIN(24, "GPIO_S524"),
409 PINCTRL_PIN(25, "GPIO_S525"),
410 PINCTRL_PIN(26, "GPIO_S526"),
411 PINCTRL_PIN(27, "GPIO_S527"),
412 PINCTRL_PIN(28, "GPIO_S528"),
413 PINCTRL_PIN(29, "GPIO_S529"),
414 PINCTRL_PIN(30, "GPIO_S530"),
415 PINCTRL_PIN(31, "USB_ULPI_CLK"),
416 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
417 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
418 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
419 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
420 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
421 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
422 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
423 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
424 PINCTRL_PIN(40, "USB_ULPI_DIR"),
425 PINCTRL_PIN(41, "USB_ULPI_NXT"),
426 PINCTRL_PIN(42, "USB_ULPI_STP"),
427 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
428 };
429
430 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
431 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
432 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
433 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
434 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
435 52, 53, 59, 40,
436 };
437
438 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
439 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
440 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
441
442 static const unsigned int byt_sus_usb_ulpi_pins[] = {
443 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
444 };
445 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
446 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
447 };
448 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
449 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
450 };
451
452 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
453 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
454 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
455
456 static const struct intel_pingroup byt_sus_groups[] = {
457 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
458 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
459 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
460 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
461 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
462 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
463 };
464
465 static const char * const byt_sus_usb_groups[] = {
466 "usb_oc_grp", "usb_ulpi_grp",
467 };
468 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
469 static const char * const byt_sus_gpio_groups[] = {
470 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
471 };
472
473 static const struct intel_function byt_sus_functions[] = {
474 FUNCTION("usb", byt_sus_usb_groups),
475 FUNCTION("spi", byt_sus_spi_groups),
476 FUNCTION("gpio", byt_sus_gpio_groups),
477 };
478
479 static const struct intel_community byt_sus_communities[] = {
480 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
481 };
482
483 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
484 .uid = BYT_SUS_ACPI_UID,
485 .pins = byt_sus_pins,
486 .npins = ARRAY_SIZE(byt_sus_pins),
487 .groups = byt_sus_groups,
488 .ngroups = ARRAY_SIZE(byt_sus_groups),
489 .functions = byt_sus_functions,
490 .nfunctions = ARRAY_SIZE(byt_sus_functions),
491 .communities = byt_sus_communities,
492 .ncommunities = ARRAY_SIZE(byt_sus_communities),
493 };
494
495 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
496 PINCTRL_PIN(0, "GPIO_NCORE0"),
497 PINCTRL_PIN(1, "GPIO_NCORE1"),
498 PINCTRL_PIN(2, "GPIO_NCORE2"),
499 PINCTRL_PIN(3, "GPIO_NCORE3"),
500 PINCTRL_PIN(4, "GPIO_NCORE4"),
501 PINCTRL_PIN(5, "GPIO_NCORE5"),
502 PINCTRL_PIN(6, "GPIO_NCORE6"),
503 PINCTRL_PIN(7, "GPIO_NCORE7"),
504 PINCTRL_PIN(8, "GPIO_NCORE8"),
505 PINCTRL_PIN(9, "GPIO_NCORE9"),
506 PINCTRL_PIN(10, "GPIO_NCORE10"),
507 PINCTRL_PIN(11, "GPIO_NCORE11"),
508 PINCTRL_PIN(12, "GPIO_NCORE12"),
509 PINCTRL_PIN(13, "GPIO_NCORE13"),
510 PINCTRL_PIN(14, "GPIO_NCORE14"),
511 PINCTRL_PIN(15, "GPIO_NCORE15"),
512 PINCTRL_PIN(16, "GPIO_NCORE16"),
513 PINCTRL_PIN(17, "GPIO_NCORE17"),
514 PINCTRL_PIN(18, "GPIO_NCORE18"),
515 PINCTRL_PIN(19, "GPIO_NCORE19"),
516 PINCTRL_PIN(20, "GPIO_NCORE20"),
517 PINCTRL_PIN(21, "GPIO_NCORE21"),
518 PINCTRL_PIN(22, "GPIO_NCORE22"),
519 PINCTRL_PIN(23, "GPIO_NCORE23"),
520 PINCTRL_PIN(24, "GPIO_NCORE24"),
521 PINCTRL_PIN(25, "GPIO_NCORE25"),
522 PINCTRL_PIN(26, "GPIO_NCORE26"),
523 PINCTRL_PIN(27, "GPIO_NCORE27"),
524 };
525
526 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
527 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
528 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
529 3, 6, 10, 13, 2, 5, 9, 7,
530 };
531
532 static const struct intel_community byt_ncore_communities[] = {
533 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
534 };
535
536 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
537 .uid = BYT_NCORE_ACPI_UID,
538 .pins = byt_ncore_pins,
539 .npins = ARRAY_SIZE(byt_ncore_pins),
540 .communities = byt_ncore_communities,
541 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
542 };
543
544 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
545 &byt_score_soc_data,
546 &byt_sus_soc_data,
547 &byt_ncore_soc_data,
548 NULL
549 };
550
551 static DEFINE_RAW_SPINLOCK(byt_lock);
552
byt_get_community(struct byt_gpio * vg,unsigned int pin)553 static struct intel_community *byt_get_community(struct byt_gpio *vg,
554 unsigned int pin)
555 {
556 struct intel_community *comm;
557 int i;
558
559 for (i = 0; i < vg->soc_data->ncommunities; i++) {
560 comm = vg->communities_copy + i;
561 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
562 return comm;
563 }
564
565 return NULL;
566 }
567
byt_gpio_reg(struct byt_gpio * vg,unsigned int offset,int reg)568 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
569 int reg)
570 {
571 struct intel_community *comm = byt_get_community(vg, offset);
572 u32 reg_offset;
573
574 if (!comm)
575 return NULL;
576
577 offset -= comm->pin_base;
578 switch (reg) {
579 case BYT_INT_STAT_REG:
580 reg_offset = (offset / 32) * 4;
581 break;
582 case BYT_DEBOUNCE_REG:
583 reg_offset = 0;
584 break;
585 default:
586 reg_offset = comm->pad_map[offset] * 16;
587 break;
588 }
589
590 return comm->pad_regs + reg_offset + reg;
591 }
592
byt_get_groups_count(struct pinctrl_dev * pctldev)593 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
594 {
595 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
596
597 return vg->soc_data->ngroups;
598 }
599
byt_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)600 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
601 unsigned int selector)
602 {
603 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
604
605 return vg->soc_data->groups[selector].name;
606 }
607
byt_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)608 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
609 unsigned int selector,
610 const unsigned int **pins,
611 unsigned int *num_pins)
612 {
613 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
614
615 *pins = vg->soc_data->groups[selector].pins;
616 *num_pins = vg->soc_data->groups[selector].npins;
617
618 return 0;
619 }
620
621 static const struct pinctrl_ops byt_pinctrl_ops = {
622 .get_groups_count = byt_get_groups_count,
623 .get_group_name = byt_get_group_name,
624 .get_group_pins = byt_get_group_pins,
625 };
626
byt_get_functions_count(struct pinctrl_dev * pctldev)627 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
628 {
629 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
630
631 return vg->soc_data->nfunctions;
632 }
633
byt_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)634 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
635 unsigned int selector)
636 {
637 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
638
639 return vg->soc_data->functions[selector].name;
640 }
641
byt_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)642 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
643 unsigned int selector,
644 const char * const **groups,
645 unsigned int *num_groups)
646 {
647 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
648
649 *groups = vg->soc_data->functions[selector].groups;
650 *num_groups = vg->soc_data->functions[selector].ngroups;
651
652 return 0;
653 }
654
byt_set_group_simple_mux(struct byt_gpio * vg,const struct intel_pingroup group,unsigned int func)655 static void byt_set_group_simple_mux(struct byt_gpio *vg,
656 const struct intel_pingroup group,
657 unsigned int func)
658 {
659 unsigned long flags;
660 int i;
661
662 raw_spin_lock_irqsave(&byt_lock, flags);
663
664 for (i = 0; i < group.npins; i++) {
665 void __iomem *padcfg0;
666 u32 value;
667
668 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
669 if (!padcfg0) {
670 dev_warn(&vg->pdev->dev,
671 "Group %s, pin %i not muxed (no padcfg0)\n",
672 group.name, i);
673 continue;
674 }
675
676 value = readl(padcfg0);
677 value &= ~BYT_PIN_MUX;
678 value |= func;
679 writel(value, padcfg0);
680 }
681
682 raw_spin_unlock_irqrestore(&byt_lock, flags);
683 }
684
byt_set_group_mixed_mux(struct byt_gpio * vg,const struct intel_pingroup group,const unsigned int * func)685 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
686 const struct intel_pingroup group,
687 const unsigned int *func)
688 {
689 unsigned long flags;
690 int i;
691
692 raw_spin_lock_irqsave(&byt_lock, flags);
693
694 for (i = 0; i < group.npins; i++) {
695 void __iomem *padcfg0;
696 u32 value;
697
698 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
699 if (!padcfg0) {
700 dev_warn(&vg->pdev->dev,
701 "Group %s, pin %i not muxed (no padcfg0)\n",
702 group.name, i);
703 continue;
704 }
705
706 value = readl(padcfg0);
707 value &= ~BYT_PIN_MUX;
708 value |= func[i];
709 writel(value, padcfg0);
710 }
711
712 raw_spin_unlock_irqrestore(&byt_lock, flags);
713 }
714
byt_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)715 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
716 unsigned int group_selector)
717 {
718 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
719 const struct intel_function func = vg->soc_data->functions[func_selector];
720 const struct intel_pingroup group = vg->soc_data->groups[group_selector];
721
722 if (group.modes)
723 byt_set_group_mixed_mux(vg, group, group.modes);
724 else if (!strcmp(func.name, "gpio"))
725 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
726 else
727 byt_set_group_simple_mux(vg, group, group.mode);
728
729 return 0;
730 }
731
byt_get_gpio_mux(struct byt_gpio * vg,unsigned int offset)732 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
733 {
734 /* SCORE pin 92-93 */
735 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
736 offset >= 92 && offset <= 93)
737 return BYT_ALTER_GPIO_MUX;
738
739 /* SUS pin 11-21 */
740 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
741 offset >= 11 && offset <= 21)
742 return BYT_ALTER_GPIO_MUX;
743
744 return BYT_DEFAULT_GPIO_MUX;
745 }
746
byt_gpio_clear_triggering(struct byt_gpio * vg,unsigned int offset)747 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
748 {
749 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
750 unsigned long flags;
751 u32 value;
752
753 raw_spin_lock_irqsave(&byt_lock, flags);
754 value = readl(reg);
755 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
756 writel(value, reg);
757 raw_spin_unlock_irqrestore(&byt_lock, flags);
758 }
759
byt_gpio_request_enable(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)760 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
761 struct pinctrl_gpio_range *range,
762 unsigned int offset)
763 {
764 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
765 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
766 u32 value, gpio_mux;
767 unsigned long flags;
768
769 raw_spin_lock_irqsave(&byt_lock, flags);
770
771 /*
772 * In most cases, func pin mux 000 means GPIO function.
773 * But, some pins may have func pin mux 001 represents
774 * GPIO function.
775 *
776 * Because there are devices out there where some pins were not
777 * configured correctly we allow changing the mux value from
778 * request (but print out warning about that).
779 */
780 value = readl(reg) & BYT_PIN_MUX;
781 gpio_mux = byt_get_gpio_mux(vg, offset);
782 if (gpio_mux != value) {
783 value = readl(reg) & ~BYT_PIN_MUX;
784 value |= gpio_mux;
785 writel(value, reg);
786
787 dev_warn(&vg->pdev->dev, FW_BUG
788 "pin %u forcibly re-configured as GPIO\n", offset);
789 }
790
791 raw_spin_unlock_irqrestore(&byt_lock, flags);
792
793 pm_runtime_get(&vg->pdev->dev);
794
795 return 0;
796 }
797
byt_gpio_disable_free(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)798 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
799 struct pinctrl_gpio_range *range,
800 unsigned int offset)
801 {
802 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
803
804 byt_gpio_clear_triggering(vg, offset);
805 pm_runtime_put(&vg->pdev->dev);
806 }
807
byt_gpio_set_direction(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)808 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
809 struct pinctrl_gpio_range *range,
810 unsigned int offset,
811 bool input)
812 {
813 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
814 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
815 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
816 unsigned long flags;
817 u32 value;
818
819 raw_spin_lock_irqsave(&byt_lock, flags);
820
821 value = readl(val_reg);
822 value &= ~BYT_DIR_MASK;
823 if (input)
824 value |= BYT_OUTPUT_EN;
825 else
826 /*
827 * Before making any direction modifications, do a check if gpio
828 * is set for direct IRQ. On baytrail, setting GPIO to output
829 * does not make sense, so let's at least warn the caller before
830 * they shoot themselves in the foot.
831 */
832 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
833 "Potential Error: Setting GPIO with direct_irq_en to output");
834 writel(value, val_reg);
835
836 raw_spin_unlock_irqrestore(&byt_lock, flags);
837
838 return 0;
839 }
840
841 static const struct pinmux_ops byt_pinmux_ops = {
842 .get_functions_count = byt_get_functions_count,
843 .get_function_name = byt_get_function_name,
844 .get_function_groups = byt_get_function_groups,
845 .set_mux = byt_set_mux,
846 .gpio_request_enable = byt_gpio_request_enable,
847 .gpio_disable_free = byt_gpio_disable_free,
848 .gpio_set_direction = byt_gpio_set_direction,
849 };
850
byt_get_pull_strength(u32 reg,u16 * strength)851 static void byt_get_pull_strength(u32 reg, u16 *strength)
852 {
853 switch (reg & BYT_PULL_STR_MASK) {
854 case BYT_PULL_STR_2K:
855 *strength = 2000;
856 break;
857 case BYT_PULL_STR_10K:
858 *strength = 10000;
859 break;
860 case BYT_PULL_STR_20K:
861 *strength = 20000;
862 break;
863 case BYT_PULL_STR_40K:
864 *strength = 40000;
865 break;
866 }
867 }
868
byt_set_pull_strength(u32 * reg,u16 strength)869 static int byt_set_pull_strength(u32 *reg, u16 strength)
870 {
871 *reg &= ~BYT_PULL_STR_MASK;
872
873 switch (strength) {
874 case 2000:
875 *reg |= BYT_PULL_STR_2K;
876 break;
877 case 10000:
878 *reg |= BYT_PULL_STR_10K;
879 break;
880 case 20000:
881 *reg |= BYT_PULL_STR_20K;
882 break;
883 case 40000:
884 *reg |= BYT_PULL_STR_40K;
885 break;
886 default:
887 return -EINVAL;
888 }
889
890 return 0;
891 }
892
byt_pin_config_get(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * config)893 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
894 unsigned long *config)
895 {
896 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
897 enum pin_config_param param = pinconf_to_config_param(*config);
898 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
899 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
900 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
901 unsigned long flags;
902 u32 conf, pull, val, debounce;
903 u16 arg = 0;
904
905 raw_spin_lock_irqsave(&byt_lock, flags);
906 conf = readl(conf_reg);
907 pull = conf & BYT_PULL_ASSIGN_MASK;
908 val = readl(val_reg);
909 raw_spin_unlock_irqrestore(&byt_lock, flags);
910
911 switch (param) {
912 case PIN_CONFIG_BIAS_DISABLE:
913 if (pull)
914 return -EINVAL;
915 break;
916 case PIN_CONFIG_BIAS_PULL_DOWN:
917 /* Pull assignment is only applicable in input mode */
918 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
919 return -EINVAL;
920
921 byt_get_pull_strength(conf, &arg);
922
923 break;
924 case PIN_CONFIG_BIAS_PULL_UP:
925 /* Pull assignment is only applicable in input mode */
926 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
927 return -EINVAL;
928
929 byt_get_pull_strength(conf, &arg);
930
931 break;
932 case PIN_CONFIG_INPUT_DEBOUNCE:
933 if (!(conf & BYT_DEBOUNCE_EN))
934 return -EINVAL;
935
936 raw_spin_lock_irqsave(&byt_lock, flags);
937 debounce = readl(db_reg);
938 raw_spin_unlock_irqrestore(&byt_lock, flags);
939
940 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
941 case BYT_DEBOUNCE_PULSE_375US:
942 arg = 375;
943 break;
944 case BYT_DEBOUNCE_PULSE_750US:
945 arg = 750;
946 break;
947 case BYT_DEBOUNCE_PULSE_1500US:
948 arg = 1500;
949 break;
950 case BYT_DEBOUNCE_PULSE_3MS:
951 arg = 3000;
952 break;
953 case BYT_DEBOUNCE_PULSE_6MS:
954 arg = 6000;
955 break;
956 case BYT_DEBOUNCE_PULSE_12MS:
957 arg = 12000;
958 break;
959 case BYT_DEBOUNCE_PULSE_24MS:
960 arg = 24000;
961 break;
962 default:
963 return -EINVAL;
964 }
965
966 break;
967 default:
968 return -ENOTSUPP;
969 }
970
971 *config = pinconf_to_config_packed(param, arg);
972
973 return 0;
974 }
975
byt_pin_config_set(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * configs,unsigned int num_configs)976 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
977 unsigned int offset,
978 unsigned long *configs,
979 unsigned int num_configs)
980 {
981 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
982 unsigned int param, arg;
983 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
984 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
985 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
986 unsigned long flags;
987 u32 conf, val, debounce;
988 int i, ret = 0;
989
990 raw_spin_lock_irqsave(&byt_lock, flags);
991
992 conf = readl(conf_reg);
993 val = readl(val_reg);
994
995 for (i = 0; i < num_configs; i++) {
996 param = pinconf_to_config_param(configs[i]);
997 arg = pinconf_to_config_argument(configs[i]);
998
999 switch (param) {
1000 case PIN_CONFIG_BIAS_DISABLE:
1001 conf &= ~BYT_PULL_ASSIGN_MASK;
1002 break;
1003 case PIN_CONFIG_BIAS_PULL_DOWN:
1004 /* Set default strength value in case none is given */
1005 if (arg == 1)
1006 arg = 2000;
1007
1008 /*
1009 * Pull assignment is only applicable in input mode. If
1010 * chip is not in input mode, set it and warn about it.
1011 */
1012 if (val & BYT_INPUT_EN) {
1013 val &= ~BYT_INPUT_EN;
1014 writel(val, val_reg);
1015 dev_warn(&vg->pdev->dev,
1016 "pin %u forcibly set to input mode\n",
1017 offset);
1018 }
1019
1020 conf &= ~BYT_PULL_ASSIGN_MASK;
1021 conf |= BYT_PULL_ASSIGN_DOWN;
1022 ret = byt_set_pull_strength(&conf, arg);
1023
1024 break;
1025 case PIN_CONFIG_BIAS_PULL_UP:
1026 /* Set default strength value in case none is given */
1027 if (arg == 1)
1028 arg = 2000;
1029
1030 /*
1031 * Pull assignment is only applicable in input mode. If
1032 * chip is not in input mode, set it and warn about it.
1033 */
1034 if (val & BYT_INPUT_EN) {
1035 val &= ~BYT_INPUT_EN;
1036 writel(val, val_reg);
1037 dev_warn(&vg->pdev->dev,
1038 "pin %u forcibly set to input mode\n",
1039 offset);
1040 }
1041
1042 conf &= ~BYT_PULL_ASSIGN_MASK;
1043 conf |= BYT_PULL_ASSIGN_UP;
1044 ret = byt_set_pull_strength(&conf, arg);
1045
1046 break;
1047 case PIN_CONFIG_INPUT_DEBOUNCE:
1048 debounce = readl(db_reg);
1049 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1050
1051 if (arg)
1052 conf |= BYT_DEBOUNCE_EN;
1053 else
1054 conf &= ~BYT_DEBOUNCE_EN;
1055
1056 switch (arg) {
1057 case 375:
1058 debounce |= BYT_DEBOUNCE_PULSE_375US;
1059 break;
1060 case 750:
1061 debounce |= BYT_DEBOUNCE_PULSE_750US;
1062 break;
1063 case 1500:
1064 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1065 break;
1066 case 3000:
1067 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1068 break;
1069 case 6000:
1070 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1071 break;
1072 case 12000:
1073 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1074 break;
1075 case 24000:
1076 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1077 break;
1078 default:
1079 if (arg)
1080 ret = -EINVAL;
1081 break;
1082 }
1083
1084 if (!ret)
1085 writel(debounce, db_reg);
1086 break;
1087 default:
1088 ret = -ENOTSUPP;
1089 }
1090
1091 if (ret)
1092 break;
1093 }
1094
1095 if (!ret)
1096 writel(conf, conf_reg);
1097
1098 raw_spin_unlock_irqrestore(&byt_lock, flags);
1099
1100 return ret;
1101 }
1102
1103 static const struct pinconf_ops byt_pinconf_ops = {
1104 .is_generic = true,
1105 .pin_config_get = byt_pin_config_get,
1106 .pin_config_set = byt_pin_config_set,
1107 };
1108
1109 static const struct pinctrl_desc byt_pinctrl_desc = {
1110 .pctlops = &byt_pinctrl_ops,
1111 .pmxops = &byt_pinmux_ops,
1112 .confops = &byt_pinconf_ops,
1113 .owner = THIS_MODULE,
1114 };
1115
byt_gpio_get(struct gpio_chip * chip,unsigned int offset)1116 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1117 {
1118 struct byt_gpio *vg = gpiochip_get_data(chip);
1119 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1120 unsigned long flags;
1121 u32 val;
1122
1123 raw_spin_lock_irqsave(&byt_lock, flags);
1124 val = readl(reg);
1125 raw_spin_unlock_irqrestore(&byt_lock, flags);
1126
1127 return !!(val & BYT_LEVEL);
1128 }
1129
byt_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1130 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1131 {
1132 struct byt_gpio *vg = gpiochip_get_data(chip);
1133 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1134 unsigned long flags;
1135 u32 old_val;
1136
1137 if (!reg)
1138 return;
1139
1140 raw_spin_lock_irqsave(&byt_lock, flags);
1141 old_val = readl(reg);
1142 if (value)
1143 writel(old_val | BYT_LEVEL, reg);
1144 else
1145 writel(old_val & ~BYT_LEVEL, reg);
1146 raw_spin_unlock_irqrestore(&byt_lock, flags);
1147 }
1148
byt_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1149 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1150 {
1151 struct byt_gpio *vg = gpiochip_get_data(chip);
1152 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1153 unsigned long flags;
1154 u32 value;
1155
1156 if (!reg)
1157 return -EINVAL;
1158
1159 raw_spin_lock_irqsave(&byt_lock, flags);
1160 value = readl(reg);
1161 raw_spin_unlock_irqrestore(&byt_lock, flags);
1162
1163 if (!(value & BYT_OUTPUT_EN))
1164 return 0;
1165 if (!(value & BYT_INPUT_EN))
1166 return 1;
1167
1168 return -EINVAL;
1169 }
1170
byt_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1171 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1172 {
1173 return pinctrl_gpio_direction_input(chip->base + offset);
1174 }
1175
byt_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1176 static int byt_gpio_direction_output(struct gpio_chip *chip,
1177 unsigned int offset, int value)
1178 {
1179 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1180
1181 if (ret)
1182 return ret;
1183
1184 byt_gpio_set(chip, offset, value);
1185
1186 return 0;
1187 }
1188
byt_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1189 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1190 {
1191 struct byt_gpio *vg = gpiochip_get_data(chip);
1192 int i;
1193 u32 conf0, val;
1194
1195 for (i = 0; i < vg->soc_data->npins; i++) {
1196 const struct intel_community *comm;
1197 const char *pull_str = NULL;
1198 const char *pull = NULL;
1199 void __iomem *reg;
1200 unsigned long flags;
1201 const char *label;
1202 unsigned int pin;
1203
1204 raw_spin_lock_irqsave(&byt_lock, flags);
1205 pin = vg->soc_data->pins[i].number;
1206 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1207 if (!reg) {
1208 seq_printf(s,
1209 "Could not retrieve pin %i conf0 reg\n",
1210 pin);
1211 raw_spin_unlock_irqrestore(&byt_lock, flags);
1212 continue;
1213 }
1214 conf0 = readl(reg);
1215
1216 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1217 if (!reg) {
1218 seq_printf(s,
1219 "Could not retrieve pin %i val reg\n", pin);
1220 raw_spin_unlock_irqrestore(&byt_lock, flags);
1221 continue;
1222 }
1223 val = readl(reg);
1224 raw_spin_unlock_irqrestore(&byt_lock, flags);
1225
1226 comm = byt_get_community(vg, pin);
1227 if (!comm) {
1228 seq_printf(s,
1229 "Could not get community for pin %i\n", pin);
1230 continue;
1231 }
1232 label = gpiochip_is_requested(chip, i);
1233 if (!label)
1234 label = "Unrequested";
1235
1236 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1237 case BYT_PULL_ASSIGN_UP:
1238 pull = "up";
1239 break;
1240 case BYT_PULL_ASSIGN_DOWN:
1241 pull = "down";
1242 break;
1243 }
1244
1245 switch (conf0 & BYT_PULL_STR_MASK) {
1246 case BYT_PULL_STR_2K:
1247 pull_str = "2k";
1248 break;
1249 case BYT_PULL_STR_10K:
1250 pull_str = "10k";
1251 break;
1252 case BYT_PULL_STR_20K:
1253 pull_str = "20k";
1254 break;
1255 case BYT_PULL_STR_40K:
1256 pull_str = "40k";
1257 break;
1258 }
1259
1260 seq_printf(s,
1261 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1262 pin,
1263 label,
1264 val & BYT_INPUT_EN ? " " : "in",
1265 val & BYT_OUTPUT_EN ? " " : "out",
1266 val & BYT_LEVEL ? "hi" : "lo",
1267 comm->pad_map[i], comm->pad_map[i] * 16,
1268 conf0 & 0x7,
1269 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1270 conf0 & BYT_TRIG_POS ? " rise" : " ",
1271 conf0 & BYT_TRIG_LVL ? " level" : " ");
1272
1273 if (pull && pull_str)
1274 seq_printf(s, " %-4s %-3s", pull, pull_str);
1275 else
1276 seq_puts(s, " ");
1277
1278 if (conf0 & BYT_IODEN)
1279 seq_puts(s, " open-drain");
1280
1281 seq_puts(s, "\n");
1282 }
1283 }
1284
1285 static const struct gpio_chip byt_gpio_chip = {
1286 .owner = THIS_MODULE,
1287 .request = gpiochip_generic_request,
1288 .free = gpiochip_generic_free,
1289 .get_direction = byt_gpio_get_direction,
1290 .direction_input = byt_gpio_direction_input,
1291 .direction_output = byt_gpio_direction_output,
1292 .get = byt_gpio_get,
1293 .set = byt_gpio_set,
1294 .dbg_show = byt_gpio_dbg_show,
1295 };
1296
byt_irq_ack(struct irq_data * d)1297 static void byt_irq_ack(struct irq_data *d)
1298 {
1299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1300 struct byt_gpio *vg = gpiochip_get_data(gc);
1301 unsigned int offset = irqd_to_hwirq(d);
1302 void __iomem *reg;
1303
1304 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1305 if (!reg)
1306 return;
1307
1308 raw_spin_lock(&byt_lock);
1309 writel(BIT(offset % 32), reg);
1310 raw_spin_unlock(&byt_lock);
1311 }
1312
byt_irq_mask(struct irq_data * d)1313 static void byt_irq_mask(struct irq_data *d)
1314 {
1315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1316 struct byt_gpio *vg = gpiochip_get_data(gc);
1317
1318 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1319 }
1320
byt_irq_unmask(struct irq_data * d)1321 static void byt_irq_unmask(struct irq_data *d)
1322 {
1323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1324 struct byt_gpio *vg = gpiochip_get_data(gc);
1325 unsigned int offset = irqd_to_hwirq(d);
1326 unsigned long flags;
1327 void __iomem *reg;
1328 u32 value;
1329
1330 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1331 if (!reg)
1332 return;
1333
1334 raw_spin_lock_irqsave(&byt_lock, flags);
1335 value = readl(reg);
1336
1337 switch (irqd_get_trigger_type(d)) {
1338 case IRQ_TYPE_LEVEL_HIGH:
1339 value |= BYT_TRIG_LVL;
1340 /* fall through */
1341 case IRQ_TYPE_EDGE_RISING:
1342 value |= BYT_TRIG_POS;
1343 break;
1344 case IRQ_TYPE_LEVEL_LOW:
1345 value |= BYT_TRIG_LVL;
1346 /* fall through */
1347 case IRQ_TYPE_EDGE_FALLING:
1348 value |= BYT_TRIG_NEG;
1349 break;
1350 case IRQ_TYPE_EDGE_BOTH:
1351 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1352 break;
1353 }
1354
1355 writel(value, reg);
1356
1357 raw_spin_unlock_irqrestore(&byt_lock, flags);
1358 }
1359
byt_irq_type(struct irq_data * d,unsigned int type)1360 static int byt_irq_type(struct irq_data *d, unsigned int type)
1361 {
1362 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1363 u32 offset = irqd_to_hwirq(d);
1364 u32 value;
1365 unsigned long flags;
1366 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1367
1368 if (!reg || offset >= vg->chip.ngpio)
1369 return -EINVAL;
1370
1371 raw_spin_lock_irqsave(&byt_lock, flags);
1372 value = readl(reg);
1373
1374 WARN(value & BYT_DIRECT_IRQ_EN,
1375 "Bad pad config for io mode, force direct_irq_en bit clearing");
1376
1377 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1378 * are used to indicate high and low level triggering
1379 */
1380 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1381 BYT_TRIG_LVL);
1382 /* Enable glitch filtering */
1383 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1384 BYT_GLITCH_F_FAST_CLK;
1385
1386 writel(value, reg);
1387
1388 if (type & IRQ_TYPE_EDGE_BOTH)
1389 irq_set_handler_locked(d, handle_edge_irq);
1390 else if (type & IRQ_TYPE_LEVEL_MASK)
1391 irq_set_handler_locked(d, handle_level_irq);
1392
1393 raw_spin_unlock_irqrestore(&byt_lock, flags);
1394
1395 return 0;
1396 }
1397
1398 static struct irq_chip byt_irqchip = {
1399 .name = "BYT-GPIO",
1400 .irq_ack = byt_irq_ack,
1401 .irq_mask = byt_irq_mask,
1402 .irq_unmask = byt_irq_unmask,
1403 .irq_set_type = byt_irq_type,
1404 .flags = IRQCHIP_SKIP_SET_WAKE,
1405 };
1406
byt_gpio_irq_handler(struct irq_desc * desc)1407 static void byt_gpio_irq_handler(struct irq_desc *desc)
1408 {
1409 struct irq_data *data = irq_desc_get_irq_data(desc);
1410 struct byt_gpio *vg = gpiochip_get_data(
1411 irq_desc_get_handler_data(desc));
1412 struct irq_chip *chip = irq_data_get_irq_chip(data);
1413 u32 base, pin;
1414 void __iomem *reg;
1415 unsigned long pending;
1416 unsigned int virq;
1417
1418 /* check from GPIO controller which pin triggered the interrupt */
1419 for (base = 0; base < vg->chip.ngpio; base += 32) {
1420 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1421
1422 if (!reg) {
1423 dev_warn(&vg->pdev->dev,
1424 "Pin %i: could not retrieve interrupt status register\n",
1425 base);
1426 continue;
1427 }
1428
1429 raw_spin_lock(&byt_lock);
1430 pending = readl(reg);
1431 raw_spin_unlock(&byt_lock);
1432 for_each_set_bit(pin, &pending, 32) {
1433 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1434 generic_handle_irq(virq);
1435 }
1436 }
1437 chip->irq_eoi(data);
1438 }
1439
byt_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1440 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1441 unsigned long *valid_mask,
1442 unsigned int ngpios)
1443 {
1444 /*
1445 * FIXME: currently the valid_mask is filled in as part of
1446 * initializing the irq_chip below in byt_gpio_irq_init_hw().
1447 * when converting this driver to the new way of passing the
1448 * gpio_irq_chip along when adding the gpio_chip, move the
1449 * mask initialization into this callback instead. Right now
1450 * this callback is here to make sure the mask gets allocated.
1451 */
1452 }
1453
byt_gpio_irq_init_hw(struct byt_gpio * vg)1454 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1455 {
1456 struct gpio_chip *gc = &vg->chip;
1457 struct device *dev = &vg->pdev->dev;
1458 void __iomem *reg;
1459 u32 base, value;
1460 int i;
1461
1462 /*
1463 * Clear interrupt triggers for all pins that are GPIOs and
1464 * do not use direct IRQ mode. This will prevent spurious
1465 * interrupts from misconfigured pins.
1466 */
1467 for (i = 0; i < vg->soc_data->npins; i++) {
1468 unsigned int pin = vg->soc_data->pins[i].number;
1469
1470 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1471 if (!reg) {
1472 dev_warn(&vg->pdev->dev,
1473 "Pin %i: could not retrieve conf0 register\n",
1474 i);
1475 continue;
1476 }
1477
1478 value = readl(reg);
1479 if (value & BYT_DIRECT_IRQ_EN) {
1480 clear_bit(i, gc->irq.valid_mask);
1481 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1482 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1483 byt_gpio_clear_triggering(vg, i);
1484 dev_dbg(dev, "disabling GPIO %d\n", i);
1485 }
1486 }
1487
1488 /* clear interrupt status trigger registers */
1489 for (base = 0; base < vg->soc_data->npins; base += 32) {
1490 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1491
1492 if (!reg) {
1493 dev_warn(&vg->pdev->dev,
1494 "Pin %i: could not retrieve irq status reg\n",
1495 base);
1496 continue;
1497 }
1498
1499 writel(0xffffffff, reg);
1500 /* make sure trigger bits are cleared, if not then a pin
1501 might be misconfigured in bios */
1502 value = readl(reg);
1503 if (value)
1504 dev_err(&vg->pdev->dev,
1505 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1506 base / 32, value);
1507 }
1508 }
1509
byt_gpio_probe(struct byt_gpio * vg)1510 static int byt_gpio_probe(struct byt_gpio *vg)
1511 {
1512 struct gpio_chip *gc;
1513 struct resource *irq_rc;
1514 int ret;
1515
1516 /* Set up gpio chip */
1517 vg->chip = byt_gpio_chip;
1518 gc = &vg->chip;
1519 gc->label = dev_name(&vg->pdev->dev);
1520 gc->base = -1;
1521 gc->can_sleep = false;
1522 gc->parent = &vg->pdev->dev;
1523 gc->ngpio = vg->soc_data->npins;
1524 gc->irq.init_valid_mask = byt_init_irq_valid_mask;
1525
1526 #ifdef CONFIG_PM_SLEEP
1527 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1528 sizeof(*vg->saved_context), GFP_KERNEL);
1529 if (!vg->saved_context)
1530 return -ENOMEM;
1531 #endif
1532 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1533 if (ret) {
1534 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1535 return ret;
1536 }
1537
1538 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1539 0, 0, vg->soc_data->npins);
1540 if (ret) {
1541 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1542 return ret;
1543 }
1544
1545 /* set up interrupts */
1546 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1547 if (irq_rc && irq_rc->start) {
1548 byt_gpio_irq_init_hw(vg);
1549 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1550 handle_bad_irq, IRQ_TYPE_NONE);
1551 if (ret) {
1552 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1553 return ret;
1554 }
1555
1556 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1557 (unsigned)irq_rc->start,
1558 byt_gpio_irq_handler);
1559 }
1560
1561 return ret;
1562 }
1563
byt_set_soc_data(struct byt_gpio * vg,const struct intel_pinctrl_soc_data * soc_data)1564 static int byt_set_soc_data(struct byt_gpio *vg,
1565 const struct intel_pinctrl_soc_data *soc_data)
1566 {
1567 int i;
1568
1569 vg->soc_data = soc_data;
1570 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1571 soc_data->ncommunities,
1572 sizeof(*vg->communities_copy),
1573 GFP_KERNEL);
1574 if (!vg->communities_copy)
1575 return -ENOMEM;
1576
1577 for (i = 0; i < soc_data->ncommunities; i++) {
1578 struct intel_community *comm = vg->communities_copy + i;
1579
1580 *comm = vg->soc_data->communities[i];
1581
1582 comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
1583 if (IS_ERR(comm->pad_regs))
1584 return PTR_ERR(comm->pad_regs);
1585 }
1586
1587 return 0;
1588 }
1589
1590 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1591 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1592 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1593 { }
1594 };
1595
byt_pinctrl_probe(struct platform_device * pdev)1596 static int byt_pinctrl_probe(struct platform_device *pdev)
1597 {
1598 const struct intel_pinctrl_soc_data *soc_data = NULL;
1599 const struct intel_pinctrl_soc_data **soc_table;
1600 struct acpi_device *acpi_dev;
1601 struct byt_gpio *vg;
1602 int i, ret;
1603
1604 acpi_dev = ACPI_COMPANION(&pdev->dev);
1605 if (!acpi_dev)
1606 return -ENODEV;
1607
1608 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
1609
1610 for (i = 0; soc_table[i]; i++) {
1611 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1612 soc_data = soc_table[i];
1613 break;
1614 }
1615 }
1616
1617 if (!soc_data)
1618 return -ENODEV;
1619
1620 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1621 if (!vg)
1622 return -ENOMEM;
1623
1624 vg->pdev = pdev;
1625 ret = byt_set_soc_data(vg, soc_data);
1626 if (ret) {
1627 dev_err(&pdev->dev, "failed to set soc data\n");
1628 return ret;
1629 }
1630
1631 vg->pctl_desc = byt_pinctrl_desc;
1632 vg->pctl_desc.name = dev_name(&pdev->dev);
1633 vg->pctl_desc.pins = vg->soc_data->pins;
1634 vg->pctl_desc.npins = vg->soc_data->npins;
1635
1636 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1637 if (IS_ERR(vg->pctl_dev)) {
1638 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1639 return PTR_ERR(vg->pctl_dev);
1640 }
1641
1642 ret = byt_gpio_probe(vg);
1643 if (ret)
1644 return ret;
1645
1646 platform_set_drvdata(pdev, vg);
1647 pm_runtime_enable(&pdev->dev);
1648
1649 return 0;
1650 }
1651
1652 #ifdef CONFIG_PM_SLEEP
byt_gpio_suspend(struct device * dev)1653 static int byt_gpio_suspend(struct device *dev)
1654 {
1655 struct byt_gpio *vg = dev_get_drvdata(dev);
1656 unsigned long flags;
1657 int i;
1658
1659 raw_spin_lock_irqsave(&byt_lock, flags);
1660
1661 for (i = 0; i < vg->soc_data->npins; i++) {
1662 void __iomem *reg;
1663 u32 value;
1664 unsigned int pin = vg->soc_data->pins[i].number;
1665
1666 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1667 if (!reg) {
1668 dev_warn(&vg->pdev->dev,
1669 "Pin %i: could not retrieve conf0 register\n",
1670 i);
1671 continue;
1672 }
1673 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1674 vg->saved_context[i].conf0 = value;
1675
1676 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1677 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1678 vg->saved_context[i].val = value;
1679 }
1680
1681 raw_spin_unlock_irqrestore(&byt_lock, flags);
1682 return 0;
1683 }
1684
byt_gpio_resume(struct device * dev)1685 static int byt_gpio_resume(struct device *dev)
1686 {
1687 struct byt_gpio *vg = dev_get_drvdata(dev);
1688 unsigned long flags;
1689 int i;
1690
1691 raw_spin_lock_irqsave(&byt_lock, flags);
1692
1693 for (i = 0; i < vg->soc_data->npins; i++) {
1694 void __iomem *reg;
1695 u32 value;
1696 unsigned int pin = vg->soc_data->pins[i].number;
1697
1698 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1699 if (!reg) {
1700 dev_warn(&vg->pdev->dev,
1701 "Pin %i: could not retrieve conf0 register\n",
1702 i);
1703 continue;
1704 }
1705 value = readl(reg);
1706 if ((value & BYT_CONF0_RESTORE_MASK) !=
1707 vg->saved_context[i].conf0) {
1708 value &= ~BYT_CONF0_RESTORE_MASK;
1709 value |= vg->saved_context[i].conf0;
1710 writel(value, reg);
1711 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1712 }
1713
1714 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1715 value = readl(reg);
1716 if ((value & BYT_VAL_RESTORE_MASK) !=
1717 vg->saved_context[i].val) {
1718 u32 v;
1719
1720 v = value & ~BYT_VAL_RESTORE_MASK;
1721 v |= vg->saved_context[i].val;
1722 if (v != value) {
1723 writel(v, reg);
1724 dev_dbg(dev, "restored pin %d val %#08x\n",
1725 i, v);
1726 }
1727 }
1728 }
1729
1730 raw_spin_unlock_irqrestore(&byt_lock, flags);
1731 return 0;
1732 }
1733 #endif
1734
1735 #ifdef CONFIG_PM
byt_gpio_runtime_suspend(struct device * dev)1736 static int byt_gpio_runtime_suspend(struct device *dev)
1737 {
1738 return 0;
1739 }
1740
byt_gpio_runtime_resume(struct device * dev)1741 static int byt_gpio_runtime_resume(struct device *dev)
1742 {
1743 return 0;
1744 }
1745 #endif
1746
1747 static const struct dev_pm_ops byt_gpio_pm_ops = {
1748 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1749 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1750 NULL)
1751 };
1752
1753 static struct platform_driver byt_gpio_driver = {
1754 .probe = byt_pinctrl_probe,
1755 .driver = {
1756 .name = "byt_gpio",
1757 .pm = &byt_gpio_pm_ops,
1758 .suppress_bind_attrs = true,
1759
1760 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1761 },
1762 };
1763
byt_gpio_init(void)1764 static int __init byt_gpio_init(void)
1765 {
1766 return platform_driver_register(&byt_gpio_driver);
1767 }
1768 subsys_initcall(byt_gpio_init);
1769