1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel Low Power Subsystem PWM controller driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
8 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
9 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
10 * Author: Alan Cox <alan@linux.intel.com>
11 */
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/time.h>
20
21 #include "pwm-lpss.h"
22
23 #define PWM 0x00000000
24 #define PWM_ENABLE BIT(31)
25 #define PWM_SW_UPDATE BIT(30)
26 #define PWM_BASE_UNIT_SHIFT 8
27 #define PWM_ON_TIME_DIV_MASK 0x000000ff
28
29 /* Size of each PWM register space if multiple */
30 #define PWM_SIZE 0x400
31
to_lpwm(struct pwm_chip * chip)32 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
33 {
34 return container_of(chip, struct pwm_lpss_chip, chip);
35 }
36
pwm_lpss_read(const struct pwm_device * pwm)37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
38 {
39 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
40
41 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
42 }
43
pwm_lpss_write(const struct pwm_device * pwm,u32 value)44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
45 {
46 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
47
48 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
49 }
50
pwm_lpss_wait_for_update(struct pwm_device * pwm)51 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
52 {
53 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
54 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
55 const unsigned int ms = 500 * USEC_PER_MSEC;
56 u32 val;
57 int err;
58
59 /*
60 * PWM Configuration register has SW_UPDATE bit that is set when a new
61 * configuration is written to the register. The bit is automatically
62 * cleared at the start of the next output cycle by the IP block.
63 *
64 * If one writes a new configuration to the register while it still has
65 * the bit enabled, PWM may freeze. That is, while one can still write
66 * to the register, it won't have an effect. Thus, we try to sleep long
67 * enough that the bit gets cleared and make sure the bit is not
68 * enabled while we update the configuration.
69 */
70 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
71 if (err)
72 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
73
74 return err;
75 }
76
pwm_lpss_is_updating(struct pwm_device * pwm)77 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
78 {
79 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
80 }
81
pwm_lpss_prepare(struct pwm_lpss_chip * lpwm,struct pwm_device * pwm,int duty_ns,int period_ns)82 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
83 int duty_ns, int period_ns)
84 {
85 unsigned long long on_time_div;
86 unsigned long c = lpwm->info->clk_rate, base_unit_range;
87 unsigned long long base_unit, freq = NSEC_PER_SEC;
88 u32 orig_ctrl, ctrl;
89
90 do_div(freq, period_ns);
91
92 /*
93 * The equation is:
94 * base_unit = round(base_unit_range * freq / c)
95 */
96 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
97 freq *= base_unit_range;
98
99 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
100
101 on_time_div = 255ULL * duty_ns;
102 do_div(on_time_div, period_ns);
103 on_time_div = 255ULL - on_time_div;
104
105 orig_ctrl = ctrl = pwm_lpss_read(pwm);
106 ctrl &= ~PWM_ON_TIME_DIV_MASK;
107 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
108 base_unit &= base_unit_range;
109 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
110 ctrl |= on_time_div;
111
112 if (orig_ctrl != ctrl) {
113 pwm_lpss_write(pwm, ctrl);
114 pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
115 }
116 }
117
pwm_lpss_cond_enable(struct pwm_device * pwm,bool cond)118 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
119 {
120 if (cond)
121 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
122 }
123
pwm_lpss_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)124 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
125 const struct pwm_state *state)
126 {
127 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
128 int ret;
129
130 if (state->enabled) {
131 if (!pwm_is_enabled(pwm)) {
132 pm_runtime_get_sync(chip->dev);
133 ret = pwm_lpss_is_updating(pwm);
134 if (ret) {
135 pm_runtime_put(chip->dev);
136 return ret;
137 }
138 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
139 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
140 ret = pwm_lpss_wait_for_update(pwm);
141 if (ret) {
142 pm_runtime_put(chip->dev);
143 return ret;
144 }
145 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
146 } else {
147 ret = pwm_lpss_is_updating(pwm);
148 if (ret)
149 return ret;
150 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
151 return pwm_lpss_wait_for_update(pwm);
152 }
153 } else if (pwm_is_enabled(pwm)) {
154 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
155 pm_runtime_put(chip->dev);
156 }
157
158 return 0;
159 }
160
161 /* This function gets called once from pwmchip_add to get the initial state */
pwm_lpss_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)162 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
163 struct pwm_state *state)
164 {
165 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
166 unsigned long base_unit_range;
167 unsigned long long base_unit, freq, on_time_div;
168 u32 ctrl;
169
170 base_unit_range = BIT(lpwm->info->base_unit_bits);
171
172 ctrl = pwm_lpss_read(pwm);
173 on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
174 base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
175
176 freq = base_unit * lpwm->info->clk_rate;
177 do_div(freq, base_unit_range);
178 if (freq == 0)
179 state->period = NSEC_PER_SEC;
180 else
181 state->period = NSEC_PER_SEC / (unsigned long)freq;
182
183 on_time_div *= state->period;
184 do_div(on_time_div, 255);
185 state->duty_cycle = on_time_div;
186
187 state->polarity = PWM_POLARITY_NORMAL;
188 state->enabled = !!(ctrl & PWM_ENABLE);
189
190 if (state->enabled)
191 pm_runtime_get(chip->dev);
192 }
193
194 static const struct pwm_ops pwm_lpss_ops = {
195 .apply = pwm_lpss_apply,
196 .get_state = pwm_lpss_get_state,
197 .owner = THIS_MODULE,
198 };
199
pwm_lpss_probe(struct device * dev,struct resource * r,const struct pwm_lpss_boardinfo * info)200 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
201 const struct pwm_lpss_boardinfo *info)
202 {
203 struct pwm_lpss_chip *lpwm;
204 unsigned long c;
205 int ret;
206
207 if (WARN_ON(info->npwm > MAX_PWMS))
208 return ERR_PTR(-ENODEV);
209
210 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
211 if (!lpwm)
212 return ERR_PTR(-ENOMEM);
213
214 lpwm->regs = devm_ioremap_resource(dev, r);
215 if (IS_ERR(lpwm->regs))
216 return ERR_CAST(lpwm->regs);
217
218 lpwm->info = info;
219
220 c = lpwm->info->clk_rate;
221 if (!c)
222 return ERR_PTR(-EINVAL);
223
224 lpwm->chip.dev = dev;
225 lpwm->chip.ops = &pwm_lpss_ops;
226 lpwm->chip.base = -1;
227 lpwm->chip.npwm = info->npwm;
228
229 ret = pwmchip_add(&lpwm->chip);
230 if (ret) {
231 dev_err(dev, "failed to add PWM chip: %d\n", ret);
232 return ERR_PTR(ret);
233 }
234
235 return lpwm;
236 }
237 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
238
pwm_lpss_remove(struct pwm_lpss_chip * lpwm)239 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
240 {
241 int i;
242
243 for (i = 0; i < lpwm->info->npwm; i++) {
244 if (pwm_is_enabled(&lpwm->chip.pwms[i]))
245 pm_runtime_put(lpwm->chip.dev);
246 }
247 return pwmchip_remove(&lpwm->chip);
248 }
249 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
250
pwm_lpss_suspend(struct device * dev)251 int pwm_lpss_suspend(struct device *dev)
252 {
253 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
254 int i;
255
256 for (i = 0; i < lpwm->info->npwm; i++)
257 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
258
259 return 0;
260 }
261 EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
262
pwm_lpss_resume(struct device * dev)263 int pwm_lpss_resume(struct device *dev)
264 {
265 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
266 int i;
267
268 for (i = 0; i < lpwm->info->npwm; i++)
269 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
270
271 return 0;
272 }
273 EXPORT_SYMBOL_GPL(pwm_lpss_resume);
274
275 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
276 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
277 MODULE_LICENSE("GPL v2");
278