1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Regulator Driver for Freescale MC13783 PMIC
4 //
5 // Copyright 2010 Yong Shen <yong.shen@linaro.org>
6 // Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 // Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
8
9 #include <linux/mfd/mc13783.h>
10 #include <linux/regulator/machine.h>
11 #include <linux/regulator/driver.h>
12 #include <linux/platform_device.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include "mc13xxx.h"
19
20 #define MC13783_REG_SWITCHERS0 24
21 /* Enable does not exist for SW1A */
22 #define MC13783_REG_SWITCHERS0_SW1AEN 0
23 #define MC13783_REG_SWITCHERS0_SW1AVSEL 0
24 #define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0)
25
26 #define MC13783_REG_SWITCHERS1 25
27 /* Enable does not exist for SW1B */
28 #define MC13783_REG_SWITCHERS1_SW1BEN 0
29 #define MC13783_REG_SWITCHERS1_SW1BVSEL 0
30 #define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0)
31
32 #define MC13783_REG_SWITCHERS2 26
33 /* Enable does not exist for SW2A */
34 #define MC13783_REG_SWITCHERS2_SW2AEN 0
35 #define MC13783_REG_SWITCHERS2_SW2AVSEL 0
36 #define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0)
37
38 #define MC13783_REG_SWITCHERS3 27
39 /* Enable does not exist for SW2B */
40 #define MC13783_REG_SWITCHERS3_SW2BEN 0
41 #define MC13783_REG_SWITCHERS3_SW2BVSEL 0
42 #define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0)
43
44 #define MC13783_REG_SWITCHERS5 29
45 #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
46 #define MC13783_REG_SWITCHERS5_SW3VSEL 18
47 #define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
48
49 #define MC13783_REG_REGULATORSETTING0 30
50 #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
51 #define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
52 #define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
53 #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
54 #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
55 #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
56 #define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
57 #define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
58 #define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
59
60 #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
61 #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
62 #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
63 #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
64 #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
65 #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
66 #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
67 #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
68 #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
69
70 #define MC13783_REG_REGULATORSETTING1 31
71 #define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
72 #define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
73 #define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
74 #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
75 #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
76
77 #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
78 #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
79 #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
80 #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
81 #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
82
83 #define MC13783_REG_REGULATORMODE0 32
84 #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
85 #define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
86 #define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
87 #define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
88 #define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
89 #define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
90 #define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
91 #define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
92
93 #define MC13783_REG_REGULATORMODE1 33
94 #define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
95 #define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
96 #define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
97 #define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
98 #define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
99 #define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
100 #define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
101 #define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
102 #define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
103
104 #define MC13783_REG_POWERMISC 34
105 #define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
106 #define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
107 #define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
108 #define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
109 #define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
110 #define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
111
112 #define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
113
114
115 /* Voltage Values */
116 static const int mc13783_sw1x_val[] = {
117 900000, 925000, 950000, 975000,
118 1000000, 1025000, 1050000, 1075000,
119 1100000, 1125000, 1150000, 1175000,
120 1200000, 1225000, 1250000, 1275000,
121 1300000, 1325000, 1350000, 1375000,
122 1400000, 1425000, 1450000, 1475000,
123 1500000, 1525000, 1550000, 1575000,
124 1600000, 1625000, 1650000, 1675000,
125 1700000, 1700000, 1700000, 1700000,
126 1800000, 1800000, 1800000, 1800000,
127 1850000, 1850000, 1850000, 1850000,
128 2000000, 2000000, 2000000, 2000000,
129 2100000, 2100000, 2100000, 2100000,
130 2200000, 2200000, 2200000, 2200000,
131 2200000, 2200000, 2200000, 2200000,
132 2200000, 2200000, 2200000, 2200000,
133 };
134
135 static const int mc13783_sw2x_val[] = {
136 900000, 925000, 950000, 975000,
137 1000000, 1025000, 1050000, 1075000,
138 1100000, 1125000, 1150000, 1175000,
139 1200000, 1225000, 1250000, 1275000,
140 1300000, 1325000, 1350000, 1375000,
141 1400000, 1425000, 1450000, 1475000,
142 1500000, 1525000, 1550000, 1575000,
143 1600000, 1625000, 1650000, 1675000,
144 1700000, 1700000, 1700000, 1700000,
145 1800000, 1800000, 1800000, 1800000,
146 1900000, 1900000, 1900000, 1900000,
147 2000000, 2000000, 2000000, 2000000,
148 2100000, 2100000, 2100000, 2100000,
149 2200000, 2200000, 2200000, 2200000,
150 2200000, 2200000, 2200000, 2200000,
151 2200000, 2200000, 2200000, 2200000,
152 };
153
154 static const unsigned int mc13783_sw3_val[] = {
155 5000000, 5000000, 5000000, 5500000,
156 };
157
158 static const unsigned int mc13783_vaudio_val[] = {
159 2775000,
160 };
161
162 static const unsigned int mc13783_viohi_val[] = {
163 2775000,
164 };
165
166 static const unsigned int mc13783_violo_val[] = {
167 1200000, 1300000, 1500000, 1800000,
168 };
169
170 static const unsigned int mc13783_vdig_val[] = {
171 1200000, 1300000, 1500000, 1800000,
172 };
173
174 static const unsigned int mc13783_vgen_val[] = {
175 1200000, 1300000, 1500000, 1800000,
176 1100000, 2000000, 2775000, 2400000,
177 };
178
179 static const unsigned int mc13783_vrfdig_val[] = {
180 1200000, 1500000, 1800000, 1875000,
181 };
182
183 static const unsigned int mc13783_vrfref_val[] = {
184 2475000, 2600000, 2700000, 2775000,
185 };
186
187 static const unsigned int mc13783_vrfcp_val[] = {
188 2700000, 2775000,
189 };
190
191 static const unsigned int mc13783_vsim_val[] = {
192 1800000, 2900000, 3000000,
193 };
194
195 static const unsigned int mc13783_vesim_val[] = {
196 1800000, 2900000,
197 };
198
199 static const unsigned int mc13783_vcam_val[] = {
200 1500000, 1800000, 2500000, 2550000,
201 2600000, 2750000, 2800000, 3000000,
202 };
203
204 static const unsigned int mc13783_vrfbg_val[] = {
205 1250000,
206 };
207
208 static const unsigned int mc13783_vvib_val[] = {
209 1300000, 1800000, 2000000, 3000000,
210 };
211
212 static const unsigned int mc13783_vmmc_val[] = {
213 1600000, 1800000, 2000000, 2600000,
214 2700000, 2800000, 2900000, 3000000,
215 };
216
217 static const unsigned int mc13783_vrf_val[] = {
218 1500000, 1875000, 2700000, 2775000,
219 };
220
221 static const unsigned int mc13783_gpo_val[] = {
222 3100000,
223 };
224
225 static const unsigned int mc13783_pwgtdrv_val[] = {
226 5500000,
227 };
228
229 static const struct regulator_ops mc13783_gpo_regulator_ops;
230
231 #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \
232 MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \
233 mc13xxx_regulator_ops)
234
235 #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \
236 MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \
237 mc13xxx_fixed_regulator_ops)
238
239 #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \
240 MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \
241 mc13783_gpo_regulator_ops)
242
243 #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
244 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
245 #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \
246 MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
247
248 static struct mc13xxx_regulator mc13783_regulators[] = {
249 MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
250 MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
251 MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
252 MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
253 MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
254
255 MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
256 MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
257 MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0,
258 mc13783_violo_val),
259 MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
260 mc13783_vdig_val),
261 MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0,
262 mc13783_vgen_val),
263 MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0,
264 mc13783_vrfdig_val),
265 MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0,
266 mc13783_vrfref_val),
267 MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0,
268 mc13783_vrfcp_val),
269 MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0,
270 mc13783_vsim_val),
271 MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0,
272 mc13783_vesim_val),
273 MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
274 mc13783_vcam_val),
275 MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
276 MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1,
277 mc13783_vvib_val),
278 MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1,
279 mc13783_vrf_val),
280 MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1,
281 mc13783_vrf_val),
282 MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1,
283 mc13783_vmmc_val),
284 MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1,
285 mc13783_vmmc_val),
286 MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
287 MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
288 MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
289 MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
290 MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
291 MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
292 };
293
mc13783_powermisc_rmw(struct mc13xxx_regulator_priv * priv,u32 mask,u32 val)294 static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
295 u32 val)
296 {
297 struct mc13xxx *mc13783 = priv->mc13xxx;
298 int ret;
299 u32 valread;
300
301 BUG_ON(val & ~mask);
302
303 mc13xxx_lock(priv->mc13xxx);
304 ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
305 if (ret)
306 goto out;
307
308 /* Update the stored state for Power Gates. */
309 priv->powermisc_pwgt_state =
310 (priv->powermisc_pwgt_state & ~mask) | val;
311 priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
312
313 /* Construct the new register value */
314 valread = (valread & ~mask) | val;
315 /* Overwrite the PWGTxEN with the stored version */
316 valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
317 priv->powermisc_pwgt_state;
318
319 ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
320 out:
321 mc13xxx_unlock(priv->mc13xxx);
322 return ret;
323 }
324
mc13783_gpo_regulator_enable(struct regulator_dev * rdev)325 static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
326 {
327 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
328 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
329 int id = rdev_get_id(rdev);
330 u32 en_val = mc13xxx_regulators[id].enable_bit;
331
332 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
333
334 /* Power Gate enable value is 0 */
335 if (id == MC13783_REG_PWGT1SPI ||
336 id == MC13783_REG_PWGT2SPI)
337 en_val = 0;
338
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
340 en_val);
341 }
342
mc13783_gpo_regulator_disable(struct regulator_dev * rdev)343 static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
344 {
345 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
346 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
347 int id = rdev_get_id(rdev);
348 u32 dis_val = 0;
349
350 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
351
352 /* Power Gate disable value is 1 */
353 if (id == MC13783_REG_PWGT1SPI ||
354 id == MC13783_REG_PWGT2SPI)
355 dis_val = mc13xxx_regulators[id].enable_bit;
356
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
358 dis_val);
359 }
360
mc13783_gpo_regulator_is_enabled(struct regulator_dev * rdev)361 static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
362 {
363 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
364 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
365 int ret, id = rdev_get_id(rdev);
366 unsigned int val;
367
368 mc13xxx_lock(priv->mc13xxx);
369 ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
370 mc13xxx_unlock(priv->mc13xxx);
371
372 if (ret)
373 return ret;
374
375 /* Power Gates state is stored in powermisc_pwgt_state
376 * where the meaning of bits is negated */
377 val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
378 (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
379
380 return (val & mc13xxx_regulators[id].enable_bit) != 0;
381 }
382
383 static const struct regulator_ops mc13783_gpo_regulator_ops = {
384 .enable = mc13783_gpo_regulator_enable,
385 .disable = mc13783_gpo_regulator_disable,
386 .is_enabled = mc13783_gpo_regulator_is_enabled,
387 .list_voltage = regulator_list_voltage_table,
388 .set_voltage = mc13xxx_fixed_regulator_set_voltage,
389 };
390
mc13783_regulator_probe(struct platform_device * pdev)391 static int mc13783_regulator_probe(struct platform_device *pdev)
392 {
393 struct mc13xxx_regulator_priv *priv;
394 struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
395 struct mc13xxx_regulator_platform_data *pdata =
396 dev_get_platdata(&pdev->dev);
397 struct mc13xxx_regulator_init_data *mc13xxx_data;
398 struct regulator_config config = { };
399 int i, num_regulators;
400
401 num_regulators = mc13xxx_get_num_regulators_dt(pdev);
402
403 if (num_regulators <= 0 && pdata)
404 num_regulators = pdata->num_regulators;
405 if (num_regulators <= 0)
406 return -EINVAL;
407
408 priv = devm_kzalloc(&pdev->dev,
409 struct_size(priv, regulators, num_regulators),
410 GFP_KERNEL);
411 if (!priv)
412 return -ENOMEM;
413
414 priv->num_regulators = num_regulators;
415 priv->mc13xxx_regulators = mc13783_regulators;
416 priv->mc13xxx = mc13783;
417 platform_set_drvdata(pdev, priv);
418
419 mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
420 ARRAY_SIZE(mc13783_regulators));
421
422 for (i = 0; i < priv->num_regulators; i++) {
423 struct regulator_init_data *init_data;
424 struct regulator_desc *desc;
425 struct device_node *node = NULL;
426 int id;
427
428 if (mc13xxx_data) {
429 id = mc13xxx_data[i].id;
430 init_data = mc13xxx_data[i].init_data;
431 node = mc13xxx_data[i].node;
432 } else {
433 id = pdata->regulators[i].id;
434 init_data = pdata->regulators[i].init_data;
435 }
436 desc = &mc13783_regulators[id].desc;
437
438 config.dev = &pdev->dev;
439 config.init_data = init_data;
440 config.driver_data = priv;
441 config.of_node = node;
442
443 priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
444 &config);
445 if (IS_ERR(priv->regulators[i])) {
446 dev_err(&pdev->dev, "failed to register regulator %s\n",
447 mc13783_regulators[i].desc.name);
448 return PTR_ERR(priv->regulators[i]);
449 }
450 }
451
452 return 0;
453 }
454
455 static struct platform_driver mc13783_regulator_driver = {
456 .driver = {
457 .name = "mc13783-regulator",
458 },
459 .probe = mc13783_regulator_probe,
460 };
461
mc13783_regulator_init(void)462 static int __init mc13783_regulator_init(void)
463 {
464 return platform_driver_register(&mc13783_regulator_driver);
465 }
466 subsys_initcall(mc13783_regulator_init);
467
mc13783_regulator_exit(void)468 static void __exit mc13783_regulator_exit(void)
469 {
470 platform_driver_unregister(&mc13783_regulator_driver);
471 }
472 module_exit(mc13783_regulator_exit);
473
474 MODULE_LICENSE("GPL v2");
475 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
476 MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
477 MODULE_ALIAS("platform:mc13783-regulator");
478