1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Memory-mapped interface driver for DW SPI Core
4 *
5 * Copyright (c) 2010, Octasic semiconductor.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/spi/spi.h>
14 #include <linux/scatterlist.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_platform.h>
19 #include <linux/acpi.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22
23 #include "spi-dw.h"
24
25 #define DRIVER_NAME "dw_spi_mmio"
26
27 struct dw_spi_mmio {
28 struct dw_spi dws;
29 struct clk *clk;
30 struct clk *pclk;
31 void *priv;
32 };
33
34 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
35 #define OCELOT_IF_SI_OWNER_OFFSET 4
36 #define JAGUAR2_IF_SI_OWNER_OFFSET 6
37 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
38 #define MSCC_IF_SI_OWNER_SISL 0
39 #define MSCC_IF_SI_OWNER_SIBM 1
40 #define MSCC_IF_SI_OWNER_SIMC 2
41
42 #define MSCC_SPI_MST_SW_MODE 0x14
43 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
44 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
45
46 struct dw_spi_mscc {
47 struct regmap *syscon;
48 void __iomem *spi_mst;
49 };
50
51 /*
52 * The Designware SPI controller (referred to as master in the documentation)
53 * automatically deasserts chip select when the tx fifo is empty. The chip
54 * selects then needs to be either driven as GPIOs or, for the first 4 using the
55 * the SPI boot controller registers. the final chip select is an OR gate
56 * between the Designware SPI controller and the SPI boot controller.
57 */
dw_spi_mscc_set_cs(struct spi_device * spi,bool enable)58 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
59 {
60 struct dw_spi *dws = spi_master_get_devdata(spi->master);
61 struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
62 struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
63 u32 cs = spi->chip_select;
64
65 if (cs < 4) {
66 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
67
68 if (!enable)
69 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
70
71 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
72 }
73
74 dw_spi_set_cs(spi, enable);
75 }
76
dw_spi_mscc_init(struct platform_device * pdev,struct dw_spi_mmio * dwsmmio,const char * cpu_syscon,u32 if_si_owner_offset)77 static int dw_spi_mscc_init(struct platform_device *pdev,
78 struct dw_spi_mmio *dwsmmio,
79 const char *cpu_syscon, u32 if_si_owner_offset)
80 {
81 struct dw_spi_mscc *dwsmscc;
82
83 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
84 if (!dwsmscc)
85 return -ENOMEM;
86
87 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
88 if (IS_ERR(dwsmscc->spi_mst)) {
89 dev_err(&pdev->dev, "SPI_MST region map failed\n");
90 return PTR_ERR(dwsmscc->spi_mst);
91 }
92
93 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
94 if (IS_ERR(dwsmscc->syscon))
95 return PTR_ERR(dwsmscc->syscon);
96
97 /* Deassert all CS */
98 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
99
100 /* Select the owner of the SI interface */
101 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
102 MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
103 MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
104
105 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
106 dwsmmio->priv = dwsmscc;
107
108 return 0;
109 }
110
dw_spi_mscc_ocelot_init(struct platform_device * pdev,struct dw_spi_mmio * dwsmmio)111 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
112 struct dw_spi_mmio *dwsmmio)
113 {
114 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
115 OCELOT_IF_SI_OWNER_OFFSET);
116 }
117
dw_spi_mscc_jaguar2_init(struct platform_device * pdev,struct dw_spi_mmio * dwsmmio)118 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
119 struct dw_spi_mmio *dwsmmio)
120 {
121 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
122 JAGUAR2_IF_SI_OWNER_OFFSET);
123 }
124
dw_spi_alpine_init(struct platform_device * pdev,struct dw_spi_mmio * dwsmmio)125 static int dw_spi_alpine_init(struct platform_device *pdev,
126 struct dw_spi_mmio *dwsmmio)
127 {
128 dwsmmio->dws.cs_override = 1;
129
130 return 0;
131 }
132
dw_spi_mmio_probe(struct platform_device * pdev)133 static int dw_spi_mmio_probe(struct platform_device *pdev)
134 {
135 int (*init_func)(struct platform_device *pdev,
136 struct dw_spi_mmio *dwsmmio);
137 struct dw_spi_mmio *dwsmmio;
138 struct dw_spi *dws;
139 int ret;
140 int num_cs;
141
142 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
143 GFP_KERNEL);
144 if (!dwsmmio)
145 return -ENOMEM;
146
147 dws = &dwsmmio->dws;
148
149 /* Get basic io resource and map it */
150 dws->regs = devm_platform_ioremap_resource(pdev, 0);
151 if (IS_ERR(dws->regs)) {
152 dev_err(&pdev->dev, "SPI region map failed\n");
153 return PTR_ERR(dws->regs);
154 }
155
156 dws->irq = platform_get_irq(pdev, 0);
157 if (dws->irq < 0)
158 return dws->irq; /* -ENXIO */
159
160 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
161 if (IS_ERR(dwsmmio->clk))
162 return PTR_ERR(dwsmmio->clk);
163 ret = clk_prepare_enable(dwsmmio->clk);
164 if (ret)
165 return ret;
166
167 /* Optional clock needed to access the registers */
168 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
169 if (IS_ERR(dwsmmio->pclk)) {
170 ret = PTR_ERR(dwsmmio->pclk);
171 goto out_clk;
172 }
173 ret = clk_prepare_enable(dwsmmio->pclk);
174 if (ret)
175 goto out_clk;
176
177 dws->bus_num = pdev->id;
178
179 dws->max_freq = clk_get_rate(dwsmmio->clk);
180
181 device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
182
183 num_cs = 4;
184
185 device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
186
187 dws->num_cs = num_cs;
188
189 init_func = device_get_match_data(&pdev->dev);
190 if (init_func) {
191 ret = init_func(pdev, dwsmmio);
192 if (ret)
193 goto out;
194 }
195
196 ret = dw_spi_add_host(&pdev->dev, dws);
197 if (ret)
198 goto out;
199
200 platform_set_drvdata(pdev, dwsmmio);
201 return 0;
202
203 out:
204 clk_disable_unprepare(dwsmmio->pclk);
205 out_clk:
206 clk_disable_unprepare(dwsmmio->clk);
207 return ret;
208 }
209
dw_spi_mmio_remove(struct platform_device * pdev)210 static int dw_spi_mmio_remove(struct platform_device *pdev)
211 {
212 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
213
214 dw_spi_remove_host(&dwsmmio->dws);
215 clk_disable_unprepare(dwsmmio->pclk);
216 clk_disable_unprepare(dwsmmio->clk);
217
218 return 0;
219 }
220
221 static const struct of_device_id dw_spi_mmio_of_match[] = {
222 { .compatible = "snps,dw-apb-ssi", },
223 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
224 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
225 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
226 { /* end of table */}
227 };
228 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
229
230 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
231 {"HISI0173", 0},
232 {},
233 };
234 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
235
236 static struct platform_driver dw_spi_mmio_driver = {
237 .probe = dw_spi_mmio_probe,
238 .remove = dw_spi_mmio_remove,
239 .driver = {
240 .name = DRIVER_NAME,
241 .of_match_table = dw_spi_mmio_of_match,
242 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
243 },
244 };
245 module_platform_driver(dw_spi_mmio_driver);
246
247 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
248 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
249 MODULE_LICENSE("GPL v2");
250