1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
27
28 /* Registers */
29 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
30 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
31 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
32 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
33 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
34 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
35 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
36 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
37 /* (AD7792)/24-bit (AD7192)) */
38 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
39 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
40
41 /* Communications Register Bit Designations (AD7192_REG_COMM) */
42 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
43 #define AD7192_COMM_WRITE 0 /* Write Operation */
44 #define AD7192_COMM_READ BIT(6) /* Read Operation */
45 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
46 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
47
48 /* Status Register Bit Designations (AD7192_REG_STAT) */
49 #define AD7192_STAT_RDY BIT(7) /* Ready */
50 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
51 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
52 #define AD7192_STAT_PARITY BIT(4) /* Parity */
53 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
54 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
55 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
56
57 /* Mode Register Bit Designations (AD7192_REG_MODE) */
58 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
59 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
60 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
61 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
62 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
63 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
64 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
65 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
66 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
67 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
68 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
69
70 /* Mode Register: AD7192_MODE_SEL options */
71 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
72 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
73 #define AD7192_MODE_IDLE 2 /* Idle Mode */
74 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
75 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
76 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
79
80 /* Mode Register: AD7192_MODE_CLKSRC options */
81 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
82 /* from MCLK1 to MCLK2 */
83 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
84 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
85 /* available at the MCLK2 pin */
86 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
87 /* at the MCLK2 pin */
88
89 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
90
91 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
92 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
93 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
94 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
95 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
96 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
97 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
98 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
99 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
100
101 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
102 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
103 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
104 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
105 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
106 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
107 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
108 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
109
110 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
111 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
112 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
113 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
114 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
115 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
116 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
117 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
118 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
119 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
120 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
121 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
122 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
123 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
124 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
125
126 /* ID Register Bit Designations (AD7192_REG_ID) */
127 #define ID_AD7190 0x4
128 #define ID_AD7192 0x0
129 #define ID_AD7193 0x2
130 #define ID_AD7195 0x6
131 #define AD7192_ID_MASK 0x0F
132
133 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
134 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
135 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
136 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
137 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
138 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
139 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
140 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
141
142 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
143 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
144 #define AD7192_INT_FREQ_MHZ 4915200
145
146 #define AD7192_NO_SYNC_FILTER 1
147 #define AD7192_SYNC3_FILTER 3
148 #define AD7192_SYNC4_FILTER 4
149
150 /* NOTE:
151 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
152 * In order to avoid contentions on the SPI bus, it's therefore necessary
153 * to use spi bus locking.
154 *
155 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
156 */
157
158 struct ad7192_state {
159 struct regulator *avdd;
160 struct regulator *dvdd;
161 struct clk *mclk;
162 u16 int_vref_mv;
163 u32 fclk;
164 u32 f_order;
165 u32 mode;
166 u32 conf;
167 u32 scale_avail[8][2];
168 u8 gpocon;
169 u8 devid;
170 u8 clock_sel;
171 struct mutex lock; /* protect sensor state */
172
173 struct ad_sigma_delta sd;
174 };
175
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)176 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
177 {
178 return container_of(sd, struct ad7192_state, sd);
179 }
180
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)181 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
182 {
183 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
184
185 st->conf &= ~AD7192_CONF_CHAN_MASK;
186 st->conf |= AD7192_CONF_CHAN(channel);
187
188 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
189 }
190
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)191 static int ad7192_set_mode(struct ad_sigma_delta *sd,
192 enum ad_sigma_delta_mode mode)
193 {
194 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
195
196 st->mode &= ~AD7192_MODE_SEL_MASK;
197 st->mode |= AD7192_MODE_SEL(mode);
198
199 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
200 }
201
202 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
203 .set_channel = ad7192_set_channel,
204 .set_mode = ad7192_set_mode,
205 .has_registers = true,
206 .addr_shift = 3,
207 .read_mask = BIT(6),
208 };
209
210 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
211 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
212 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
213 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
214 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
215 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
216 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
217 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
218 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
219 };
220
ad7192_calibrate_all(struct ad7192_state * st)221 static int ad7192_calibrate_all(struct ad7192_state *st)
222 {
223 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
224 ARRAY_SIZE(ad7192_calib_arr));
225 }
226
ad7192_valid_external_frequency(u32 freq)227 static inline bool ad7192_valid_external_frequency(u32 freq)
228 {
229 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
230 freq <= AD7192_EXT_FREQ_MHZ_MAX);
231 }
232
ad7192_of_clock_select(struct ad7192_state * st)233 static int ad7192_of_clock_select(struct ad7192_state *st)
234 {
235 struct device_node *np = st->sd.spi->dev.of_node;
236 unsigned int clock_sel;
237
238 clock_sel = AD7192_CLK_INT;
239
240 /* use internal clock */
241 if (PTR_ERR(st->mclk) == -ENOENT) {
242 if (of_property_read_bool(np, "adi,int-clock-output-enable"))
243 clock_sel = AD7192_CLK_INT_CO;
244 } else {
245 if (of_property_read_bool(np, "adi,clock-xtal"))
246 clock_sel = AD7192_CLK_EXT_MCLK1_2;
247 else
248 clock_sel = AD7192_CLK_EXT_MCLK2;
249 }
250
251 return clock_sel;
252 }
253
ad7192_setup(struct ad7192_state * st,struct device_node * np)254 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
255 {
256 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
257 bool rej60_en, refin2_en;
258 bool buf_en, bipolar, burnout_curr_en;
259 unsigned long long scale_uv;
260 int i, ret, id;
261
262 /* reset the serial interface */
263 ret = ad_sd_reset(&st->sd, 48);
264 if (ret < 0)
265 return ret;
266 usleep_range(500, 1000); /* Wait for at least 500us */
267
268 /* write/read test for device presence */
269 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
270 if (ret)
271 return ret;
272
273 id &= AD7192_ID_MASK;
274
275 if (id != st->devid)
276 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
277 id);
278
279 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
280 AD7192_MODE_CLKSRC(st->clock_sel) |
281 AD7192_MODE_RATE(480);
282
283 st->conf = AD7192_CONF_GAIN(0);
284
285 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
286 if (rej60_en)
287 st->mode |= AD7192_MODE_REJ60;
288
289 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
290 if (refin2_en && st->devid != ID_AD7195)
291 st->conf |= AD7192_CONF_REFSEL;
292
293 st->conf &= ~AD7192_CONF_CHOP;
294 st->f_order = AD7192_NO_SYNC_FILTER;
295
296 buf_en = of_property_read_bool(np, "adi,buffer-enable");
297 if (buf_en)
298 st->conf |= AD7192_CONF_BUF;
299
300 bipolar = of_property_read_bool(np, "bipolar");
301 if (!bipolar)
302 st->conf |= AD7192_CONF_UNIPOLAR;
303
304 burnout_curr_en = of_property_read_bool(np,
305 "adi,burnout-currents-enable");
306 if (burnout_curr_en && buf_en) {
307 st->conf |= AD7192_CONF_BURN;
308 } else if (burnout_curr_en) {
309 dev_warn(&st->sd.spi->dev,
310 "Can't enable burnout currents: see CHOP or buffer\n");
311 }
312
313 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
314 if (ret)
315 return ret;
316
317 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
318 if (ret)
319 return ret;
320
321 ret = ad7192_calibrate_all(st);
322 if (ret)
323 return ret;
324
325 /* Populate available ADC input ranges */
326 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
327 scale_uv = ((u64)st->int_vref_mv * 100000000)
328 >> (indio_dev->channels[0].scan_type.realbits -
329 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
330 scale_uv >>= i;
331
332 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
333 st->scale_avail[i][0] = scale_uv;
334 }
335
336 return 0;
337 }
338
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)339 static ssize_t ad7192_show_ac_excitation(struct device *dev,
340 struct device_attribute *attr,
341 char *buf)
342 {
343 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
344 struct ad7192_state *st = iio_priv(indio_dev);
345
346 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
347 }
348
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)349 static ssize_t ad7192_show_bridge_switch(struct device *dev,
350 struct device_attribute *attr,
351 char *buf)
352 {
353 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
354 struct ad7192_state *st = iio_priv(indio_dev);
355
356 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
357 }
358
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)359 static ssize_t ad7192_set(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf,
362 size_t len)
363 {
364 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
365 struct ad7192_state *st = iio_priv(indio_dev);
366 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
367 int ret;
368 bool val;
369
370 ret = strtobool(buf, &val);
371 if (ret < 0)
372 return ret;
373
374 ret = iio_device_claim_direct_mode(indio_dev);
375 if (ret)
376 return ret;
377
378 switch ((u32)this_attr->address) {
379 case AD7192_REG_GPOCON:
380 if (val)
381 st->gpocon |= AD7192_GPOCON_BPDSW;
382 else
383 st->gpocon &= ~AD7192_GPOCON_BPDSW;
384
385 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
386 break;
387 case AD7192_REG_MODE:
388 if (val)
389 st->mode |= AD7192_MODE_ACX;
390 else
391 st->mode &= ~AD7192_MODE_ACX;
392
393 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
394 break;
395 default:
396 ret = -EINVAL;
397 }
398
399 iio_device_release_direct_mode(indio_dev);
400
401 return ret ? ret : len;
402 }
403
ad7192_get_available_filter_freq(struct ad7192_state * st,int * freq)404 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
405 int *freq)
406 {
407 unsigned int fadc;
408
409 /* Formulas for filter at page 25 of the datasheet */
410 fadc = DIV_ROUND_CLOSEST(st->fclk,
411 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
412 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
413
414 fadc = DIV_ROUND_CLOSEST(st->fclk,
415 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
416 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
417
418 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
419 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
420 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
421 }
422
ad7192_show_filter_avail(struct device * dev,struct device_attribute * attr,char * buf)423 static ssize_t ad7192_show_filter_avail(struct device *dev,
424 struct device_attribute *attr,
425 char *buf)
426 {
427 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
428 struct ad7192_state *st = iio_priv(indio_dev);
429 unsigned int freq_avail[4], i;
430 size_t len = 0;
431
432 ad7192_get_available_filter_freq(st, freq_avail);
433
434 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
435 len += scnprintf(buf + len, PAGE_SIZE - len,
436 "%d.%d ", freq_avail[i] / 1000,
437 freq_avail[i] % 1000);
438
439 buf[len - 1] = '\n';
440
441 return len;
442 }
443
444 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
445 0444, ad7192_show_filter_avail, NULL, 0);
446
447 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
448 ad7192_show_bridge_switch, ad7192_set,
449 AD7192_REG_GPOCON);
450
451 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
452 ad7192_show_ac_excitation, ad7192_set,
453 AD7192_REG_MODE);
454
455 static struct attribute *ad7192_attributes[] = {
456 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
457 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
458 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
459 NULL
460 };
461
462 static const struct attribute_group ad7192_attribute_group = {
463 .attrs = ad7192_attributes,
464 };
465
466 static struct attribute *ad7195_attributes[] = {
467 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
468 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
469 NULL
470 };
471
472 static const struct attribute_group ad7195_attribute_group = {
473 .attrs = ad7195_attributes,
474 };
475
ad7192_get_temp_scale(bool unipolar)476 static unsigned int ad7192_get_temp_scale(bool unipolar)
477 {
478 return unipolar ? 2815 * 2 : 2815;
479 }
480
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)481 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
482 int val, int val2)
483 {
484 int freq_avail[4], i, ret, freq;
485 unsigned int diff_new, diff_old;
486 int idx = 0;
487
488 diff_old = U32_MAX;
489 freq = val * 1000 + val2;
490
491 ad7192_get_available_filter_freq(st, freq_avail);
492
493 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
494 diff_new = abs(freq - freq_avail[i]);
495 if (diff_new < diff_old) {
496 diff_old = diff_new;
497 idx = i;
498 }
499 }
500
501 switch (idx) {
502 case 0:
503 st->f_order = AD7192_SYNC4_FILTER;
504 st->mode &= ~AD7192_MODE_SINC3;
505
506 st->conf |= AD7192_CONF_CHOP;
507 break;
508 case 1:
509 st->f_order = AD7192_SYNC3_FILTER;
510 st->mode |= AD7192_MODE_SINC3;
511
512 st->conf |= AD7192_CONF_CHOP;
513 break;
514 case 2:
515 st->f_order = AD7192_NO_SYNC_FILTER;
516 st->mode &= ~AD7192_MODE_SINC3;
517
518 st->conf &= ~AD7192_CONF_CHOP;
519 break;
520 case 3:
521 st->f_order = AD7192_NO_SYNC_FILTER;
522 st->mode |= AD7192_MODE_SINC3;
523
524 st->conf &= ~AD7192_CONF_CHOP;
525 break;
526 }
527
528 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
529 if (ret < 0)
530 return ret;
531
532 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
533 }
534
ad7192_get_3db_filter_freq(struct ad7192_state * st)535 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
536 {
537 unsigned int fadc;
538
539 fadc = DIV_ROUND_CLOSEST(st->fclk,
540 st->f_order * AD7192_MODE_RATE(st->mode));
541
542 if (st->conf & AD7192_CONF_CHOP)
543 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
544 if (st->mode & AD7192_MODE_SINC3)
545 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
546 else
547 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
548 }
549
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)550 static int ad7192_read_raw(struct iio_dev *indio_dev,
551 struct iio_chan_spec const *chan,
552 int *val,
553 int *val2,
554 long m)
555 {
556 struct ad7192_state *st = iio_priv(indio_dev);
557 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
558
559 switch (m) {
560 case IIO_CHAN_INFO_RAW:
561 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
562 case IIO_CHAN_INFO_SCALE:
563 switch (chan->type) {
564 case IIO_VOLTAGE:
565 mutex_lock(&st->lock);
566 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
567 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
568 mutex_unlock(&st->lock);
569 return IIO_VAL_INT_PLUS_NANO;
570 case IIO_TEMP:
571 *val = 0;
572 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
573 return IIO_VAL_INT_PLUS_NANO;
574 default:
575 return -EINVAL;
576 }
577 case IIO_CHAN_INFO_OFFSET:
578 if (!unipolar)
579 *val = -(1 << (chan->scan_type.realbits - 1));
580 else
581 *val = 0;
582 /* Kelvin to Celsius */
583 if (chan->type == IIO_TEMP)
584 *val -= 273 * ad7192_get_temp_scale(unipolar);
585 return IIO_VAL_INT;
586 case IIO_CHAN_INFO_SAMP_FREQ:
587 *val = st->fclk /
588 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
589 return IIO_VAL_INT;
590 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
591 *val = ad7192_get_3db_filter_freq(st);
592 *val2 = 1000;
593 return IIO_VAL_FRACTIONAL;
594 }
595
596 return -EINVAL;
597 }
598
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)599 static int ad7192_write_raw(struct iio_dev *indio_dev,
600 struct iio_chan_spec const *chan,
601 int val,
602 int val2,
603 long mask)
604 {
605 struct ad7192_state *st = iio_priv(indio_dev);
606 int ret, i, div;
607 unsigned int tmp;
608
609 ret = iio_device_claim_direct_mode(indio_dev);
610 if (ret)
611 return ret;
612
613 switch (mask) {
614 case IIO_CHAN_INFO_SCALE:
615 ret = -EINVAL;
616 mutex_lock(&st->lock);
617 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
618 if (val2 == st->scale_avail[i][1]) {
619 ret = 0;
620 tmp = st->conf;
621 st->conf &= ~AD7192_CONF_GAIN(-1);
622 st->conf |= AD7192_CONF_GAIN(i);
623 if (tmp == st->conf)
624 break;
625 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
626 3, st->conf);
627 ad7192_calibrate_all(st);
628 break;
629 }
630 mutex_unlock(&st->lock);
631 break;
632 case IIO_CHAN_INFO_SAMP_FREQ:
633 if (!val) {
634 ret = -EINVAL;
635 break;
636 }
637
638 div = st->fclk / (val * st->f_order * 1024);
639 if (div < 1 || div > 1023) {
640 ret = -EINVAL;
641 break;
642 }
643
644 st->mode &= ~AD7192_MODE_RATE(-1);
645 st->mode |= AD7192_MODE_RATE(div);
646 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
647 break;
648 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
649 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
650 break;
651 default:
652 ret = -EINVAL;
653 }
654
655 iio_device_release_direct_mode(indio_dev);
656
657 return ret;
658 }
659
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)660 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
661 struct iio_chan_spec const *chan,
662 long mask)
663 {
664 switch (mask) {
665 case IIO_CHAN_INFO_SCALE:
666 return IIO_VAL_INT_PLUS_NANO;
667 case IIO_CHAN_INFO_SAMP_FREQ:
668 return IIO_VAL_INT;
669 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
670 return IIO_VAL_INT_PLUS_MICRO;
671 default:
672 return -EINVAL;
673 }
674 }
675
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)676 static int ad7192_read_avail(struct iio_dev *indio_dev,
677 struct iio_chan_spec const *chan,
678 const int **vals, int *type, int *length,
679 long mask)
680 {
681 struct ad7192_state *st = iio_priv(indio_dev);
682
683 switch (mask) {
684 case IIO_CHAN_INFO_SCALE:
685 *vals = (int *)st->scale_avail;
686 *type = IIO_VAL_INT_PLUS_NANO;
687 /* Values are stored in a 2D matrix */
688 *length = ARRAY_SIZE(st->scale_avail) * 2;
689
690 return IIO_AVAIL_LIST;
691 }
692
693 return -EINVAL;
694 }
695
696 static const struct iio_info ad7192_info = {
697 .read_raw = ad7192_read_raw,
698 .write_raw = ad7192_write_raw,
699 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
700 .read_avail = ad7192_read_avail,
701 .attrs = &ad7192_attribute_group,
702 .validate_trigger = ad_sd_validate_trigger,
703 };
704
705 static const struct iio_info ad7195_info = {
706 .read_raw = ad7192_read_raw,
707 .write_raw = ad7192_write_raw,
708 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
709 .read_avail = ad7192_read_avail,
710 .attrs = &ad7195_attribute_group,
711 .validate_trigger = ad_sd_validate_trigger,
712 };
713
714 static const struct iio_chan_spec ad7192_channels[] = {
715 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
716 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
717 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
718 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
719 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
720 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
721 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
722 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
723 IIO_CHAN_SOFT_TIMESTAMP(8),
724 };
725
726 static const struct iio_chan_spec ad7193_channels[] = {
727 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
728 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
729 AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
730 AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
731 AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
732 AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
733 AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
734 AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
735 AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
736 AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
737 AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
738 AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
739 AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
740 AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
741 IIO_CHAN_SOFT_TIMESTAMP(14),
742 };
743
ad7192_channels_config(struct iio_dev * indio_dev)744 static int ad7192_channels_config(struct iio_dev *indio_dev)
745 {
746 struct ad7192_state *st = iio_priv(indio_dev);
747 const struct iio_chan_spec *channels;
748 struct iio_chan_spec *chan;
749 int i;
750
751 switch (st->devid) {
752 case ID_AD7193:
753 channels = ad7193_channels;
754 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
755 break;
756 default:
757 channels = ad7192_channels;
758 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
759 break;
760 }
761
762 chan = devm_kcalloc(indio_dev->dev.parent, indio_dev->num_channels,
763 sizeof(*chan), GFP_KERNEL);
764 if (!chan)
765 return -ENOMEM;
766
767 indio_dev->channels = chan;
768
769 for (i = 0; i < indio_dev->num_channels; i++) {
770 *chan = channels[i];
771 chan->info_mask_shared_by_all |=
772 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY);
773 if (chan->type != IIO_TEMP)
774 chan->info_mask_shared_by_type_available |=
775 BIT(IIO_CHAN_INFO_SCALE);
776 chan++;
777 }
778
779 return 0;
780 }
781
ad7192_probe(struct spi_device * spi)782 static int ad7192_probe(struct spi_device *spi)
783 {
784 struct ad7192_state *st;
785 struct iio_dev *indio_dev;
786 int ret, voltage_uv = 0;
787
788 if (!spi->irq) {
789 dev_err(&spi->dev, "no IRQ?\n");
790 return -ENODEV;
791 }
792
793 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
794 if (!indio_dev)
795 return -ENOMEM;
796
797 st = iio_priv(indio_dev);
798
799 mutex_init(&st->lock);
800
801 st->avdd = devm_regulator_get(&spi->dev, "avdd");
802 if (IS_ERR(st->avdd))
803 return PTR_ERR(st->avdd);
804
805 ret = regulator_enable(st->avdd);
806 if (ret) {
807 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
808 return ret;
809 }
810
811 st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
812 if (IS_ERR(st->dvdd)) {
813 ret = PTR_ERR(st->dvdd);
814 goto error_disable_avdd;
815 }
816
817 ret = regulator_enable(st->dvdd);
818 if (ret) {
819 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
820 goto error_disable_avdd;
821 }
822
823 voltage_uv = regulator_get_voltage(st->avdd);
824
825 if (voltage_uv)
826 st->int_vref_mv = voltage_uv / 1000;
827 else
828 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
829
830 spi_set_drvdata(spi, indio_dev);
831 st->devid = spi_get_device_id(spi)->driver_data;
832 indio_dev->dev.parent = &spi->dev;
833 indio_dev->name = spi_get_device_id(spi)->name;
834 indio_dev->modes = INDIO_DIRECT_MODE;
835
836 ret = ad7192_channels_config(indio_dev);
837 if (ret < 0)
838 goto error_disable_dvdd;
839
840 if (st->devid == ID_AD7195)
841 indio_dev->info = &ad7195_info;
842 else
843 indio_dev->info = &ad7192_info;
844
845 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
846
847 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
848 if (ret)
849 goto error_disable_dvdd;
850
851 st->fclk = AD7192_INT_FREQ_MHZ;
852
853 st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk");
854 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) {
855 ret = PTR_ERR(st->mclk);
856 goto error_remove_trigger;
857 }
858
859 st->clock_sel = ad7192_of_clock_select(st);
860
861 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
862 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
863 ret = clk_prepare_enable(st->mclk);
864 if (ret < 0)
865 goto error_remove_trigger;
866
867 st->fclk = clk_get_rate(st->mclk);
868 if (!ad7192_valid_external_frequency(st->fclk)) {
869 ret = -EINVAL;
870 dev_err(&spi->dev,
871 "External clock frequency out of bounds\n");
872 goto error_disable_clk;
873 }
874 }
875
876 ret = ad7192_setup(st, spi->dev.of_node);
877 if (ret)
878 goto error_disable_clk;
879
880 ret = iio_device_register(indio_dev);
881 if (ret < 0)
882 goto error_disable_clk;
883 return 0;
884
885 error_disable_clk:
886 clk_disable_unprepare(st->mclk);
887 error_remove_trigger:
888 ad_sd_cleanup_buffer_and_trigger(indio_dev);
889 error_disable_dvdd:
890 regulator_disable(st->dvdd);
891 error_disable_avdd:
892 regulator_disable(st->avdd);
893
894 return ret;
895 }
896
ad7192_remove(struct spi_device * spi)897 static int ad7192_remove(struct spi_device *spi)
898 {
899 struct iio_dev *indio_dev = spi_get_drvdata(spi);
900 struct ad7192_state *st = iio_priv(indio_dev);
901
902 iio_device_unregister(indio_dev);
903 clk_disable_unprepare(st->mclk);
904 ad_sd_cleanup_buffer_and_trigger(indio_dev);
905
906 regulator_disable(st->dvdd);
907 regulator_disable(st->avdd);
908
909 return 0;
910 }
911
912 static const struct spi_device_id ad7192_id[] = {
913 {"ad7190", ID_AD7190},
914 {"ad7192", ID_AD7192},
915 {"ad7193", ID_AD7193},
916 {"ad7195", ID_AD7195},
917 {}
918 };
919
920 MODULE_DEVICE_TABLE(spi, ad7192_id);
921
922 static const struct of_device_id ad7192_of_match[] = {
923 { .compatible = "adi,ad7190" },
924 { .compatible = "adi,ad7192" },
925 { .compatible = "adi,ad7193" },
926 { .compatible = "adi,ad7195" },
927 {}
928 };
929
930 MODULE_DEVICE_TABLE(of, ad7192_of_match);
931
932 static struct spi_driver ad7192_driver = {
933 .driver = {
934 .name = "ad7192",
935 .of_match_table = ad7192_of_match,
936 },
937 .probe = ad7192_probe,
938 .remove = ad7192_remove,
939 .id_table = ad7192_id,
940 };
941 module_spi_driver(ad7192_driver);
942
943 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
944 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
945 MODULE_LICENSE("GPL v2");
946