1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * KP2000 SPI controller driver
4 *
5 * Copyright (C) 2014-2018 Daktronics
6 * Author: Matt Sickler <matt.sickler@daktronics.com>
7 * Very loosely based on spi-omap2-mcspi.c
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/gcd.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/flash.h>
28 #include <linux/mtd/partitions.h>
29
30 #include "kpc.h"
31
32 static struct mtd_partition p2kr0_spi0_parts[] = {
33 { .name = "SLOT_0", .size = 7798784, .offset = 0, },
34 { .name = "SLOT_1", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
35 { .name = "SLOT_2", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
36 { .name = "SLOT_3", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
37 { .name = "CS0_EXTRA", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_NXTBLK},
38 };
39
40 static struct mtd_partition p2kr0_spi1_parts[] = {
41 { .name = "SLOT_4", .size = 7798784, .offset = 0, },
42 { .name = "SLOT_5", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
43 { .name = "SLOT_6", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
44 { .name = "SLOT_7", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
45 { .name = "CS1_EXTRA", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_NXTBLK},
46 };
47
48 static struct flash_platform_data p2kr0_spi0_pdata = {
49 .name = "SPI0",
50 .nr_parts = ARRAY_SIZE(p2kr0_spi0_parts),
51 .parts = p2kr0_spi0_parts,
52 };
53 static struct flash_platform_data p2kr0_spi1_pdata = {
54 .name = "SPI1",
55 .nr_parts = ARRAY_SIZE(p2kr0_spi1_parts),
56 .parts = p2kr0_spi1_parts,
57 };
58
59 static struct spi_board_info p2kr0_board_info[] = {
60 {
61 .modalias = "n25q256a11",
62 .bus_num = 1,
63 .chip_select = 0,
64 .mode = SPI_MODE_0,
65 .platform_data = &p2kr0_spi0_pdata
66 },
67 {
68 .modalias = "n25q256a11",
69 .bus_num = 1,
70 .chip_select = 1,
71 .mode = SPI_MODE_0,
72 .platform_data = &p2kr0_spi1_pdata
73 },
74 };
75
76 /***************
77 * SPI Defines *
78 ***************/
79 #define KP_SPI_REG_CONFIG 0x0 /* 0x00 */
80 #define KP_SPI_REG_STATUS 0x1 /* 0x08 */
81 #define KP_SPI_REG_FFCTRL 0x2 /* 0x10 */
82 #define KP_SPI_REG_TXDATA 0x3 /* 0x18 */
83 #define KP_SPI_REG_RXDATA 0x4 /* 0x20 */
84
85 #define KP_SPI_CLK 48000000
86 #define KP_SPI_MAX_FIFODEPTH 64
87 #define KP_SPI_MAX_FIFOWCNT 0xFFFF
88
89 #define KP_SPI_REG_CONFIG_TRM_TXRX 0
90 #define KP_SPI_REG_CONFIG_TRM_RX 1
91 #define KP_SPI_REG_CONFIG_TRM_TX 2
92
93 #define KP_SPI_REG_STATUS_RXS 0x01
94 #define KP_SPI_REG_STATUS_TXS 0x02
95 #define KP_SPI_REG_STATUS_EOT 0x04
96 #define KP_SPI_REG_STATUS_TXFFE 0x10
97 #define KP_SPI_REG_STATUS_TXFFF 0x20
98 #define KP_SPI_REG_STATUS_RXFFE 0x40
99 #define KP_SPI_REG_STATUS_RXFFF 0x80
100
101 /******************
102 * SPI Structures *
103 ******************/
104 struct kp_spi {
105 struct spi_master *master;
106 u64 __iomem *base;
107 struct device *dev;
108 };
109
110 struct kp_spi_controller_state {
111 void __iomem *base;
112 s64 conf_cache;
113 };
114
115 union kp_spi_config {
116 /* use this to access individual elements */
117 struct __packed spi_config_bitfield {
118 unsigned int pha : 1; /* spim_clk Phase */
119 unsigned int pol : 1; /* spim_clk Polarity */
120 unsigned int epol : 1; /* spim_csx Polarity */
121 unsigned int dpe : 1; /* Transmission Enable */
122 unsigned int wl : 5; /* Word Length */
123 unsigned int : 3;
124 unsigned int trm : 2; /* TxRx Mode */
125 unsigned int cs : 4; /* Chip Select */
126 unsigned int wcnt : 7; /* Word Count */
127 unsigned int ffen : 1; /* FIFO Enable */
128 unsigned int spi_en : 1; /* SPI Enable */
129 unsigned int : 5;
130 } bitfield;
131 /* use this to grab the whole register */
132 u32 reg;
133 };
134
135 union kp_spi_status {
136 struct __packed spi_status_bitfield {
137 unsigned int rx : 1; /* Rx Status */
138 unsigned int tx : 1; /* Tx Status */
139 unsigned int eo : 1; /* End of Transfer */
140 unsigned int : 1;
141 unsigned int txffe : 1; /* Tx FIFO Empty */
142 unsigned int txfff : 1; /* Tx FIFO Full */
143 unsigned int rxffe : 1; /* Rx FIFO Empty */
144 unsigned int rxfff : 1; /* Rx FIFO Full */
145 unsigned int : 24;
146 } bitfield;
147 u32 reg;
148 };
149
150 union kp_spi_ffctrl {
151 struct __packed spi_ffctrl_bitfield {
152 unsigned int ffstart : 1; /* FIFO Start */
153 unsigned int : 31;
154 } bitfield;
155 u32 reg;
156 };
157
158 /***************
159 * SPI Helpers *
160 ***************/
161 static inline u64
kp_spi_read_reg(struct kp_spi_controller_state * cs,int idx)162 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx)
163 {
164 u64 __iomem *addr = cs->base;
165 u64 val;
166
167 addr += idx;
168 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0))
169 return cs->conf_cache;
170
171 val = readq(addr);
172 return val;
173 }
174
175 static inline void
kp_spi_write_reg(struct kp_spi_controller_state * cs,int idx,u64 val)176 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val)
177 {
178 u64 __iomem *addr = cs->base;
179
180 addr += idx;
181 writeq(val, addr);
182 if (idx == KP_SPI_REG_CONFIG)
183 cs->conf_cache = val;
184 }
185
186 static int
kp_spi_wait_for_reg_bit(struct kp_spi_controller_state * cs,int idx,unsigned long bit)187 kp_spi_wait_for_reg_bit(struct kp_spi_controller_state *cs, int idx,
188 unsigned long bit)
189 {
190 unsigned long timeout;
191
192 timeout = jiffies + msecs_to_jiffies(1000);
193 while (!(kp_spi_read_reg(cs, idx) & bit)) {
194 if (time_after(jiffies, timeout)) {
195 if (!(kp_spi_read_reg(cs, idx) & bit))
196 return -ETIMEDOUT;
197 else
198 return 0;
199 }
200 cpu_relax();
201 }
202 return 0;
203 }
204
205 static unsigned
kp_spi_txrx_pio(struct spi_device * spidev,struct spi_transfer * transfer)206 kp_spi_txrx_pio(struct spi_device *spidev, struct spi_transfer *transfer)
207 {
208 struct kp_spi_controller_state *cs = spidev->controller_state;
209 unsigned int count = transfer->len;
210 unsigned int c = count;
211
212 int i;
213 int res;
214 u8 *rx = transfer->rx_buf;
215 const u8 *tx = transfer->tx_buf;
216 int processed = 0;
217
218 if (tx) {
219 for (i = 0 ; i < c ; i++) {
220 char val = *tx++;
221
222 res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
223 KP_SPI_REG_STATUS_TXS);
224 if (res < 0)
225 goto out;
226
227 kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, val);
228 processed++;
229 }
230 }
231 else if (rx) {
232 for (i = 0 ; i < c ; i++) {
233 char test = 0;
234
235 kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, 0x00);
236 res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
237 KP_SPI_REG_STATUS_RXS);
238 if (res < 0)
239 goto out;
240
241 test = kp_spi_read_reg(cs, KP_SPI_REG_RXDATA);
242 *rx++ = test;
243 processed++;
244 }
245 }
246
247 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
248 KP_SPI_REG_STATUS_EOT) < 0) {
249 //TODO: Figure out how to abort transaction??
250 //Ths has never happened in practice though...
251 }
252
253 out:
254 return processed;
255 }
256
257 /*****************
258 * SPI Functions *
259 *****************/
260 static int
kp_spi_setup(struct spi_device * spidev)261 kp_spi_setup(struct spi_device *spidev)
262 {
263 union kp_spi_config sc;
264 struct kp_spi *kpspi = spi_master_get_devdata(spidev->master);
265 struct kp_spi_controller_state *cs;
266
267 /* setup controller state */
268 cs = spidev->controller_state;
269 if (!cs) {
270 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
271 if (!cs)
272 return -ENOMEM;
273 cs->base = kpspi->base;
274 cs->conf_cache = -1;
275 spidev->controller_state = cs;
276 }
277
278 /* set config register */
279 sc.bitfield.wl = spidev->bits_per_word - 1;
280 sc.bitfield.cs = spidev->chip_select;
281 sc.bitfield.spi_en = 0;
282 sc.bitfield.trm = 0;
283 sc.bitfield.ffen = 0;
284 kp_spi_write_reg(spidev->controller_state, KP_SPI_REG_CONFIG, sc.reg);
285 return 0;
286 }
287
288 static int
kp_spi_transfer_one_message(struct spi_master * master,struct spi_message * m)289 kp_spi_transfer_one_message(struct spi_master *master, struct spi_message *m)
290 {
291 struct kp_spi_controller_state *cs;
292 struct spi_device *spidev;
293 struct kp_spi *kpspi;
294 struct spi_transfer *transfer;
295 union kp_spi_config sc;
296 int status = 0;
297
298 spidev = m->spi;
299 kpspi = spi_master_get_devdata(master);
300 m->actual_length = 0;
301 m->status = 0;
302
303 cs = spidev->controller_state;
304
305 /* reject invalid messages and transfers */
306 if (list_empty(&m->transfers))
307 return -EINVAL;
308
309 /* validate input */
310 list_for_each_entry(transfer, &m->transfers, transfer_list) {
311 const void *tx_buf = transfer->tx_buf;
312 void *rx_buf = transfer->rx_buf;
313 unsigned int len = transfer->len;
314
315 if (transfer->speed_hz > KP_SPI_CLK ||
316 (len && !(rx_buf || tx_buf))) {
317 dev_dbg(kpspi->dev, " transfer: %d Hz, %d %s%s, %d bpw\n",
318 transfer->speed_hz,
319 len,
320 tx_buf ? "tx" : "",
321 rx_buf ? "rx" : "",
322 transfer->bits_per_word);
323 dev_dbg(kpspi->dev, " transfer -EINVAL\n");
324 return -EINVAL;
325 }
326 if (transfer->speed_hz &&
327 transfer->speed_hz < (KP_SPI_CLK >> 15)) {
328 dev_dbg(kpspi->dev, "speed_hz %d below minimum %d Hz\n",
329 transfer->speed_hz,
330 KP_SPI_CLK >> 15);
331 dev_dbg(kpspi->dev, " speed_hz -EINVAL\n");
332 return -EINVAL;
333 }
334 }
335
336 /* assert chip select to start the sequence*/
337 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
338 sc.bitfield.spi_en = 1;
339 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
340
341 /* work */
342 if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
343 KP_SPI_REG_STATUS_EOT) < 0) {
344 dev_info(kpspi->dev, "EOT timed out\n");
345 goto out;
346 }
347
348 /* do the transfers for this message */
349 list_for_each_entry(transfer, &m->transfers, transfer_list) {
350 if (!transfer->tx_buf && !transfer->rx_buf &&
351 transfer->len) {
352 status = -EINVAL;
353 goto error;
354 }
355
356 /* transfer */
357 if (transfer->len) {
358 unsigned int word_len = spidev->bits_per_word;
359 unsigned int count;
360
361 /* set up the transfer... */
362 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
363
364 /* ...direction */
365 if (transfer->tx_buf)
366 sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_TX;
367 else if (transfer->rx_buf)
368 sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_RX;
369
370 /* ...word length */
371 if (transfer->bits_per_word)
372 word_len = transfer->bits_per_word;
373 sc.bitfield.wl = word_len - 1;
374
375 /* ...chip select */
376 sc.bitfield.cs = spidev->chip_select;
377
378 /* ...and write the new settings */
379 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
380
381 /* do the transfer */
382 count = kp_spi_txrx_pio(spidev, transfer);
383 m->actual_length += count;
384
385 if (count != transfer->len) {
386 status = -EIO;
387 goto error;
388 }
389 }
390
391 if (transfer->delay_usecs)
392 udelay(transfer->delay_usecs);
393 }
394
395 /* de-assert chip select to end the sequence */
396 sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
397 sc.bitfield.spi_en = 0;
398 kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
399
400 out:
401 /* done work */
402 spi_finalize_current_message(master);
403 return 0;
404
405 error:
406 m->status = status;
407 return status;
408 }
409
410 static void
kp_spi_cleanup(struct spi_device * spidev)411 kp_spi_cleanup(struct spi_device *spidev)
412 {
413 struct kp_spi_controller_state *cs = spidev->controller_state;
414
415 kfree(cs);
416 }
417
418 /******************
419 * Probe / Remove *
420 ******************/
421 static int
kp_spi_probe(struct platform_device * pldev)422 kp_spi_probe(struct platform_device *pldev)
423 {
424 struct kpc_core_device_platdata *drvdata;
425 struct spi_master *master;
426 struct kp_spi *kpspi;
427 struct resource *r;
428 int status = 0;
429 int i;
430
431 drvdata = pldev->dev.platform_data;
432 if (!drvdata) {
433 dev_err(&pldev->dev, "%s: platform_data is NULL\n", __func__);
434 return -ENODEV;
435 }
436
437 master = spi_alloc_master(&pldev->dev, sizeof(struct kp_spi));
438 if (!master) {
439 dev_err(&pldev->dev, "%s: master allocation failed\n",
440 __func__);
441 return -ENOMEM;
442 }
443
444 /* set up the spi functions */
445 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
446 master->bits_per_word_mask = (unsigned int)SPI_BPW_RANGE_MASK(4, 32);
447 master->setup = kp_spi_setup;
448 master->transfer_one_message = kp_spi_transfer_one_message;
449 master->cleanup = kp_spi_cleanup;
450
451 platform_set_drvdata(pldev, master);
452
453 kpspi = spi_master_get_devdata(master);
454 kpspi->master = master;
455 kpspi->dev = &pldev->dev;
456
457 master->num_chipselect = 4;
458 if (pldev->id != -1)
459 master->bus_num = pldev->id;
460
461 r = platform_get_resource(pldev, IORESOURCE_MEM, 0);
462 if (!r) {
463 dev_err(&pldev->dev, "%s: Unable to get platform resources\n",
464 __func__);
465 status = -ENODEV;
466 goto free_master;
467 }
468
469 kpspi->base = devm_ioremap_nocache(&pldev->dev, r->start,
470 resource_size(r));
471
472 status = spi_register_master(master);
473 if (status < 0) {
474 dev_err(&pldev->dev, "Unable to register SPI device\n");
475 goto free_master;
476 }
477
478 /* register the slave boards */
479 #define NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(table) \
480 for (i = 0 ; i < ARRAY_SIZE(table) ; i++) { \
481 spi_new_device(master, &(table[i])); \
482 }
483
484 switch ((drvdata->card_id & 0xFFFF0000) >> 16) {
485 case PCI_DEVICE_ID_DAKTRONICS_KADOKA_P2KR0:
486 NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(p2kr0_board_info);
487 break;
488 default:
489 dev_err(&pldev->dev, "Unknown hardware, cant know what partition table to use!\n");
490 goto free_master;
491 }
492
493 return status;
494
495 free_master:
496 spi_master_put(master);
497 return status;
498 }
499
500 static int
kp_spi_remove(struct platform_device * pldev)501 kp_spi_remove(struct platform_device *pldev)
502 {
503 struct spi_master *master = platform_get_drvdata(pldev);
504
505 spi_unregister_master(master);
506 return 0;
507 }
508
509 static struct platform_driver kp_spi_driver = {
510 .driver = {
511 .name = KP_DRIVER_NAME_SPI,
512 },
513 .probe = kp_spi_probe,
514 .remove = kp_spi_remove,
515 };
516
517 module_platform_driver(kp_spi_driver);
518 MODULE_LICENSE("GPL");
519 MODULE_ALIAS("platform:kp_spi");
520