1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #define _RTL8723B_PHYCFG_C_
8
9 #include <drv_types.h>
10 #include <rtw_debug.h>
11 #include <rtl8723b_hal.h>
12
13
14 /*---------------------------Define Local Constant---------------------------*/
15 /* Channel switch:The size of command tables for switch channel*/
16 #define MAX_PRECMD_CNT 16
17 #define MAX_RFDEPENDCMD_CNT 16
18 #define MAX_POSTCMD_CNT 16
19
20 #define MAX_DOZE_WAITING_TIMES_9x 64
21
22 /**
23 * Function: phy_CalculateBitShift
24 *
25 * OverView: Get shifted position of the BitMask
26 *
27 * Input:
28 * u32 BitMask,
29 *
30 * Output: none
31 * Return: u32 Return the shift bit bit position of the mask
32 */
phy_CalculateBitShift(u32 BitMask)33 static u32 phy_CalculateBitShift(u32 BitMask)
34 {
35 u32 i;
36
37 for (i = 0; i <= 31; i++) {
38 if (((BitMask>>i) & 0x1) == 1)
39 break;
40 }
41 return i;
42 }
43
44
45 /**
46 * Function: PHY_QueryBBReg
47 *
48 * OverView: Read "specific bits" from BB register
49 *
50 * Input:
51 * struct adapter * Adapter,
52 * u32 RegAddr, The target address to be readback
53 * u32 BitMask The target bit position in the target address
54 * to be readback
55 * Output: None
56 * Return: u32 Data The readback register value
57 * Note: This function is equal to "GetRegSetting" in PHY programming guide
58 */
PHY_QueryBBReg_8723B(struct adapter * Adapter,u32 RegAddr,u32 BitMask)59 u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
60 {
61 u32 OriginalValue, BitShift;
62
63 #if (DISABLE_BB_RF == 1)
64 return 0;
65 #endif
66
67 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */
68
69 OriginalValue = rtw_read32(Adapter, RegAddr);
70 BitShift = phy_CalculateBitShift(BitMask);
71
72 return (OriginalValue & BitMask) >> BitShift;
73
74 }
75
76
77 /**
78 * Function: PHY_SetBBReg
79 *
80 * OverView: Write "Specific bits" to BB register (page 8~)
81 *
82 * Input:
83 * struct adapter * Adapter,
84 * u32 RegAddr, The target address to be modified
85 * u32 BitMask The target bit position in the target address
86 * to be modified
87 * u32 Data The new register value in the target bit position
88 * of the target address
89 *
90 * Output: None
91 * Return: None
92 * Note: This function is equal to "PutRegSetting" in PHY programming guide
93 */
94
PHY_SetBBReg_8723B(struct adapter * Adapter,u32 RegAddr,u32 BitMask,u32 Data)95 void PHY_SetBBReg_8723B(
96 struct adapter *Adapter,
97 u32 RegAddr,
98 u32 BitMask,
99 u32 Data
100 )
101 {
102 /* u16 BBWaitCounter = 0; */
103 u32 OriginalValue, BitShift;
104
105 #if (DISABLE_BB_RF == 1)
106 return;
107 #endif
108
109 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
110
111 if (BitMask != bMaskDWord) { /* if not "double word" write */
112 OriginalValue = rtw_read32(Adapter, RegAddr);
113 BitShift = phy_CalculateBitShift(BitMask);
114 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
115 }
116
117 rtw_write32(Adapter, RegAddr, Data);
118
119 }
120
121
122 /* */
123 /* 2. RF register R/W API */
124 /* */
125
phy_RFSerialRead_8723B(struct adapter * Adapter,enum RF_PATH eRFPath,u32 Offset)126 static u32 phy_RFSerialRead_8723B(
127 struct adapter *Adapter, enum RF_PATH eRFPath, u32 Offset
128 )
129 {
130 u32 retValue = 0;
131 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
132 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
133 u32 NewOffset;
134 u32 tmplong2;
135 u8 RfPiEnable = 0;
136 u32 MaskforPhySet = 0;
137 int i = 0;
138
139 /* */
140 /* Make sure RF register offset is correct */
141 /* */
142 Offset &= 0xff;
143
144 NewOffset = Offset;
145
146 if (eRFPath == RF_PATH_A) {
147 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
148 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
149 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
150 } else {
151 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
152 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
153 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
154 }
155
156 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
157 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
158 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
159
160 udelay(10);
161
162 for (i = 0; i < 2; i++)
163 udelay(MAX_STALL_TIME);
164 udelay(10);
165
166 if (eRFPath == RF_PATH_A)
167 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
168 else if (eRFPath == RF_PATH_B)
169 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
170
171 if (RfPiEnable) {
172 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
173 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
174
175 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
176 } else {
177 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
178 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
179
180 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-SI : 0x%x\n", retValue)); */
181 }
182 return retValue;
183
184 }
185
186 /**
187 * Function: phy_RFSerialWrite_8723B
188 *
189 * OverView: Write data to RF register (page 8~)
190 *
191 * Input:
192 * struct adapter * Adapter,
193 * RF_PATH eRFPath, Radio path of A/B/C/D
194 * u32 Offset, The target address to be read
195 * u32 Data The new register Data in the target bit position
196 * of the target to be read
197 *
198 * Output: None
199 * Return: None
200 * Note: Threre are three types of serial operations:
201 * 1. Software serial write
202 * 2. Hardware LSSI-Low Speed Serial Interface
203 * 3. Hardware HSSI-High speed
204 * serial write. Driver need to implement (1) and (2).
205 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
206 *
207 * Note: For RF8256 only
208 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
209 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
210 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
211 * programming guide" for more details.
212 * Thus, we define a sub-finction for RTL8526 register address conversion
213 * ===========================================================
214 * Register Mode RegCTL[1] RegCTL[0] Note
215 * (Reg00[12]) (Reg00[10])
216 * ===========================================================
217 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
218 * ------------------------------------------------------------------
219 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
220 * ------------------------------------------------------------------
221 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
222 * ------------------------------------------------------------------
223 *
224 *2008/09/02 MH Add 92S RF definition
225 *
226 *
227 *
228 */
phy_RFSerialWrite_8723B(struct adapter * Adapter,enum RF_PATH eRFPath,u32 Offset,u32 Data)229 static void phy_RFSerialWrite_8723B(
230 struct adapter *Adapter,
231 enum RF_PATH eRFPath,
232 u32 Offset,
233 u32 Data
234 )
235 {
236 u32 DataAndAddr = 0;
237 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
238 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
239 u32 NewOffset;
240
241 Offset &= 0xff;
242
243 /* */
244 /* Switch page for 8256 RF IC */
245 /* */
246 NewOffset = Offset;
247
248 /* */
249 /* Put write addr in [5:0] and write data in [31:16] */
250 /* */
251 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
252 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */
253
254 /* */
255 /* Write Operation */
256 /* */
257 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
258 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
259
260 }
261
262
263 /**
264 * Function: PHY_QueryRFReg
265 *
266 * OverView: Query "Specific bits" to RF register (page 8~)
267 *
268 * Input:
269 * struct adapter * Adapter,
270 * RF_PATH eRFPath, Radio path of A/B/C/D
271 * u32 RegAddr, The target address to be read
272 * u32 BitMask The target bit position in the target address
273 * to be read
274 *
275 * Output: None
276 * Return: u32 Readback value
277 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
278 */
PHY_QueryRFReg_8723B(struct adapter * Adapter,u8 eRFPath,u32 RegAddr,u32 BitMask)279 u32 PHY_QueryRFReg_8723B(
280 struct adapter *Adapter,
281 u8 eRFPath,
282 u32 RegAddr,
283 u32 BitMask
284 )
285 {
286 u32 Original_Value, BitShift;
287
288 #if (DISABLE_BB_RF == 1)
289 return 0;
290 #endif
291
292 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
293 BitShift = phy_CalculateBitShift(BitMask);
294
295 return (Original_Value & BitMask) >> BitShift;
296 }
297
298 /**
299 * Function: PHY_SetRFReg
300 *
301 * OverView: Write "Specific bits" to RF register (page 8~)
302 *
303 * Input:
304 * struct adapter * Adapter,
305 * RF_PATH eRFPath, Radio path of A/B/C/D
306 * u32 RegAddr, The target address to be modified
307 * u32 BitMask The target bit position in the target address
308 * to be modified
309 * u32 Data The new register Data in the target bit position
310 * of the target address
311 *
312 * Output: None
313 * Return: None
314 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
315 */
PHY_SetRFReg_8723B(struct adapter * Adapter,u8 eRFPath,u32 RegAddr,u32 BitMask,u32 Data)316 void PHY_SetRFReg_8723B(
317 struct adapter *Adapter,
318 u8 eRFPath,
319 u32 RegAddr,
320 u32 BitMask,
321 u32 Data
322 )
323 {
324 u32 Original_Value, BitShift;
325
326 #if (DISABLE_BB_RF == 1)
327 return;
328 #endif
329
330 /* RF data is 12 bits only */
331 if (BitMask != bRFRegOffsetMask) {
332 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
333 BitShift = phy_CalculateBitShift(BitMask);
334 Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
335 }
336
337 phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
338 }
339
340
341 /* */
342 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
343 /* */
344
345
346 /*-----------------------------------------------------------------------------
347 * Function: PHY_MACConfig8192C
348 *
349 * Overview: Condig MAC by header file or parameter file.
350 *
351 * Input: NONE
352 *
353 * Output: NONE
354 *
355 * Return: NONE
356 *
357 * Revised History:
358 * When Who Remark
359 * 08/12/2008 MHC Create Version 0.
360 *
361 *---------------------------------------------------------------------------
362 */
PHY_MACConfig8723B(struct adapter * Adapter)363 s32 PHY_MACConfig8723B(struct adapter *Adapter)
364 {
365 int rtStatus = _SUCCESS;
366 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
367 s8 *pszMACRegFile;
368 s8 sz8723MACRegFile[] = RTL8723B_PHY_MACREG;
369
370
371 pszMACRegFile = sz8723MACRegFile;
372
373 /* */
374 /* Config MAC */
375 /* */
376 rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
377 if (rtStatus == _FAIL) {
378 ODM_ReadAndConfig_MP_8723B_MAC_REG(&pHalData->odmpriv);
379 rtStatus = _SUCCESS;
380 }
381
382 return rtStatus;
383 }
384
385 /**
386 * Function: phy_InitBBRFRegisterDefinition
387 *
388 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
389 *
390 * Input:
391 * struct adapter * Adapter,
392 *
393 * Output: None
394 * Return: None
395 * Note: The initialization value is constant and it should never be changes
396 */
phy_InitBBRFRegisterDefinition(struct adapter * Adapter)397 static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
398 {
399 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
400
401 /* RF Interface Sowrtware Control */
402 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
403 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
404
405 /* RF Interface Output (and Enable) */
406 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
407 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
408
409 /* RF Interface (Output and) Enable */
410 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
411 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
412
413 pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
414 pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
415
416 pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
417 pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
418
419 /* Tranceiver Readback LSSI/HSPI mode */
420 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
421 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
422 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
423 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
424
425 }
426
phy_BB8723b_Config_ParaFile(struct adapter * Adapter)427 static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
428 {
429 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
430 int rtStatus = _SUCCESS;
431 u8 sz8723BBRegFile[] = RTL8723B_PHY_REG;
432 u8 sz8723AGCTableFile[] = RTL8723B_AGC_TAB;
433 u8 sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG;
434 u8 sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT;
435 u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszRFTxPwrLmtFile = NULL;
436
437 pszBBRegFile = sz8723BBRegFile;
438 pszAGCTableFile = sz8723AGCTableFile;
439 pszBBRegPgFile = sz8723BBBRegPgFile;
440 pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile;
441
442 /* Read Tx Power Limit File */
443 PHY_InitTxPowerLimit(Adapter);
444 if (
445 Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
446 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
447 ) {
448 if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) {
449 if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))
450 rtStatus = _FAIL;
451 }
452
453 if (rtStatus != _SUCCESS) {
454 DBG_871X("%s():Read Tx power limit fail\n", __func__);
455 goto phy_BB8190_Config_ParaFile_Fail;
456 }
457 }
458
459 /* */
460 /* 1. Read PHY_REG.TXT BB INIT!! */
461 /* */
462 if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) ==
463 _FAIL) {
464 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
465 rtStatus = _FAIL;
466 }
467
468 if (rtStatus != _SUCCESS) {
469 DBG_8192C("%s():Write BB Reg Fail!!", __func__);
470 goto phy_BB8190_Config_ParaFile_Fail;
471 }
472
473 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
474 PHY_InitTxPowerByRate(Adapter);
475 if (
476 Adapter->registrypriv.RegEnableTxPowerByRate == 1 ||
477 (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2)
478 ) {
479 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) ==
480 _FAIL) {
481 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
482 rtStatus = _FAIL;
483 }
484
485 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE)
486 PHY_TxPowerByRateConfiguration(Adapter);
487
488 if (
489 Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
490 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
491 )
492 PHY_ConvertTxPowerLimitToPowerIndex(Adapter);
493
494 if (rtStatus != _SUCCESS) {
495 DBG_8192C("%s():BB_PG Reg Fail!!\n", __func__);
496 }
497 }
498
499 /* */
500 /* 2. Read BB AGC table Initialization */
501 /* */
502 if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile,
503 CONFIG_BB_AGC_TAB) == _FAIL) {
504 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
505 rtStatus = _FAIL;
506 }
507
508 if (rtStatus != _SUCCESS) {
509 DBG_8192C("%s():AGC Table Fail\n", __func__);
510 goto phy_BB8190_Config_ParaFile_Fail;
511 }
512
513 phy_BB8190_Config_ParaFile_Fail:
514
515 return rtStatus;
516 }
517
518
PHY_BBConfig8723B(struct adapter * Adapter)519 int PHY_BBConfig8723B(struct adapter *Adapter)
520 {
521 int rtStatus = _SUCCESS;
522 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
523 u32 RegVal;
524 u8 CrystalCap;
525
526 phy_InitBBRFRegisterDefinition(Adapter);
527
528 /* Enable BB and RF */
529 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
530 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
531
532 rtw_write32(Adapter, 0x948, 0x280); /* Others use Antenna S1 */
533
534 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
535
536 msleep(1);
537
538 PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780);
539
540 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
541
542 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
543
544 /* */
545 /* Config BB and AGC */
546 /* */
547 rtStatus = phy_BB8723b_Config_ParaFile(Adapter);
548
549 /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
550 CrystalCap = pHalData->CrystalCap & 0x3F;
551 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
552
553 return rtStatus;
554 }
555
phy_LCK_8723B(struct adapter * Adapter)556 static void phy_LCK_8723B(struct adapter *Adapter)
557 {
558 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
559 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
560 mdelay(200);
561 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
562 }
563
PHY_RFConfig8723B(struct adapter * Adapter)564 int PHY_RFConfig8723B(struct adapter *Adapter)
565 {
566 int rtStatus = _SUCCESS;
567
568 /* */
569 /* RF config */
570 /* */
571 rtStatus = PHY_RF6052_Config8723B(Adapter);
572
573 phy_LCK_8723B(Adapter);
574 /* PHY_BB8723B_Config_1T(Adapter); */
575
576 return rtStatus;
577 }
578
579 /**************************************************************************************************************
580 * Description:
581 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
582 *
583 * <20120830, Kordan>
584 **************************************************************************************************************/
585
PHY_SetTxPowerIndex(struct adapter * Adapter,u32 PowerIndex,u8 RFPath,u8 Rate)586 void PHY_SetTxPowerIndex(
587 struct adapter *Adapter,
588 u32 PowerIndex,
589 u8 RFPath,
590 u8 Rate
591 )
592 {
593 if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) {
594 switch (Rate) {
595 case MGN_1M:
596 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
597 break;
598 case MGN_2M:
599 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
600 break;
601 case MGN_5_5M:
602 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
603 break;
604 case MGN_11M:
605 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
606 break;
607
608 case MGN_6M:
609 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
610 break;
611 case MGN_9M:
612 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
613 break;
614 case MGN_12M:
615 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
616 break;
617 case MGN_18M:
618 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
619 break;
620
621 case MGN_24M:
622 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
623 break;
624 case MGN_36M:
625 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
626 break;
627 case MGN_48M:
628 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
629 break;
630 case MGN_54M:
631 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
632 break;
633
634 case MGN_MCS0:
635 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
636 break;
637 case MGN_MCS1:
638 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
639 break;
640 case MGN_MCS2:
641 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
642 break;
643 case MGN_MCS3:
644 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
645 break;
646
647 case MGN_MCS4:
648 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
649 break;
650 case MGN_MCS5:
651 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
652 break;
653 case MGN_MCS6:
654 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
655 break;
656 case MGN_MCS7:
657 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
658 break;
659
660 default:
661 DBG_871X("Invalid Rate!!\n");
662 break;
663 }
664 } else {
665 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n"));
666 }
667 }
668
PHY_GetTxPowerIndex(struct adapter * padapter,u8 RFPath,u8 Rate,enum CHANNEL_WIDTH BandWidth,u8 Channel)669 u8 PHY_GetTxPowerIndex(
670 struct adapter *padapter,
671 u8 RFPath,
672 u8 Rate,
673 enum CHANNEL_WIDTH BandWidth,
674 u8 Channel
675 )
676 {
677 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
678 s8 txPower = 0, powerDiffByRate = 0, limit = 0;
679 bool bIn24G = false;
680
681 /* DBG_871X("===>%s\n", __func__); */
682
683 txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
684 powerDiffByRate = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
685
686 limit = phy_get_tx_pwr_lmt(
687 padapter,
688 padapter->registrypriv.RegPwrTblSel,
689 (u8)(!bIn24G),
690 pHalData->CurrentChannelBW,
691 RFPath,
692 Rate,
693 pHalData->CurrentChannel
694 );
695
696 powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate;
697 txPower += powerDiffByRate;
698
699 txPower += PHY_GetTxPowerTrackingOffset(padapter, RFPath, Rate);
700
701 if (txPower > MAX_POWER_INDEX)
702 txPower = MAX_POWER_INDEX;
703
704 /* DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath == 0)?'A':'B'), Channel, txPower, txPower)); */
705 return (u8) txPower;
706 }
707
PHY_SetTxPowerLevel8723B(struct adapter * Adapter,u8 Channel)708 void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)
709 {
710 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
711 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
712 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
713 u8 RFPath = ODM_RF_PATH_A;
714
715 if (pHalData->AntDivCfg) {/* antenna diversity Enable */
716 RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
717 } else { /* antenna diversity disable */
718 RFPath = pHalData->ant_path;
719 }
720
721 RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8723B()\n"));
722
723 PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);
724
725 RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8723B()\n"));
726 }
727
PHY_GetTxPowerLevel8723B(struct adapter * Adapter,s32 * powerlevel)728 void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel)
729 {
730 }
731
phy_SetRegBW_8723B(struct adapter * Adapter,enum CHANNEL_WIDTH CurrentBW)732 static void phy_SetRegBW_8723B(
733 struct adapter *Adapter, enum CHANNEL_WIDTH CurrentBW
734 )
735 {
736 u16 RegRfMod_BW, u2tmp = 0;
737 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B);
738
739 switch (CurrentBW) {
740 case CHANNEL_WIDTH_20:
741 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
742 break;
743
744 case CHANNEL_WIDTH_40:
745 u2tmp = RegRfMod_BW | BIT7;
746 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
747 break;
748
749 case CHANNEL_WIDTH_80:
750 u2tmp = RegRfMod_BW | BIT8;
751 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
752 break;
753
754 default:
755 DBG_871X("phy_PostSetBWMode8723B(): unknown Bandwidth: %#X\n", CurrentBW);
756 break;
757 }
758 }
759
phy_GetSecondaryChnl_8723B(struct adapter * Adapter)760 static u8 phy_GetSecondaryChnl_8723B(struct adapter *Adapter)
761 {
762 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
763 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
764
765 RT_TRACE(
766 _module_hal_init_c_,
767 _drv_info_,
768 (
769 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",
770 pHalData->CurrentChannelBW,
771 pHalData->nCur80MhzPrimeSC,
772 pHalData->nCur40MhzPrimeSC
773 )
774 );
775 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
776 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
777 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
778 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
779 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
780 else
781 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
782
783 if (
784 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
785 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
786 )
787 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
788 else if (
789 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
790 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
791 )
792 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
793 else if (
794 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
795 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
796 )
797 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
798 else if (
799 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
800 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
801 )
802 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
803 else
804 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
805 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
806 RT_TRACE(
807 _module_hal_init_c_,
808 _drv_info_,
809 (
810 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n",
811 pHalData->CurrentChannelBW,
812 pHalData->nCur40MhzPrimeSC
813 )
814 );
815
816 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
817 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
818 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
819 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
820 else
821 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
822 }
823
824 RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20)));
825 return (SCSettingOf40 << 4) | SCSettingOf20;
826 }
827
phy_PostSetBwMode8723B(struct adapter * Adapter)828 static void phy_PostSetBwMode8723B(struct adapter *Adapter)
829 {
830 u8 SubChnlNum = 0;
831 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
832
833
834 /* 3 Set Reg668 Reg440 BW */
835 phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
836
837 /* 3 Set Reg483 */
838 SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter);
839 rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum);
840
841 /* 3 */
842 /* 3<2>Set PHY related register */
843 /* 3 */
844 switch (pHalData->CurrentChannelBW) {
845 /* 20 MHz channel*/
846 case CHANNEL_WIDTH_20:
847 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
848
849 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
850
851 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
852
853 PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
854 break;
855
856 /* 40 MHz channel*/
857 case CHANNEL_WIDTH_40:
858 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
859
860 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
861
862 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
863 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
864
865 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
866
867 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */
868
869 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
870
871 break;
872
873 default:
874 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\
875 , pHalData->CurrentChannelBW));*/
876 break;
877 }
878
879 /* 3<3>Set RF related register */
880 PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW);
881 }
882
phy_SwChnl8723B(struct adapter * padapter)883 static void phy_SwChnl8723B(struct adapter *padapter)
884 {
885 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
886 u8 channelToSW = pHalData->CurrentChannel;
887
888 if (pHalData->rf_chip == RF_PSEUDO_11N) {
889 /* RT_TRACE(COMP_MLME, DBG_LOUD, ("phy_SwChnl8723B: return for PSEUDO\n")); */
890 return;
891 }
892 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
893 PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
894 PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
895
896 DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW);
897 }
898
phy_SwChnlAndSetBwMode8723B(struct adapter * Adapter)899 static void phy_SwChnlAndSetBwMode8723B(struct adapter *Adapter)
900 {
901 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
902
903 /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */
904 if (Adapter->bNotifyChannelChange) {
905 DBG_871X("[%s] bSwChnl =%d, ch =%d, bSetChnlBW =%d, bw =%d\n",
906 __func__,
907 pHalData->bSwChnl,
908 pHalData->CurrentChannel,
909 pHalData->bSetChnlBW,
910 pHalData->CurrentChannelBW);
911 }
912
913 if (Adapter->bDriverStopped || Adapter->bSurpriseRemoved)
914 return;
915
916 if (pHalData->bSwChnl) {
917 phy_SwChnl8723B(Adapter);
918 pHalData->bSwChnl = false;
919 }
920
921 if (pHalData->bSetChnlBW) {
922 phy_PostSetBwMode8723B(Adapter);
923 pHalData->bSetChnlBW = false;
924 }
925
926 PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel);
927 }
928
PHY_HandleSwChnlAndSetBW8723B(struct adapter * Adapter,bool bSwitchChannel,bool bSetBandWidth,u8 ChannelNum,enum CHANNEL_WIDTH ChnlWidth,enum EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,enum EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)929 static void PHY_HandleSwChnlAndSetBW8723B(
930 struct adapter *Adapter,
931 bool bSwitchChannel,
932 bool bSetBandWidth,
933 u8 ChannelNum,
934 enum CHANNEL_WIDTH ChnlWidth,
935 enum EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
936 enum EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
937 u8 CenterFrequencyIndex1
938 )
939 {
940 /* static bool bInitialzed = false; */
941 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
942 u8 tmpChannel = pHalData->CurrentChannel;
943 enum CHANNEL_WIDTH tmpBW = pHalData->CurrentChannelBW;
944 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
945 u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
946 u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
947
948 /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */
949
950 /* check is swchnl or setbw */
951 if (!bSwitchChannel && !bSetBandWidth) {
952 DBG_871X("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth\n");
953 return;
954 }
955
956 /* skip change for channel or bandwidth is the same */
957 if (bSwitchChannel) {
958 /* if (pHalData->CurrentChannel != ChannelNum) */
959 {
960 if (HAL_IsLegalChannel(Adapter, ChannelNum))
961 pHalData->bSwChnl = true;
962 }
963 }
964
965 if (bSetBandWidth)
966 pHalData->bSetChnlBW = true;
967
968 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
969 /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */
970 return;
971 }
972
973
974 if (pHalData->bSwChnl) {
975 pHalData->CurrentChannel = ChannelNum;
976 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
977 }
978
979
980 if (pHalData->bSetChnlBW) {
981 pHalData->CurrentChannelBW = ChnlWidth;
982 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
983 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
984 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
985 }
986
987 /* Switch workitem or set timer to do switch channel or setbandwidth operation */
988 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
989 phy_SwChnlAndSetBwMode8723B(Adapter);
990 } else {
991 if (pHalData->bSwChnl) {
992 pHalData->CurrentChannel = tmpChannel;
993 pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
994 }
995
996 if (pHalData->bSetChnlBW) {
997 pHalData->CurrentChannelBW = tmpBW;
998 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
999 pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1000 pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1001 }
1002 }
1003 }
1004
PHY_SetBWMode8723B(struct adapter * Adapter,enum CHANNEL_WIDTH Bandwidth,unsigned char Offset)1005 void PHY_SetBWMode8723B(
1006 struct adapter *Adapter,
1007 enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
1008 unsigned char Offset /* Upper, Lower, or Don't care */
1009 )
1010 {
1011 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1012
1013 PHY_HandleSwChnlAndSetBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel);
1014 }
1015
1016 /* Call after initialization */
PHY_SwChnl8723B(struct adapter * Adapter,u8 channel)1017 void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel)
1018 {
1019 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, false, channel, 0, 0, 0, channel);
1020 }
1021
PHY_SetSwChnlBWMode8723B(struct adapter * Adapter,u8 channel,enum CHANNEL_WIDTH Bandwidth,u8 Offset40,u8 Offset80)1022 void PHY_SetSwChnlBWMode8723B(
1023 struct adapter *Adapter,
1024 u8 channel,
1025 enum CHANNEL_WIDTH Bandwidth,
1026 u8 Offset40,
1027 u8 Offset80
1028 )
1029 {
1030 /* DBG_871X("%s() ===>\n", __func__); */
1031
1032 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Offset40, Offset80, channel);
1033
1034 /* DBG_871X("<==%s()\n", __func__); */
1035 }
1036