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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Wireless Host Controller: Radio Control Interface (WHCI v0.95[2.3])
4  * Radio Control command/event transport to the UWB stack
5  *
6  * Copyright (C) 2005-2006 Intel Corporation
7  * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
8  *
9  * Initialize and hook up the Radio Control interface.
10  *
11  * For each device probed, creates an 'struct whcrc' which contains
12  * just the representation of the UWB Radio Controller, and the logic
13  * for reading notifications and passing them to the UWB Core.
14  *
15  * So we initialize all of those, register the UWB Radio Controller
16  * and setup the notification/event handle to pipe the notifications
17  * to the UWB management Daemon.
18  *
19  * Once uwb_rc_add() is called, the UWB stack takes control, resets
20  * the radio and readies the device to take commands the UWB
21  * API/user-space.
22  *
23  * Note this driver is just a transport driver; the commands are
24  * formed at the UWB stack and given to this driver who will deliver
25  * them to the hw and transfer the replies/notifications back to the
26  * UWB stack through the UWB daemon (UWBD).
27  */
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/interrupt.h>
34 #include <linux/slab.h>
35 #include <linux/workqueue.h>
36 #include "uwb.h"
37 #include "include/whci.h"
38 #include "include/umc.h"
39 
40 #include "uwb-internal.h"
41 
42 /**
43  * Descriptor for an instance of the UWB Radio Control Driver that
44  * attaches to the URC interface of the WHCI PCI card.
45  *
46  * Unless there is a lock specific to the 'data members', all access
47  * is protected by uwb_rc->mutex.
48  */
49 struct whcrc {
50 	struct umc_dev *umc_dev;
51 	struct uwb_rc *uwb_rc;		/* UWB host controller */
52 
53 	unsigned long area;
54 	void __iomem *rc_base;
55 	size_t rc_len;
56 	spinlock_t irq_lock;
57 
58 	void *evt_buf, *cmd_buf;
59 	dma_addr_t evt_dma_buf, cmd_dma_buf;
60 	wait_queue_head_t cmd_wq;
61 	struct work_struct event_work;
62 };
63 
64 /**
65  * Execute an UWB RC command on WHCI/RC
66  *
67  * @rc:       Instance of a Radio Controller that is a whcrc
68  * @cmd:      Buffer containing the RCCB and payload to execute
69  * @cmd_size: Size of the command buffer.
70  *
71  * We copy the command into whcrc->cmd_buf (as it is pretty and
72  * aligned`and physically contiguous) and then press the right keys in
73  * the controller's URCCMD register to get it to read it. We might
74  * have to wait for the cmd_sem to be open to us.
75  *
76  * NOTE: rc's mutex has to be locked
77  */
whcrc_cmd(struct uwb_rc * uwb_rc,const struct uwb_rccb * cmd,size_t cmd_size)78 static int whcrc_cmd(struct uwb_rc *uwb_rc,
79 	      const struct uwb_rccb *cmd, size_t cmd_size)
80 {
81 	int result = 0;
82 	struct whcrc *whcrc = uwb_rc->priv;
83 	struct device *dev = &whcrc->umc_dev->dev;
84 	u32 urccmd;
85 
86 	if (cmd_size >= 4096)
87 		return -EINVAL;
88 
89 	/*
90 	 * If the URC is halted, then the hardware has reset itself.
91 	 * Attempt to recover by restarting the device and then return
92 	 * an error as it's likely that the current command isn't
93 	 * valid for a newly started RC.
94 	 */
95 	if (le_readl(whcrc->rc_base + URCSTS) & URCSTS_HALTED) {
96 		dev_err(dev, "requesting reset of halted radio controller\n");
97 		uwb_rc_reset_all(uwb_rc);
98 		return -EIO;
99 	}
100 
101 	result = wait_event_timeout(whcrc->cmd_wq,
102 		!(le_readl(whcrc->rc_base + URCCMD) & URCCMD_ACTIVE), HZ/2);
103 	if (result == 0) {
104 		dev_err(dev, "device is not ready to execute commands\n");
105 		return -ETIMEDOUT;
106 	}
107 
108 	memmove(whcrc->cmd_buf, cmd, cmd_size);
109 	le_writeq(whcrc->cmd_dma_buf, whcrc->rc_base + URCCMDADDR);
110 
111 	spin_lock(&whcrc->irq_lock);
112 	urccmd = le_readl(whcrc->rc_base + URCCMD);
113 	urccmd &= ~(URCCMD_EARV | URCCMD_SIZE_MASK);
114 	le_writel(urccmd | URCCMD_ACTIVE | URCCMD_IWR | cmd_size,
115 		  whcrc->rc_base + URCCMD);
116 	spin_unlock(&whcrc->irq_lock);
117 
118 	return 0;
119 }
120 
whcrc_reset(struct uwb_rc * rc)121 static int whcrc_reset(struct uwb_rc *rc)
122 {
123 	struct whcrc *whcrc = rc->priv;
124 
125 	return umc_controller_reset(whcrc->umc_dev);
126 }
127 
128 /**
129  * Reset event reception mechanism and tell hw we are ready to get more
130  *
131  * We have read all the events in the event buffer, so we are ready to
132  * reset it to the beginning.
133  *
134  * This is only called during initialization or after an event buffer
135  * has been retired.  This means we can be sure that event processing
136  * is disabled and it's safe to update the URCEVTADDR register.
137  *
138  * There's no need to wait for the event processing to start as the
139  * URC will not clear URCCMD_ACTIVE until (internal) event buffer
140  * space is available.
141  */
142 static
whcrc_enable_events(struct whcrc * whcrc)143 void whcrc_enable_events(struct whcrc *whcrc)
144 {
145 	u32 urccmd;
146 
147 	le_writeq(whcrc->evt_dma_buf, whcrc->rc_base + URCEVTADDR);
148 
149 	spin_lock(&whcrc->irq_lock);
150 	urccmd = le_readl(whcrc->rc_base + URCCMD) & ~URCCMD_ACTIVE;
151 	le_writel(urccmd | URCCMD_EARV, whcrc->rc_base + URCCMD);
152 	spin_unlock(&whcrc->irq_lock);
153 }
154 
whcrc_event_work(struct work_struct * work)155 static void whcrc_event_work(struct work_struct *work)
156 {
157 	struct whcrc *whcrc = container_of(work, struct whcrc, event_work);
158 	size_t size;
159 	u64 urcevtaddr;
160 
161 	urcevtaddr = le_readq(whcrc->rc_base + URCEVTADDR);
162 	size = urcevtaddr & URCEVTADDR_OFFSET_MASK;
163 
164 	uwb_rc_neh_grok(whcrc->uwb_rc, whcrc->evt_buf, size);
165 	whcrc_enable_events(whcrc);
166 }
167 
168 /**
169  * Catch interrupts?
170  *
171  * We ack inmediately (and expect the hw to do the right thing and
172  * raise another IRQ if things have changed :)
173  */
174 static
whcrc_irq_cb(int irq,void * _whcrc)175 irqreturn_t whcrc_irq_cb(int irq, void *_whcrc)
176 {
177 	struct whcrc *whcrc = _whcrc;
178 	struct device *dev = &whcrc->umc_dev->dev;
179 	u32 urcsts;
180 
181 	urcsts = le_readl(whcrc->rc_base + URCSTS);
182 	if (!(urcsts & URCSTS_INT_MASK))
183 		return IRQ_NONE;
184 	le_writel(urcsts & URCSTS_INT_MASK, whcrc->rc_base + URCSTS);
185 
186 	if (urcsts & URCSTS_HSE) {
187 		dev_err(dev, "host system error -- hardware halted\n");
188 		/* FIXME: do something sensible here */
189 		goto out;
190 	}
191 	if (urcsts & URCSTS_ER)
192 		schedule_work(&whcrc->event_work);
193 	if (urcsts & URCSTS_RCI)
194 		wake_up_all(&whcrc->cmd_wq);
195 out:
196 	return IRQ_HANDLED;
197 }
198 
199 
200 /**
201  * Initialize a UMC RC interface: map regions, get (shared) IRQ
202  */
203 static
whcrc_setup_rc_umc(struct whcrc * whcrc)204 int whcrc_setup_rc_umc(struct whcrc *whcrc)
205 {
206 	int result = 0;
207 	struct device *dev = &whcrc->umc_dev->dev;
208 	struct umc_dev *umc_dev = whcrc->umc_dev;
209 
210 	whcrc->area = umc_dev->resource.start;
211 	whcrc->rc_len = resource_size(&umc_dev->resource);
212 	result = -EBUSY;
213 	if (request_mem_region(whcrc->area, whcrc->rc_len, KBUILD_MODNAME) == NULL) {
214 		dev_err(dev, "can't request URC region (%zu bytes @ 0x%lx): %d\n",
215 			whcrc->rc_len, whcrc->area, result);
216 		goto error_request_region;
217 	}
218 
219 	whcrc->rc_base = ioremap_nocache(whcrc->area, whcrc->rc_len);
220 	if (whcrc->rc_base == NULL) {
221 		dev_err(dev, "can't ioremap registers (%zu bytes @ 0x%lx): %d\n",
222 			whcrc->rc_len, whcrc->area, result);
223 		goto error_ioremap_nocache;
224 	}
225 
226 	result = request_irq(umc_dev->irq, whcrc_irq_cb, IRQF_SHARED,
227 			     KBUILD_MODNAME, whcrc);
228 	if (result < 0) {
229 		dev_err(dev, "can't allocate IRQ %d: %d\n",
230 			umc_dev->irq, result);
231 		goto error_request_irq;
232 	}
233 
234 	result = -ENOMEM;
235 	whcrc->cmd_buf = dma_alloc_coherent(&umc_dev->dev, PAGE_SIZE,
236 					    &whcrc->cmd_dma_buf, GFP_KERNEL);
237 	if (whcrc->cmd_buf == NULL) {
238 		dev_err(dev, "Can't allocate cmd transfer buffer\n");
239 		goto error_cmd_buffer;
240 	}
241 
242 	whcrc->evt_buf = dma_alloc_coherent(&umc_dev->dev, PAGE_SIZE,
243 					    &whcrc->evt_dma_buf, GFP_KERNEL);
244 	if (whcrc->evt_buf == NULL) {
245 		dev_err(dev, "Can't allocate evt transfer buffer\n");
246 		goto error_evt_buffer;
247 	}
248 	return 0;
249 
250 error_evt_buffer:
251 	dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->cmd_buf,
252 			  whcrc->cmd_dma_buf);
253 error_cmd_buffer:
254 	free_irq(umc_dev->irq, whcrc);
255 error_request_irq:
256 	iounmap(whcrc->rc_base);
257 error_ioremap_nocache:
258 	release_mem_region(whcrc->area, whcrc->rc_len);
259 error_request_region:
260 	return result;
261 }
262 
263 
264 /**
265  * Release RC's UMC resources
266  */
267 static
whcrc_release_rc_umc(struct whcrc * whcrc)268 void whcrc_release_rc_umc(struct whcrc *whcrc)
269 {
270 	struct umc_dev *umc_dev = whcrc->umc_dev;
271 
272 	dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->evt_buf,
273 			  whcrc->evt_dma_buf);
274 	dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->cmd_buf,
275 			  whcrc->cmd_dma_buf);
276 	free_irq(umc_dev->irq, whcrc);
277 	iounmap(whcrc->rc_base);
278 	release_mem_region(whcrc->area, whcrc->rc_len);
279 }
280 
281 
282 /**
283  * whcrc_start_rc - start a WHCI radio controller
284  * @whcrc: the radio controller to start
285  *
286  * Reset the UMC device, start the radio controller, enable events and
287  * finally enable interrupts.
288  */
whcrc_start_rc(struct uwb_rc * rc)289 static int whcrc_start_rc(struct uwb_rc *rc)
290 {
291 	struct whcrc *whcrc = rc->priv;
292 	struct device *dev = &whcrc->umc_dev->dev;
293 
294 	/* Reset the thing */
295 	le_writel(URCCMD_RESET, whcrc->rc_base + URCCMD);
296 	if (whci_wait_for(dev, whcrc->rc_base + URCCMD, URCCMD_RESET, 0,
297 			  5000, "hardware reset") < 0)
298 		return -EBUSY;
299 
300 	/* Set the event buffer, start the controller (enable IRQs later) */
301 	le_writel(0, whcrc->rc_base + URCINTR);
302 	le_writel(URCCMD_RS, whcrc->rc_base + URCCMD);
303 	if (whci_wait_for(dev, whcrc->rc_base + URCSTS, URCSTS_HALTED, 0,
304 			  5000, "radio controller start") < 0)
305 		return -ETIMEDOUT;
306 	whcrc_enable_events(whcrc);
307 	le_writel(URCINTR_EN_ALL, whcrc->rc_base + URCINTR);
308 	return 0;
309 }
310 
311 
312 /**
313  * whcrc_stop_rc - stop a WHCI radio controller
314  * @whcrc: the radio controller to stop
315  *
316  * Disable interrupts and cancel any pending event processing work
317  * before clearing the Run/Stop bit.
318  */
319 static
whcrc_stop_rc(struct uwb_rc * rc)320 void whcrc_stop_rc(struct uwb_rc *rc)
321 {
322 	struct whcrc *whcrc = rc->priv;
323 	struct umc_dev *umc_dev = whcrc->umc_dev;
324 
325 	le_writel(0, whcrc->rc_base + URCINTR);
326 	cancel_work_sync(&whcrc->event_work);
327 
328 	le_writel(0, whcrc->rc_base + URCCMD);
329 	whci_wait_for(&umc_dev->dev, whcrc->rc_base + URCSTS,
330 		      URCSTS_HALTED, URCSTS_HALTED, 100, "radio controller stop");
331 }
332 
whcrc_init(struct whcrc * whcrc)333 static void whcrc_init(struct whcrc *whcrc)
334 {
335 	spin_lock_init(&whcrc->irq_lock);
336 	init_waitqueue_head(&whcrc->cmd_wq);
337 	INIT_WORK(&whcrc->event_work, whcrc_event_work);
338 }
339 
340 /**
341  * Initialize the radio controller.
342  *
343  * NOTE: we setup whcrc->uwb_rc before calling uwb_rc_add(); in the
344  *       IRQ handler we use that to determine if the hw is ready to
345  *       handle events. Looks like a race condition, but it really is
346  *       not.
347  */
348 static
whcrc_probe(struct umc_dev * umc_dev)349 int whcrc_probe(struct umc_dev *umc_dev)
350 {
351 	int result;
352 	struct uwb_rc *uwb_rc;
353 	struct whcrc *whcrc;
354 	struct device *dev = &umc_dev->dev;
355 
356 	result = -ENOMEM;
357 	uwb_rc = uwb_rc_alloc();
358 	if (uwb_rc == NULL) {
359 		dev_err(dev, "unable to allocate RC instance\n");
360 		goto error_rc_alloc;
361 	}
362 	whcrc = kzalloc(sizeof(*whcrc), GFP_KERNEL);
363 	if (whcrc == NULL) {
364 		dev_err(dev, "unable to allocate WHC-RC instance\n");
365 		goto error_alloc;
366 	}
367 	whcrc_init(whcrc);
368 	whcrc->umc_dev = umc_dev;
369 
370 	result = whcrc_setup_rc_umc(whcrc);
371 	if (result < 0) {
372 		dev_err(dev, "Can't setup RC UMC interface: %d\n", result);
373 		goto error_setup_rc_umc;
374 	}
375 	whcrc->uwb_rc = uwb_rc;
376 
377 	uwb_rc->owner = THIS_MODULE;
378 	uwb_rc->cmd   = whcrc_cmd;
379 	uwb_rc->reset = whcrc_reset;
380 	uwb_rc->start = whcrc_start_rc;
381 	uwb_rc->stop  = whcrc_stop_rc;
382 
383 	result = uwb_rc_add(uwb_rc, dev, whcrc);
384 	if (result < 0)
385 		goto error_rc_add;
386 	umc_set_drvdata(umc_dev, whcrc);
387 	return 0;
388 
389 error_rc_add:
390 	whcrc_release_rc_umc(whcrc);
391 error_setup_rc_umc:
392 	kfree(whcrc);
393 error_alloc:
394 	uwb_rc_put(uwb_rc);
395 error_rc_alloc:
396 	return result;
397 }
398 
399 /**
400  * Clean up the radio control resources
401  *
402  * When we up the command semaphore, everybody possibly held trying to
403  * execute a command should be granted entry and then they'll see the
404  * host is quiescing and up it (so it will chain to the next waiter).
405  * This should not happen (in any case), as we can only remove when
406  * there are no handles open...
407  */
whcrc_remove(struct umc_dev * umc_dev)408 static void whcrc_remove(struct umc_dev *umc_dev)
409 {
410 	struct whcrc *whcrc = umc_get_drvdata(umc_dev);
411 	struct uwb_rc *uwb_rc = whcrc->uwb_rc;
412 
413 	umc_set_drvdata(umc_dev, NULL);
414 	uwb_rc_rm(uwb_rc);
415 	whcrc_release_rc_umc(whcrc);
416 	kfree(whcrc);
417 	uwb_rc_put(uwb_rc);
418 }
419 
whcrc_pre_reset(struct umc_dev * umc)420 static int whcrc_pre_reset(struct umc_dev *umc)
421 {
422 	struct whcrc *whcrc = umc_get_drvdata(umc);
423 	struct uwb_rc *uwb_rc = whcrc->uwb_rc;
424 
425 	uwb_rc_pre_reset(uwb_rc);
426 	return 0;
427 }
428 
whcrc_post_reset(struct umc_dev * umc)429 static int whcrc_post_reset(struct umc_dev *umc)
430 {
431 	struct whcrc *whcrc = umc_get_drvdata(umc);
432 	struct uwb_rc *uwb_rc = whcrc->uwb_rc;
433 
434 	return uwb_rc_post_reset(uwb_rc);
435 }
436 
437 /* PCI device ID's that we handle [so it gets loaded] */
438 static struct pci_device_id __used whcrc_id_table[] = {
439 	{ PCI_DEVICE_CLASS(PCI_CLASS_WIRELESS_WHCI, ~0) },
440 	{ /* empty last entry */ }
441 };
442 MODULE_DEVICE_TABLE(pci, whcrc_id_table);
443 
444 static struct umc_driver whcrc_driver = {
445 	.name       = "whc-rc",
446 	.cap_id     = UMC_CAP_ID_WHCI_RC,
447 	.probe      = whcrc_probe,
448 	.remove     = whcrc_remove,
449 	.pre_reset  = whcrc_pre_reset,
450 	.post_reset = whcrc_post_reset,
451 };
452 
whcrc_driver_init(void)453 static int __init whcrc_driver_init(void)
454 {
455 	return umc_driver_register(&whcrc_driver);
456 }
457 module_init(whcrc_driver_init);
458 
whcrc_driver_exit(void)459 static void __exit whcrc_driver_exit(void)
460 {
461 	umc_driver_unregister(&whcrc_driver);
462 }
463 module_exit(whcrc_driver_exit);
464 
465 MODULE_AUTHOR("Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>");
466 MODULE_DESCRIPTION("Wireless Host Controller Radio Control Driver");
467 MODULE_LICENSE("GPL");
468