1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Copyright (C) 2009 - 2013 NVIDIA Corporation
7 */
8
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/gpio.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/of_gpio.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/usb/ehci_def.h>
24 #include <linux/usb/tegra_usb_phy.h>
25 #include <linux/usb.h>
26 #include <linux/usb/hcd.h>
27 #include <linux/usb/otg.h>
28
29 #include "ehci.h"
30
31 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
32
33 #define TEGRA_USB_DMA_ALIGN 32
34
35 #define DRIVER_DESC "Tegra EHCI driver"
36 #define DRV_NAME "tegra-ehci"
37
38 static struct hc_driver __read_mostly tegra_ehci_hc_driver;
39
40 struct tegra_ehci_soc_config {
41 bool has_hostpc;
42 };
43
44 struct tegra_ehci_hcd {
45 struct tegra_usb_phy *phy;
46 struct clk *clk;
47 struct reset_control *rst;
48 int port_resuming;
49 bool needs_double_reset;
50 enum tegra_usb_phy_port_speed port_speed;
51 };
52
tegra_reset_usb_controller(struct platform_device * pdev)53 static int tegra_reset_usb_controller(struct platform_device *pdev)
54 {
55 struct device_node *phy_np;
56 struct usb_hcd *hcd = platform_get_drvdata(pdev);
57 struct tegra_ehci_hcd *tegra =
58 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
59 struct reset_control *rst;
60 int err;
61
62 phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
63 if (!phy_np)
64 return -ENOENT;
65
66 /*
67 * The 1st USB controller contains some UTMI pad registers that are
68 * global for all the controllers on the chip. Those registers are
69 * also cleared when reset is asserted to the 1st controller.
70 */
71 rst = of_reset_control_get_shared(phy_np, "utmi-pads");
72 if (IS_ERR(rst)) {
73 dev_warn(&pdev->dev,
74 "can't get utmi-pads reset from the PHY\n");
75 dev_warn(&pdev->dev,
76 "continuing, but please update your DT\n");
77 } else {
78 /*
79 * PHY driver performs UTMI-pads reset in a case of
80 * non-legacy DT.
81 */
82 reset_control_put(rst);
83 }
84
85 of_node_put(phy_np);
86
87 /* reset control is shared, hence initialize it first */
88 err = reset_control_deassert(tegra->rst);
89 if (err)
90 return err;
91
92 err = reset_control_assert(tegra->rst);
93 if (err)
94 return err;
95
96 udelay(1);
97
98 err = reset_control_deassert(tegra->rst);
99 if (err)
100 return err;
101
102 return 0;
103 }
104
tegra_ehci_internal_port_reset(struct ehci_hcd * ehci,u32 __iomem * portsc_reg)105 static int tegra_ehci_internal_port_reset(
106 struct ehci_hcd *ehci,
107 u32 __iomem *portsc_reg
108 )
109 {
110 u32 temp;
111 unsigned long flags;
112 int retval = 0;
113 int i, tries;
114 u32 saved_usbintr;
115
116 spin_lock_irqsave(&ehci->lock, flags);
117 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
118 /* disable USB interrupt */
119 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
120 spin_unlock_irqrestore(&ehci->lock, flags);
121
122 /*
123 * Here we have to do Port Reset at most twice for
124 * Port Enable bit to be set.
125 */
126 for (i = 0; i < 2; i++) {
127 temp = ehci_readl(ehci, portsc_reg);
128 temp |= PORT_RESET;
129 ehci_writel(ehci, temp, portsc_reg);
130 mdelay(10);
131 temp &= ~PORT_RESET;
132 ehci_writel(ehci, temp, portsc_reg);
133 mdelay(1);
134 tries = 100;
135 do {
136 mdelay(1);
137 /*
138 * Up to this point, Port Enable bit is
139 * expected to be set after 2 ms waiting.
140 * USB1 usually takes extra 45 ms, for safety,
141 * we take 100 ms as timeout.
142 */
143 temp = ehci_readl(ehci, portsc_reg);
144 } while (!(temp & PORT_PE) && tries--);
145 if (temp & PORT_PE)
146 break;
147 }
148 if (i == 2)
149 retval = -ETIMEDOUT;
150
151 /*
152 * Clear Connect Status Change bit if it's set.
153 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
154 */
155 if (temp & PORT_CSC)
156 ehci_writel(ehci, PORT_CSC, portsc_reg);
157
158 /*
159 * Write to clear any interrupt status bits that might be set
160 * during port reset.
161 */
162 temp = ehci_readl(ehci, &ehci->regs->status);
163 ehci_writel(ehci, temp, &ehci->regs->status);
164
165 /* restore original interrupt enable bits */
166 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
167 return retval;
168 }
169
tegra_ehci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)170 static int tegra_ehci_hub_control(
171 struct usb_hcd *hcd,
172 u16 typeReq,
173 u16 wValue,
174 u16 wIndex,
175 char *buf,
176 u16 wLength
177 )
178 {
179 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
180 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
181 u32 __iomem *status_reg;
182 u32 temp;
183 unsigned long flags;
184 int retval = 0;
185
186 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
187
188 spin_lock_irqsave(&ehci->lock, flags);
189
190 if (typeReq == GetPortStatus) {
191 temp = ehci_readl(ehci, status_reg);
192 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
193 /* Resume completed, re-enable disconnect detection */
194 tegra->port_resuming = 0;
195 tegra_usb_phy_postresume(hcd->usb_phy);
196 }
197 }
198
199 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
200 temp = ehci_readl(ehci, status_reg);
201 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
202 retval = -EPIPE;
203 goto done;
204 }
205
206 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
207 temp |= PORT_WKDISC_E | PORT_WKOC_E;
208 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
209
210 /*
211 * If a transaction is in progress, there may be a delay in
212 * suspending the port. Poll until the port is suspended.
213 */
214 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
215 PORT_SUSPEND, 5000))
216 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
217
218 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
219 goto done;
220 }
221
222 /* For USB1 port we need to issue Port Reset twice internally */
223 if (tegra->needs_double_reset &&
224 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
225 spin_unlock_irqrestore(&ehci->lock, flags);
226 return tegra_ehci_internal_port_reset(ehci, status_reg);
227 }
228
229 /*
230 * Tegra host controller will time the resume operation to clear the bit
231 * when the port control state switches to HS or FS Idle. This behavior
232 * is different from EHCI where the host controller driver is required
233 * to set this bit to a zero after the resume duration is timed in the
234 * driver.
235 */
236 else if (typeReq == ClearPortFeature &&
237 wValue == USB_PORT_FEAT_SUSPEND) {
238 temp = ehci_readl(ehci, status_reg);
239 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
240 retval = -EPIPE;
241 goto done;
242 }
243
244 if (!(temp & PORT_SUSPEND))
245 goto done;
246
247 /* Disable disconnect detection during port resume */
248 tegra_usb_phy_preresume(hcd->usb_phy);
249
250 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
251
252 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
253 /* start resume signalling */
254 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
255 set_bit(wIndex-1, &ehci->resuming_ports);
256
257 spin_unlock_irqrestore(&ehci->lock, flags);
258 msleep(20);
259 spin_lock_irqsave(&ehci->lock, flags);
260
261 /* Poll until the controller clears RESUME and SUSPEND */
262 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
263 pr_err("%s: timeout waiting for RESUME\n", __func__);
264 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
265 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
266
267 ehci->reset_done[wIndex-1] = 0;
268 clear_bit(wIndex-1, &ehci->resuming_ports);
269
270 tegra->port_resuming = 1;
271 goto done;
272 }
273
274 spin_unlock_irqrestore(&ehci->lock, flags);
275
276 /* Handle the hub control events here */
277 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
278
279 done:
280 spin_unlock_irqrestore(&ehci->lock, flags);
281 return retval;
282 }
283
284 struct dma_aligned_buffer {
285 void *kmalloc_ptr;
286 void *old_xfer_buffer;
287 u8 data[0];
288 };
289
free_dma_aligned_buffer(struct urb * urb)290 static void free_dma_aligned_buffer(struct urb *urb)
291 {
292 struct dma_aligned_buffer *temp;
293 size_t length;
294
295 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
296 return;
297
298 temp = container_of(urb->transfer_buffer,
299 struct dma_aligned_buffer, data);
300
301 if (usb_urb_dir_in(urb)) {
302 if (usb_pipeisoc(urb->pipe))
303 length = urb->transfer_buffer_length;
304 else
305 length = urb->actual_length;
306
307 memcpy(temp->old_xfer_buffer, temp->data, length);
308 }
309 urb->transfer_buffer = temp->old_xfer_buffer;
310 kfree(temp->kmalloc_ptr);
311
312 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
313 }
314
alloc_dma_aligned_buffer(struct urb * urb,gfp_t mem_flags)315 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
316 {
317 struct dma_aligned_buffer *temp, *kmalloc_ptr;
318 size_t kmalloc_size;
319
320 if (urb->num_sgs || urb->sg ||
321 urb->transfer_buffer_length == 0 ||
322 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
323 return 0;
324
325 /* Allocate a buffer with enough padding for alignment */
326 kmalloc_size = urb->transfer_buffer_length +
327 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
328
329 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
330 if (!kmalloc_ptr)
331 return -ENOMEM;
332
333 /* Position our struct dma_aligned_buffer such that data is aligned */
334 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
335 temp->kmalloc_ptr = kmalloc_ptr;
336 temp->old_xfer_buffer = urb->transfer_buffer;
337 if (usb_urb_dir_out(urb))
338 memcpy(temp->data, urb->transfer_buffer,
339 urb->transfer_buffer_length);
340 urb->transfer_buffer = temp->data;
341
342 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
343
344 return 0;
345 }
346
tegra_ehci_map_urb_for_dma(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)347 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
348 gfp_t mem_flags)
349 {
350 int ret;
351
352 ret = alloc_dma_aligned_buffer(urb, mem_flags);
353 if (ret)
354 return ret;
355
356 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
357 if (ret)
358 free_dma_aligned_buffer(urb);
359
360 return ret;
361 }
362
tegra_ehci_unmap_urb_for_dma(struct usb_hcd * hcd,struct urb * urb)363 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
364 {
365 usb_hcd_unmap_urb_for_dma(hcd, urb);
366 free_dma_aligned_buffer(urb);
367 }
368
369 static const struct tegra_ehci_soc_config tegra30_soc_config = {
370 .has_hostpc = true,
371 };
372
373 static const struct tegra_ehci_soc_config tegra20_soc_config = {
374 .has_hostpc = false,
375 };
376
377 static const struct of_device_id tegra_ehci_of_match[] = {
378 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
379 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
380 { },
381 };
382
tegra_ehci_probe(struct platform_device * pdev)383 static int tegra_ehci_probe(struct platform_device *pdev)
384 {
385 const struct of_device_id *match;
386 const struct tegra_ehci_soc_config *soc_config;
387 struct resource *res;
388 struct usb_hcd *hcd;
389 struct ehci_hcd *ehci;
390 struct tegra_ehci_hcd *tegra;
391 int err = 0;
392 int irq;
393 struct usb_phy *u_phy;
394
395 match = of_match_device(tegra_ehci_of_match, &pdev->dev);
396 if (!match) {
397 dev_err(&pdev->dev, "Error: No device match found\n");
398 return -ENODEV;
399 }
400 soc_config = match->data;
401
402 /* Right now device-tree probed devices don't get dma_mask set.
403 * Since shared usb code relies on it, set it here for now.
404 * Once we have dma capability bindings this can go away.
405 */
406 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
407 if (err)
408 return err;
409
410 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
411 dev_name(&pdev->dev));
412 if (!hcd) {
413 dev_err(&pdev->dev, "Unable to create HCD\n");
414 return -ENOMEM;
415 }
416 platform_set_drvdata(pdev, hcd);
417 ehci = hcd_to_ehci(hcd);
418 tegra = (struct tegra_ehci_hcd *)ehci->priv;
419
420 hcd->has_tt = 1;
421
422 tegra->clk = devm_clk_get(&pdev->dev, NULL);
423 if (IS_ERR(tegra->clk)) {
424 dev_err(&pdev->dev, "Can't get ehci clock\n");
425 err = PTR_ERR(tegra->clk);
426 goto cleanup_hcd_create;
427 }
428
429 tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
430 if (IS_ERR(tegra->rst)) {
431 dev_err(&pdev->dev, "Can't get ehci reset\n");
432 err = PTR_ERR(tegra->rst);
433 goto cleanup_hcd_create;
434 }
435
436 err = clk_prepare_enable(tegra->clk);
437 if (err)
438 goto cleanup_hcd_create;
439
440 err = tegra_reset_usb_controller(pdev);
441 if (err) {
442 dev_err(&pdev->dev, "Failed to reset controller\n");
443 goto cleanup_clk_en;
444 }
445
446 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
447 if (IS_ERR(u_phy)) {
448 err = -EPROBE_DEFER;
449 goto cleanup_clk_en;
450 }
451 hcd->usb_phy = u_phy;
452 hcd->skip_phy_initialization = 1;
453
454 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
455 "nvidia,needs-double-reset");
456
457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
459 if (IS_ERR(hcd->regs)) {
460 err = PTR_ERR(hcd->regs);
461 goto cleanup_clk_en;
462 }
463 hcd->rsrc_start = res->start;
464 hcd->rsrc_len = resource_size(res);
465
466 ehci->caps = hcd->regs + 0x100;
467 ehci->has_hostpc = soc_config->has_hostpc;
468
469 err = usb_phy_init(hcd->usb_phy);
470 if (err) {
471 dev_err(&pdev->dev, "Failed to initialize phy\n");
472 goto cleanup_clk_en;
473 }
474
475 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
476 GFP_KERNEL);
477 if (!u_phy->otg) {
478 err = -ENOMEM;
479 goto cleanup_phy;
480 }
481 u_phy->otg->host = hcd_to_bus(hcd);
482
483 err = usb_phy_set_suspend(hcd->usb_phy, 0);
484 if (err) {
485 dev_err(&pdev->dev, "Failed to power on the phy\n");
486 goto cleanup_phy;
487 }
488
489 irq = platform_get_irq(pdev, 0);
490 if (!irq) {
491 dev_err(&pdev->dev, "Failed to get IRQ\n");
492 err = -ENODEV;
493 goto cleanup_phy;
494 }
495
496 otg_set_host(u_phy->otg, &hcd->self);
497
498 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
499 if (err) {
500 dev_err(&pdev->dev, "Failed to add USB HCD\n");
501 goto cleanup_otg_set_host;
502 }
503 device_wakeup_enable(hcd->self.controller);
504
505 return err;
506
507 cleanup_otg_set_host:
508 otg_set_host(u_phy->otg, NULL);
509 cleanup_phy:
510 usb_phy_shutdown(hcd->usb_phy);
511 cleanup_clk_en:
512 clk_disable_unprepare(tegra->clk);
513 cleanup_hcd_create:
514 usb_put_hcd(hcd);
515 return err;
516 }
517
tegra_ehci_remove(struct platform_device * pdev)518 static int tegra_ehci_remove(struct platform_device *pdev)
519 {
520 struct usb_hcd *hcd = platform_get_drvdata(pdev);
521 struct tegra_ehci_hcd *tegra =
522 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
523
524 otg_set_host(hcd->usb_phy->otg, NULL);
525
526 usb_phy_shutdown(hcd->usb_phy);
527 usb_remove_hcd(hcd);
528
529 reset_control_assert(tegra->rst);
530 udelay(1);
531
532 clk_disable_unprepare(tegra->clk);
533
534 usb_put_hcd(hcd);
535
536 return 0;
537 }
538
tegra_ehci_hcd_shutdown(struct platform_device * pdev)539 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
540 {
541 struct usb_hcd *hcd = platform_get_drvdata(pdev);
542
543 if (hcd->driver->shutdown)
544 hcd->driver->shutdown(hcd);
545 }
546
547 static struct platform_driver tegra_ehci_driver = {
548 .probe = tegra_ehci_probe,
549 .remove = tegra_ehci_remove,
550 .shutdown = tegra_ehci_hcd_shutdown,
551 .driver = {
552 .name = DRV_NAME,
553 .of_match_table = tegra_ehci_of_match,
554 }
555 };
556
tegra_ehci_reset(struct usb_hcd * hcd)557 static int tegra_ehci_reset(struct usb_hcd *hcd)
558 {
559 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
560 int retval;
561 int txfifothresh;
562
563 retval = ehci_setup(hcd);
564 if (retval)
565 return retval;
566
567 /*
568 * We should really pull this value out of tegra_ehci_soc_config, but
569 * to avoid needing access to it, make use of the fact that Tegra20 is
570 * the only one so far that needs a value of 10, and Tegra20 is the
571 * only one which doesn't set has_hostpc.
572 */
573 txfifothresh = ehci->has_hostpc ? 0x10 : 10;
574 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
575
576 return 0;
577 }
578
579 static const struct ehci_driver_overrides tegra_overrides __initconst = {
580 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
581 .reset = tegra_ehci_reset,
582 };
583
ehci_tegra_init(void)584 static int __init ehci_tegra_init(void)
585 {
586 if (usb_disabled())
587 return -ENODEV;
588
589 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
590
591 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
592
593 /*
594 * The Tegra HW has some unusual quirks, which require Tegra-specific
595 * workarounds. We override certain hc_driver functions here to
596 * achieve that. We explicitly do not enhance ehci_driver_overrides to
597 * allow this more easily, since this is an unusual case, and we don't
598 * want to encourage others to override these functions by making it
599 * too easy.
600 */
601
602 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
603 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
604 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
605
606 return platform_driver_register(&tegra_ehci_driver);
607 }
608 module_init(ehci_tegra_init);
609
ehci_tegra_cleanup(void)610 static void __exit ehci_tegra_cleanup(void)
611 {
612 platform_driver_unregister(&tegra_ehci_driver);
613 }
614 module_exit(ehci_tegra_cleanup);
615
616 MODULE_DESCRIPTION(DRIVER_DESC);
617 MODULE_LICENSE("GPL");
618 MODULE_ALIAS("platform:" DRV_NAME);
619 MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
620