1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15
16 #include "xhci.h"
17 #include "xhci-trace.h"
18 #include "xhci-pci.h"
19
20 #define SSIC_PORT_NUM 2
21 #define SSIC_PORT_CFG2 0x880c
22 #define SSIC_PORT_CFG2_OFFSET 0x30
23 #define PROG_DONE (1 << 30)
24 #define SSIC_PORT_UNUSED (1 << 31)
25
26 /* Device for a quirk */
27 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
28 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
31
32 #define PCI_VENDOR_ID_ETRON 0x1b6f
33 #define PCI_DEVICE_ID_EJ168 0x7023
34
35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
36 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
37 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
38 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
40 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
41 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
42 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
43 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
44 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
51 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
52 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
53
54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
58 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
59
60 static const char hcd_name[] = "xhci_hcd";
61
62 static struct hc_driver __read_mostly xhci_pci_hc_driver;
63
64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
65 .reset = xhci_pci_setup,
66 };
67
68 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)69 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
70 {
71 /*
72 * TODO: Implement finding debug ports later.
73 * TODO: see if there are any quirks that need to be added to handle
74 * new extended capabilities.
75 */
76
77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
78 if (!pci_set_mwi(pdev))
79 xhci_dbg(xhci, "MWI active\n");
80
81 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
82 return 0;
83 }
84
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)85 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
86 {
87 struct pci_dev *pdev = to_pci_dev(dev);
88
89 /* Look for vendor-specific quirks */
90 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
91 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
92 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x0) {
95 xhci->quirks |= XHCI_RESET_EP_QUIRK;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC needs configure"
98 " endpoint cmd after reset endpoint");
99 }
100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
101 pdev->revision == 0x4) {
102 xhci->quirks |= XHCI_SLOW_SUSPEND;
103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
104 "QUIRK: Fresco Logic xHC revision %u"
105 "must be suspended extra slowly",
106 pdev->revision);
107 }
108 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
109 xhci->quirks |= XHCI_BROKEN_STREAMS;
110 /* Fresco Logic confirms: all revisions of this chip do not
111 * support MSI, even though some of them claim to in their PCI
112 * capabilities.
113 */
114 xhci->quirks |= XHCI_BROKEN_MSI;
115 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
116 "QUIRK: Fresco Logic revision %u "
117 "has broken MSI implementation",
118 pdev->revision);
119 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
120 }
121
122 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
123 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
124 xhci->quirks |= XHCI_BROKEN_STREAMS;
125
126 if (pdev->vendor == PCI_VENDOR_ID_NEC)
127 xhci->quirks |= XHCI_NEC_HOST;
128
129 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
130 xhci->quirks |= XHCI_AMD_0x96_HOST;
131
132 /* AMD PLL quirk */
133 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
134 xhci->quirks |= XHCI_AMD_PLL_FIX;
135
136 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
137 (pdev->device == 0x15e0 ||
138 pdev->device == 0x15e1 ||
139 pdev->device == 0x43bb))
140 xhci->quirks |= XHCI_SUSPEND_DELAY;
141
142 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
143 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
144 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
145
146 if (pdev->vendor == PCI_VENDOR_ID_AMD)
147 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
148
149 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
150 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
151 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
152 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
153 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
154 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
155
156 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
157 xhci->quirks |= XHCI_LPM_SUPPORT;
158 xhci->quirks |= XHCI_INTEL_HOST;
159 xhci->quirks |= XHCI_AVOID_BEI;
160 }
161 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
162 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
163 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
164 xhci->limit_active_eps = 64;
165 xhci->quirks |= XHCI_SW_BW_CHECKING;
166 /*
167 * PPT desktop boards DH77EB and DH77DF will power back on after
168 * a few seconds of being shutdown. The fix for this is to
169 * switch the ports from xHCI to EHCI on shutdown. We can't use
170 * DMI information to find those particular boards (since each
171 * vendor will change the board name), so we have to key off all
172 * PPT chipsets.
173 */
174 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
175 }
176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
178 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
179 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
180 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
181 }
182 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
183 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
184 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
185 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
186 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
187 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
188 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
189 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
190 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
191 }
192 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
193 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
194 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
195 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
196 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
197 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
198 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
199 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
200 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
201 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
202 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
203 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
204 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
205 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
206 xhci->quirks |= XHCI_MISSING_CAS;
207
208 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
209 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
210 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
211 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
212 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
213 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
214 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
215 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
216 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI))
217 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
218
219 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
220 pdev->device == PCI_DEVICE_ID_EJ168) {
221 xhci->quirks |= XHCI_RESET_ON_RESUME;
222 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
223 xhci->quirks |= XHCI_BROKEN_STREAMS;
224 }
225 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
226 pdev->device == 0x0014) {
227 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
228 xhci->quirks |= XHCI_ZERO_64B_REGS;
229 }
230 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
231 pdev->device == 0x0015) {
232 xhci->quirks |= XHCI_RESET_ON_RESUME;
233 xhci->quirks |= XHCI_ZERO_64B_REGS;
234 }
235 if (pdev->vendor == PCI_VENDOR_ID_VIA)
236 xhci->quirks |= XHCI_RESET_ON_RESUME;
237
238 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
239 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
240 pdev->device == 0x3432)
241 xhci->quirks |= XHCI_BROKEN_STREAMS;
242
243 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
244 pdev->device == 0x1042)
245 xhci->quirks |= XHCI_BROKEN_STREAMS;
246 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
247 pdev->device == 0x1142)
248 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
249
250 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
251 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
252 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
253
254 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
255 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
256
257 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
258 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
259 pdev->device == 0x9026)
260 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
261
262 if (xhci->quirks & XHCI_RESET_ON_RESUME)
263 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
264 "QUIRK: Resetting on resume");
265 }
266
267 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)268 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
269 {
270 static const guid_t intel_dsm_guid =
271 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
272 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
273 union acpi_object *obj;
274
275 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
276 NULL);
277 ACPI_FREE(obj);
278 }
279 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)280 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
281 #endif /* CONFIG_ACPI */
282
283 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)284 int xhci_pci_setup(struct usb_hcd *hcd)
285 {
286 struct xhci_hcd *xhci;
287 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
288 int retval;
289
290 xhci = hcd_to_xhci(hcd);
291 if (!xhci->sbrn)
292 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
293
294 /* imod_interval is the interrupt moderation value in nanoseconds. */
295 xhci->imod_interval = 40000;
296
297 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
298 if (retval)
299 return retval;
300
301 if (!usb_hcd_is_primary_hcd(hcd))
302 return 0;
303
304 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
305
306 /* Find any debug ports */
307 return xhci_pci_reinit(xhci, pdev);
308 }
309 EXPORT_SYMBOL_GPL(xhci_pci_setup);
310
311 /*
312 * We need to register our own PCI probe function (instead of the USB core's
313 * function) in order to create a second roothub under xHCI.
314 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)315 int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
316 {
317 int retval;
318 struct xhci_hcd *xhci;
319 struct hc_driver *driver;
320 struct usb_hcd *hcd;
321
322 driver = (struct hc_driver *)id->driver_data;
323
324 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
325 pm_runtime_get_noresume(&dev->dev);
326
327 /* Register the USB 2.0 roothub.
328 * FIXME: USB core must know to register the USB 2.0 roothub first.
329 * This is sort of silly, because we could just set the HCD driver flags
330 * to say USB 2.0, but I'm not sure what the implications would be in
331 * the other parts of the HCD code.
332 */
333 retval = usb_hcd_pci_probe(dev, id);
334
335 if (retval)
336 goto put_runtime_pm;
337
338 /* USB 2.0 roothub is stored in the PCI device now. */
339 hcd = dev_get_drvdata(&dev->dev);
340 xhci = hcd_to_xhci(hcd);
341 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
342 pci_name(dev), hcd);
343 if (!xhci->shared_hcd) {
344 retval = -ENOMEM;
345 goto dealloc_usb2_hcd;
346 }
347
348 retval = xhci_ext_cap_init(xhci);
349 if (retval)
350 goto put_usb3_hcd;
351
352 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
353 IRQF_SHARED);
354 if (retval)
355 goto put_usb3_hcd;
356 /* Roothub already marked as USB 3.0 speed */
357
358 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
359 HCC_MAX_PSA(xhci->hcc_params) >= 4)
360 xhci->shared_hcd->can_do_streams = 1;
361
362 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
363 xhci_pme_acpi_rtd3_enable(dev);
364
365 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
366 pm_runtime_put_noidle(&dev->dev);
367
368 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
369 pm_runtime_allow(&dev->dev);
370
371 return 0;
372
373 put_usb3_hcd:
374 usb_put_hcd(xhci->shared_hcd);
375 dealloc_usb2_hcd:
376 usb_hcd_pci_remove(dev);
377 put_runtime_pm:
378 pm_runtime_put_noidle(&dev->dev);
379 return retval;
380 }
381 EXPORT_SYMBOL_GPL(xhci_pci_probe);
382
xhci_pci_remove(struct pci_dev * dev)383 void xhci_pci_remove(struct pci_dev *dev)
384 {
385 struct xhci_hcd *xhci;
386
387 xhci = hcd_to_xhci(pci_get_drvdata(dev));
388 xhci->xhc_state |= XHCI_STATE_REMOVING;
389
390 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
391 pm_runtime_forbid(&dev->dev);
392
393 if (xhci->shared_hcd) {
394 usb_remove_hcd(xhci->shared_hcd);
395 usb_put_hcd(xhci->shared_hcd);
396 xhci->shared_hcd = NULL;
397 }
398
399 /* Workaround for spurious wakeups at shutdown with HSW */
400 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
401 pci_set_power_state(dev, PCI_D3hot);
402
403 usb_hcd_pci_remove(dev);
404 }
405 EXPORT_SYMBOL_GPL(xhci_pci_remove);
406
407 #ifdef CONFIG_PM
408 /*
409 * In some Intel xHCI controllers, in order to get D3 working,
410 * through a vendor specific SSIC CONFIG register at offset 0x883c,
411 * SSIC PORT need to be marked as "unused" before putting xHCI
412 * into D3. After D3 exit, the SSIC port need to be marked as "used".
413 * Without this change, xHCI might not enter D3 state.
414 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)415 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
416 {
417 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
418 u32 val;
419 void __iomem *reg;
420 int i;
421
422 for (i = 0; i < SSIC_PORT_NUM; i++) {
423 reg = (void __iomem *) xhci->cap_regs +
424 SSIC_PORT_CFG2 +
425 i * SSIC_PORT_CFG2_OFFSET;
426
427 /* Notify SSIC that SSIC profile programming is not done. */
428 val = readl(reg) & ~PROG_DONE;
429 writel(val, reg);
430
431 /* Mark SSIC port as unused(suspend) or used(resume) */
432 val = readl(reg);
433 if (suspend)
434 val |= SSIC_PORT_UNUSED;
435 else
436 val &= ~SSIC_PORT_UNUSED;
437 writel(val, reg);
438
439 /* Notify SSIC that SSIC profile programming is done */
440 val = readl(reg) | PROG_DONE;
441 writel(val, reg);
442 readl(reg);
443 }
444 }
445
446 /*
447 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
448 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
449 */
xhci_pme_quirk(struct usb_hcd * hcd)450 static void xhci_pme_quirk(struct usb_hcd *hcd)
451 {
452 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
453 void __iomem *reg;
454 u32 val;
455
456 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
457 val = readl(reg);
458 writel(val | BIT(28), reg);
459 readl(reg);
460 }
461
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)462 int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
463 {
464 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
465 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
466 int ret;
467
468 /*
469 * Systems with the TI redriver that loses port status change events
470 * need to have the registers polled during D3, so avoid D3cold.
471 */
472 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
473 pci_d3cold_disable(pdev);
474
475 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
476 xhci_pme_quirk(hcd);
477
478 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
479 xhci_ssic_port_unused_quirk(hcd, true);
480
481 ret = xhci_suspend(xhci, do_wakeup);
482 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
483 xhci_ssic_port_unused_quirk(hcd, false);
484
485 return ret;
486 }
487 EXPORT_SYMBOL_GPL(xhci_pci_suspend);
488
xhci_pci_resume(struct usb_hcd * hcd,bool hibernated)489 int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
490 {
491 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
492 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
493 int retval = 0;
494
495 /* The BIOS on systems with the Intel Panther Point chipset may or may
496 * not support xHCI natively. That means that during system resume, it
497 * may switch the ports back to EHCI so that users can use their
498 * keyboard to select a kernel from GRUB after resume from hibernate.
499 *
500 * The BIOS is supposed to remember whether the OS had xHCI ports
501 * enabled before resume, and switch the ports back to xHCI when the
502 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
503 * writers.
504 *
505 * Unconditionally switch the ports back to xHCI after a system resume.
506 * It should not matter whether the EHCI or xHCI controller is
507 * resumed first. It's enough to do the switchover in xHCI because
508 * USB core won't notice anything as the hub driver doesn't start
509 * running again until after all the devices (including both EHCI and
510 * xHCI host controllers) have been resumed.
511 */
512
513 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
514 usb_enable_intel_xhci_ports(pdev);
515
516 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
517 xhci_ssic_port_unused_quirk(hcd, false);
518
519 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
520 xhci_pme_quirk(hcd);
521
522 retval = xhci_resume(xhci, hibernated);
523 return retval;
524 }
525
xhci_pci_shutdown(struct usb_hcd * hcd)526 static void xhci_pci_shutdown(struct usb_hcd *hcd)
527 {
528 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
529 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
530
531 xhci_shutdown(hcd);
532
533 /* Yet another workaround for spurious wakeups at shutdown with HSW */
534 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
535 pci_set_power_state(pdev, PCI_D3hot);
536 }
537 EXPORT_SYMBOL_GPL(xhci_pci_resume);
538 #endif /* CONFIG_PM */
539
540 /*-------------------------------------------------------------------------*/
541
542 /* PCI driver selection metadata; PCI hotplugging uses this */
543 static const struct pci_device_id pci_ids[] = { {
544 /* handle any USB 3.0 xHCI controller */
545 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
546 .driver_data = (unsigned long) &xhci_pci_hc_driver,
547 },
548 { /* end: all zeroes */ }
549 };
550 MODULE_DEVICE_TABLE(pci, pci_ids);
551
552 /* pci driver glue; this is a "new style" PCI driver module */
553 static struct pci_driver xhci_pci_driver = {
554 .name = (char *) hcd_name,
555 .id_table = pci_ids,
556
557 .probe = xhci_pci_probe,
558 .remove = xhci_pci_remove,
559 /* suspend and resume implemented later */
560
561 .shutdown = usb_hcd_pci_shutdown,
562 #ifdef CONFIG_PM
563 .driver = {
564 .pm = &usb_hcd_pci_pm_ops
565 },
566 #endif
567 };
568
xhci_pci_init(void)569 static int __init xhci_pci_init(void)
570 {
571 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
572 #ifdef CONFIG_PM
573 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
574 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
575 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
576 #endif
577 return pci_register_driver(&xhci_pci_driver);
578 }
579 module_init(xhci_pci_init);
580
xhci_pci_exit(void)581 static void __exit xhci_pci_exit(void)
582 {
583 pci_unregister_driver(&xhci_pci_driver);
584 }
585 module_exit(xhci_pci_exit);
586
587 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
588 MODULE_LICENSE("GPL");
589