1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
4 * http://www.picochip.com
5 *
6 * This file implements a driver for the Synopsys DesignWare watchdog device
7 * in the many subsystems. The watchdog has 16 different timeout periods
8 * and these are a function of the input clock frequency.
9 *
10 * The DesignWare watchdog cannot be stopped once it has been started so we
11 * do not implement a stop function. The watchdog core will continue to send
12 * heartbeat requests after the watchdog device has been closed.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/of.h>
24 #include <linux/pm.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/watchdog.h>
28
29 #define WDOG_CONTROL_REG_OFFSET 0x00
30 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
31 #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
32 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
33 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
34 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
35 #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
36 #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
37
38 /* The maximum TOP (timeout period) value that can be set in the watchdog. */
39 #define DW_WDT_MAX_TOP 15
40
41 #define DW_WDT_DEFAULT_SECONDS 30
42
43 static bool nowayout = WATCHDOG_NOWAYOUT;
44 module_param(nowayout, bool, 0);
45 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
46 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
47
48 struct dw_wdt {
49 void __iomem *regs;
50 struct clk *clk;
51 unsigned long rate;
52 struct watchdog_device wdd;
53 struct reset_control *rst;
54 /* Save/restore */
55 u32 control;
56 u32 timeout;
57 };
58
59 #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
60
dw_wdt_is_enabled(struct dw_wdt * dw_wdt)61 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
62 {
63 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
64 WDOG_CONTROL_REG_WDT_EN_MASK;
65 }
66
dw_wdt_top_in_seconds(struct dw_wdt * dw_wdt,unsigned top)67 static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
68 {
69 /*
70 * There are 16 possible timeout values in 0..15 where the number of
71 * cycles is 2 ^ (16 + i) and the watchdog counts down.
72 */
73 return (1U << (16 + top)) / dw_wdt->rate;
74 }
75
dw_wdt_get_top(struct dw_wdt * dw_wdt)76 static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
77 {
78 int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
79
80 return dw_wdt_top_in_seconds(dw_wdt, top);
81 }
82
dw_wdt_ping(struct watchdog_device * wdd)83 static int dw_wdt_ping(struct watchdog_device *wdd)
84 {
85 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
86
87 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
88 WDOG_COUNTER_RESTART_REG_OFFSET);
89
90 return 0;
91 }
92
dw_wdt_set_timeout(struct watchdog_device * wdd,unsigned int top_s)93 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
94 {
95 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
96 int i, top_val = DW_WDT_MAX_TOP;
97
98 /*
99 * Iterate over the timeout values until we find the closest match. We
100 * always look for >=.
101 */
102 for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
103 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
104 top_val = i;
105 break;
106 }
107
108 /*
109 * Set the new value in the watchdog. Some versions of dw_wdt
110 * have have TOPINIT in the TIMEOUT_RANGE register (as per
111 * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
112 * effectively get a pat of the watchdog right here.
113 */
114 writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
115 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
116
117 wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
118
119 return 0;
120 }
121
dw_wdt_arm_system_reset(struct dw_wdt * dw_wdt)122 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
123 {
124 u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
125
126 /* Disable interrupt mode; always perform system reset. */
127 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
128 /* Enable watchdog. */
129 val |= WDOG_CONTROL_REG_WDT_EN_MASK;
130 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
131 }
132
dw_wdt_start(struct watchdog_device * wdd)133 static int dw_wdt_start(struct watchdog_device *wdd)
134 {
135 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
136
137 dw_wdt_set_timeout(wdd, wdd->timeout);
138 dw_wdt_arm_system_reset(dw_wdt);
139
140 return 0;
141 }
142
dw_wdt_stop(struct watchdog_device * wdd)143 static int dw_wdt_stop(struct watchdog_device *wdd)
144 {
145 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
146
147 if (!dw_wdt->rst) {
148 set_bit(WDOG_HW_RUNNING, &wdd->status);
149 return 0;
150 }
151
152 reset_control_assert(dw_wdt->rst);
153 reset_control_deassert(dw_wdt->rst);
154
155 return 0;
156 }
157
dw_wdt_restart(struct watchdog_device * wdd,unsigned long action,void * data)158 static int dw_wdt_restart(struct watchdog_device *wdd,
159 unsigned long action, void *data)
160 {
161 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
162
163 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
164 if (dw_wdt_is_enabled(dw_wdt))
165 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
166 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
167 else
168 dw_wdt_arm_system_reset(dw_wdt);
169
170 /* wait for reset to assert... */
171 mdelay(500);
172
173 return 0;
174 }
175
dw_wdt_get_timeleft(struct watchdog_device * wdd)176 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
177 {
178 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
179
180 return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
181 dw_wdt->rate;
182 }
183
184 static const struct watchdog_info dw_wdt_ident = {
185 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
186 WDIOF_MAGICCLOSE,
187 .identity = "Synopsys DesignWare Watchdog",
188 };
189
190 static const struct watchdog_ops dw_wdt_ops = {
191 .owner = THIS_MODULE,
192 .start = dw_wdt_start,
193 .stop = dw_wdt_stop,
194 .ping = dw_wdt_ping,
195 .set_timeout = dw_wdt_set_timeout,
196 .get_timeleft = dw_wdt_get_timeleft,
197 .restart = dw_wdt_restart,
198 };
199
200 #ifdef CONFIG_PM_SLEEP
dw_wdt_suspend(struct device * dev)201 static int dw_wdt_suspend(struct device *dev)
202 {
203 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
204
205 dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
206 dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
207
208 clk_disable_unprepare(dw_wdt->clk);
209
210 return 0;
211 }
212
dw_wdt_resume(struct device * dev)213 static int dw_wdt_resume(struct device *dev)
214 {
215 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
216 int err = clk_prepare_enable(dw_wdt->clk);
217
218 if (err)
219 return err;
220
221 writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
222 writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
223
224 dw_wdt_ping(&dw_wdt->wdd);
225
226 return 0;
227 }
228 #endif /* CONFIG_PM_SLEEP */
229
230 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
231
dw_wdt_drv_probe(struct platform_device * pdev)232 static int dw_wdt_drv_probe(struct platform_device *pdev)
233 {
234 struct device *dev = &pdev->dev;
235 struct watchdog_device *wdd;
236 struct dw_wdt *dw_wdt;
237 int ret;
238
239 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
240 if (!dw_wdt)
241 return -ENOMEM;
242
243 dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
244 if (IS_ERR(dw_wdt->regs))
245 return PTR_ERR(dw_wdt->regs);
246
247 dw_wdt->clk = devm_clk_get(dev, NULL);
248 if (IS_ERR(dw_wdt->clk))
249 return PTR_ERR(dw_wdt->clk);
250
251 ret = clk_prepare_enable(dw_wdt->clk);
252 if (ret)
253 return ret;
254
255 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
256 if (dw_wdt->rate == 0) {
257 ret = -EINVAL;
258 goto out_disable_clk;
259 }
260
261 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
262 if (IS_ERR(dw_wdt->rst)) {
263 ret = PTR_ERR(dw_wdt->rst);
264 goto out_disable_clk;
265 }
266
267 reset_control_deassert(dw_wdt->rst);
268
269 wdd = &dw_wdt->wdd;
270 wdd->info = &dw_wdt_ident;
271 wdd->ops = &dw_wdt_ops;
272 wdd->min_timeout = 1;
273 wdd->max_hw_heartbeat_ms =
274 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
275 wdd->parent = dev;
276
277 watchdog_set_drvdata(wdd, dw_wdt);
278 watchdog_set_nowayout(wdd, nowayout);
279 watchdog_init_timeout(wdd, 0, dev);
280
281 /*
282 * If the watchdog is already running, use its already configured
283 * timeout. Otherwise use the default or the value provided through
284 * devicetree.
285 */
286 if (dw_wdt_is_enabled(dw_wdt)) {
287 wdd->timeout = dw_wdt_get_top(dw_wdt);
288 set_bit(WDOG_HW_RUNNING, &wdd->status);
289 } else {
290 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
291 watchdog_init_timeout(wdd, 0, dev);
292 }
293
294 platform_set_drvdata(pdev, dw_wdt);
295
296 watchdog_set_restart_priority(wdd, 128);
297
298 ret = watchdog_register_device(wdd);
299 if (ret)
300 goto out_disable_clk;
301
302 return 0;
303
304 out_disable_clk:
305 clk_disable_unprepare(dw_wdt->clk);
306 return ret;
307 }
308
dw_wdt_drv_remove(struct platform_device * pdev)309 static int dw_wdt_drv_remove(struct platform_device *pdev)
310 {
311 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
312
313 watchdog_unregister_device(&dw_wdt->wdd);
314 reset_control_assert(dw_wdt->rst);
315 clk_disable_unprepare(dw_wdt->clk);
316
317 return 0;
318 }
319
320 #ifdef CONFIG_OF
321 static const struct of_device_id dw_wdt_of_match[] = {
322 { .compatible = "snps,dw-wdt", },
323 { /* sentinel */ }
324 };
325 MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
326 #endif
327
328 static struct platform_driver dw_wdt_driver = {
329 .probe = dw_wdt_drv_probe,
330 .remove = dw_wdt_drv_remove,
331 .driver = {
332 .name = "dw_wdt",
333 .of_match_table = of_match_ptr(dw_wdt_of_match),
334 .pm = &dw_wdt_pm_ops,
335 },
336 };
337
338 module_platform_driver(dw_wdt_driver);
339
340 MODULE_AUTHOR("Jamie Iles");
341 MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
342 MODULE_LICENSE("GPL");
343