1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
36
37 struct clk;
38 struct clk_hw;
39 struct clk_core;
40 struct dentry;
41
42 /**
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
45 *
46 * @rate: Requested clock rate. This field will be adjusted by
47 * clock drivers according to hardware capabilities.
48 * @min_rate: Minimum rate imposed by clk users.
49 * @max_rate: Maximum rate imposed by clk users.
50 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * requested constraints.
52 * @best_parent_hw: The most appropriate parent clock that fulfills the
53 * requested constraints.
54 *
55 */
56 struct clk_rate_request {
57 unsigned long rate;
58 unsigned long min_rate;
59 unsigned long max_rate;
60 unsigned long best_parent_rate;
61 struct clk_hw *best_parent_hw;
62 };
63
64 /**
65 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
66 *
67 * @num: Numerator of the duty cycle ratio
68 * @den: Denominator of the duty cycle ratio
69 */
70 struct clk_duty {
71 unsigned int num;
72 unsigned int den;
73 };
74
75 /**
76 * struct clk_ops - Callback operations for hardware clocks; these are to
77 * be provided by the clock implementation, and will be called by drivers
78 * through the clk_* api.
79 *
80 * @prepare: Prepare the clock for enabling. This must not return until
81 * the clock is fully prepared, and it's safe to call clk_enable.
82 * This callback is intended to allow clock implementations to
83 * do any initialisation that may sleep. Called with
84 * prepare_lock held.
85 *
86 * @unprepare: Release the clock from its prepared state. This will typically
87 * undo any work done in the @prepare callback. Called with
88 * prepare_lock held.
89 *
90 * @is_prepared: Queries the hardware to determine if the clock is prepared.
91 * This function is allowed to sleep. Optional, if this op is not
92 * set then the prepare count will be used.
93 *
94 * @unprepare_unused: Unprepare the clock atomically. Only called from
95 * clk_disable_unused for prepare clocks with special needs.
96 * Called with prepare mutex held. This function may sleep.
97 *
98 * @enable: Enable the clock atomically. This must not return until the
99 * clock is generating a valid clock signal, usable by consumer
100 * devices. Called with enable_lock held. This function must not
101 * sleep.
102 *
103 * @disable: Disable the clock atomically. Called with enable_lock held.
104 * This function must not sleep.
105 *
106 * @is_enabled: Queries the hardware to determine if the clock is enabled.
107 * This function must not sleep. Optional, if this op is not
108 * set then the enable count will be used.
109 *
110 * @disable_unused: Disable the clock atomically. Only called from
111 * clk_disable_unused for gate clocks with special needs.
112 * Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @save_context: Save the context of the clock in prepration for poweroff.
116 *
117 * @restore_context: Restore the context of the clock after a restoration
118 * of power.
119 *
120 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
121 * parent rate is an input parameter. It is up to the caller to
122 * ensure that the prepare_mutex is held across this call.
123 * Returns the calculated rate. Optional, but recommended - if
124 * this op is not set then clock rate will be initialized to 0.
125 *
126 * @round_rate: Given a target rate as input, returns the closest rate actually
127 * supported by the clock. The parent rate is an input/output
128 * parameter.
129 *
130 * @determine_rate: Given a target rate as input, returns the closest rate
131 * actually supported by the clock, and optionally the parent clock
132 * that should be used to provide the clock rate.
133 *
134 * @set_parent: Change the input source of this clock; for clocks with multiple
135 * possible parents specify a new parent by passing in the index
136 * as a u8 corresponding to the parent in either the .parent_names
137 * or .parents arrays. This function in affect translates an
138 * array index into the value programmed into the hardware.
139 * Returns 0 on success, -EERROR otherwise.
140 *
141 * @get_parent: Queries the hardware to determine the parent of a clock. The
142 * return value is a u8 which specifies the index corresponding to
143 * the parent clock. This index can be applied to either the
144 * .parent_names or .parents arrays. In short, this function
145 * translates the parent value read from hardware into an array
146 * index. Currently only called when the clock is initialized by
147 * __clk_init. This callback is mandatory for clocks with
148 * multiple parents. It is optional (and unnecessary) for clocks
149 * with 0 or 1 parents.
150 *
151 * @set_rate: Change the rate of this clock. The requested rate is specified
152 * by the second argument, which should typically be the return
153 * of .round_rate call. The third argument gives the parent rate
154 * which is likely helpful for most .set_rate implementation.
155 * Returns 0 on success, -EERROR otherwise.
156 *
157 * @set_rate_and_parent: Change the rate and the parent of this clock. The
158 * requested rate is specified by the second argument, which
159 * should typically be the return of .round_rate call. The
160 * third argument gives the parent rate which is likely helpful
161 * for most .set_rate_and_parent implementation. The fourth
162 * argument gives the parent index. This callback is optional (and
163 * unnecessary) for clocks with 0 or 1 parents as well as
164 * for clocks that can tolerate switching the rate and the parent
165 * separately via calls to .set_parent and .set_rate.
166 * Returns 0 on success, -EERROR otherwise.
167 *
168 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
169 * is expressed in ppb (parts per billion). The parent accuracy is
170 * an input parameter.
171 * Returns the calculated accuracy. Optional - if this op is not
172 * set then clock accuracy will be initialized to parent accuracy
173 * or 0 (perfect clock) if clock has no parent.
174 *
175 * @get_phase: Queries the hardware to get the current phase of a clock.
176 * Returned values are 0-359 degrees on success, negative
177 * error codes on failure.
178 *
179 * @set_phase: Shift the phase this clock signal in degrees specified
180 * by the second argument. Valid values for degrees are
181 * 0-359. Return 0 on success, otherwise -EERROR.
182 *
183 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
184 * of a clock. Returned values denominator cannot be 0 and must be
185 * superior or equal to the numerator.
186 *
187 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
188 * the numerator (2nd argurment) and denominator (3rd argument).
189 * Argument must be a valid ratio (denominator > 0
190 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 *
192 * @init: Perform platform-specific initialization magic.
193 * This is not not used by any of the basic clock types.
194 * Please consider other ways of solving initialization problems
195 * before using this callback, as its use is discouraged.
196 *
197 * @debug_init: Set up type-specific debugfs entries for this clock. This
198 * is called once, after the debugfs directory entry for this
199 * clock has been created. The dentry pointer representing that
200 * directory is provided as an argument. Called with
201 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
202 *
203 * @pre_rate_change: Optional callback for a clock to fulfill its rate
204 * change requirements before any rate change has occurred in
205 * its clock tree. Returns 0 on success, -EERROR otherwise.
206 *
207 * @post_rate_change: Optional callback for a clock to clean up any
208 * requirements that were needed while the clock and its tree
209 * was changing states. Returns 0 on success, -EERROR otherwise.
210 *
211 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
212 * implementations to split any work between atomic (enable) and sleepable
213 * (prepare) contexts. If enabling a clock requires code that might sleep,
214 * this must be done in clk_prepare. Clock enable code that will never be
215 * called in a sleepable context may be implemented in clk_enable.
216 *
217 * Typically, drivers will call clk_prepare when a clock may be needed later
218 * (eg. when a device is opened), and clk_enable when the clock is actually
219 * required (eg. from an interrupt). Note that clk_prepare MUST have been
220 * called before clk_enable.
221 */
222 struct clk_ops {
223 int (*prepare)(struct clk_hw *hw);
224 void (*unprepare)(struct clk_hw *hw);
225 int (*is_prepared)(struct clk_hw *hw);
226 void (*unprepare_unused)(struct clk_hw *hw);
227 int (*enable)(struct clk_hw *hw);
228 void (*disable)(struct clk_hw *hw);
229 int (*is_enabled)(struct clk_hw *hw);
230 void (*disable_unused)(struct clk_hw *hw);
231 int (*save_context)(struct clk_hw *hw);
232 void (*restore_context)(struct clk_hw *hw);
233 unsigned long (*recalc_rate)(struct clk_hw *hw,
234 unsigned long parent_rate);
235 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
236 unsigned long *parent_rate);
237 int (*determine_rate)(struct clk_hw *hw,
238 struct clk_rate_request *req);
239 int (*set_parent)(struct clk_hw *hw, u8 index);
240 u8 (*get_parent)(struct clk_hw *hw);
241 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
242 unsigned long parent_rate);
243 int (*set_rate_and_parent)(struct clk_hw *hw,
244 unsigned long rate,
245 unsigned long parent_rate, u8 index);
246 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
247 unsigned long parent_accuracy);
248 int (*get_phase)(struct clk_hw *hw);
249 int (*set_phase)(struct clk_hw *hw, int degrees);
250 int (*get_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*set_duty_cycle)(struct clk_hw *hw,
253 struct clk_duty *duty);
254 void (*init)(struct clk_hw *hw);
255 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
256 int (*pre_rate_change)(struct clk_hw *hw,
257 unsigned long rate,
258 unsigned long new_rate);
259 int (*post_rate_change)(struct clk_hw *hw,
260 unsigned long old_rate,
261 unsigned long rate);
262 };
263
264 /**
265 * struct clk_parent_data - clk parent information
266 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
267 * @fw_name: parent name local to provider registering clk
268 * @name: globally unique parent name (used as a fallback)
269 * @index: parent index local to provider registering clk (if @fw_name absent)
270 */
271 struct clk_parent_data {
272 const struct clk_hw *hw;
273 const char *fw_name;
274 const char *name;
275 int index;
276 };
277
278 /**
279 * struct clk_init_data - holds init data that's common to all clocks and is
280 * shared between the clock provider and the common clock framework.
281 *
282 * @name: clock name
283 * @ops: operations this clock supports
284 * @parent_names: array of string names for all possible parents
285 * @parent_data: array of parent data for all possible parents (when some
286 * parents are external to the clk controller)
287 * @parent_hws: array of pointers to all possible parents (when all parents
288 * are internal to the clk controller)
289 * @num_parents: number of possible parents
290 * @flags: framework-level hints and quirks
291 */
292 struct clk_init_data {
293 const char *name;
294 const struct clk_ops *ops;
295 /* Only one of the following three should be assigned */
296 const char * const *parent_names;
297 const struct clk_parent_data *parent_data;
298 const struct clk_hw **parent_hws;
299 u8 num_parents;
300 unsigned long flags;
301 };
302
303 /**
304 * struct clk_hw - handle for traversing from a struct clk to its corresponding
305 * hardware-specific structure. struct clk_hw should be declared within struct
306 * clk_foo and then referenced by the struct clk instance that uses struct
307 * clk_foo's clk_ops
308 *
309 * @core: pointer to the struct clk_core instance that points back to this
310 * struct clk_hw instance
311 *
312 * @clk: pointer to the per-user struct clk instance that can be used to call
313 * into the clk API
314 *
315 * @init: pointer to struct clk_init_data that contains the init data shared
316 * with the common clock framework. This pointer will be set to NULL once
317 * a clk_register() variant is called on this clk_hw pointer.
318 */
319 struct clk_hw {
320 struct clk_core *core;
321 struct clk *clk;
322 const struct clk_init_data *init;
323 };
324
325 /*
326 * DOC: Basic clock implementations common to many platforms
327 *
328 * Each basic clock hardware type is comprised of a structure describing the
329 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
330 * unique flags for that hardware type, a registration function and an
331 * alternative macro for static initialization
332 */
333
334 /**
335 * struct clk_fixed_rate - fixed-rate clock
336 * @hw: handle between common and hardware-specific interfaces
337 * @fixed_rate: constant frequency of clock
338 */
339 struct clk_fixed_rate {
340 struct clk_hw hw;
341 unsigned long fixed_rate;
342 unsigned long fixed_accuracy;
343 };
344
345 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
346
347 extern const struct clk_ops clk_fixed_rate_ops;
348 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
349 const char *parent_name, unsigned long flags,
350 unsigned long fixed_rate);
351 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
352 const char *parent_name, unsigned long flags,
353 unsigned long fixed_rate);
354 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
355 const char *name, const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate, unsigned long fixed_accuracy);
357 void clk_unregister_fixed_rate(struct clk *clk);
358 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
359 const char *name, const char *parent_name, unsigned long flags,
360 unsigned long fixed_rate, unsigned long fixed_accuracy);
361 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
362
363 void of_fixed_clk_setup(struct device_node *np);
364
365 /**
366 * struct clk_gate - gating clock
367 *
368 * @hw: handle between common and hardware-specific interfaces
369 * @reg: register controlling gate
370 * @bit_idx: single bit controlling gate
371 * @flags: hardware-specific flags
372 * @lock: register lock
373 *
374 * Clock which can gate its output. Implements .enable & .disable
375 *
376 * Flags:
377 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
378 * enable the clock. Setting this flag does the opposite: setting the bit
379 * disable the clock and clearing it enables the clock
380 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
381 * of this register, and mask of gate bits are in higher 16-bit of this
382 * register. While setting the gate bits, higher 16-bit should also be
383 * updated to indicate changing gate bits.
384 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
385 * the gate register. Setting this flag makes the register accesses big
386 * endian.
387 */
388 struct clk_gate {
389 struct clk_hw hw;
390 void __iomem *reg;
391 u8 bit_idx;
392 u8 flags;
393 spinlock_t *lock;
394 };
395
396 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
397
398 #define CLK_GATE_SET_TO_DISABLE BIT(0)
399 #define CLK_GATE_HIWORD_MASK BIT(1)
400 #define CLK_GATE_BIG_ENDIAN BIT(2)
401
402 extern const struct clk_ops clk_gate_ops;
403 struct clk *clk_register_gate(struct device *dev, const char *name,
404 const char *parent_name, unsigned long flags,
405 void __iomem *reg, u8 bit_idx,
406 u8 clk_gate_flags, spinlock_t *lock);
407 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
408 const char *parent_name, unsigned long flags,
409 void __iomem *reg, u8 bit_idx,
410 u8 clk_gate_flags, spinlock_t *lock);
411 void clk_unregister_gate(struct clk *clk);
412 void clk_hw_unregister_gate(struct clk_hw *hw);
413 int clk_gate_is_enabled(struct clk_hw *hw);
414
415 struct clk_div_table {
416 unsigned int val;
417 unsigned int div;
418 };
419
420 /**
421 * struct clk_divider - adjustable divider clock
422 *
423 * @hw: handle between common and hardware-specific interfaces
424 * @reg: register containing the divider
425 * @shift: shift to the divider bit field
426 * @width: width of the divider bit field
427 * @table: array of value/divider pairs, last entry should have div = 0
428 * @lock: register lock
429 *
430 * Clock with an adjustable divider affecting its output frequency. Implements
431 * .recalc_rate, .set_rate and .round_rate
432 *
433 * Flags:
434 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
435 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
436 * the raw value read from the register, with the value of zero considered
437 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
438 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
439 * the hardware register
440 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
441 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
442 * Some hardware implementations gracefully handle this case and allow a
443 * zero divisor by not modifying their input clock
444 * (divide by one / bypass).
445 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
446 * of this register, and mask of divider bits are in higher 16-bit of this
447 * register. While setting the divider bits, higher 16-bit should also be
448 * updated to indicate changing divider bits.
449 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
450 * to the closest integer instead of the up one.
451 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
452 * not be changed by the clock framework.
453 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
454 * except when the value read from the register is zero, the divisor is
455 * 2^width of the field.
456 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
457 * for the divider register. Setting this flag makes the register accesses
458 * big endian.
459 */
460 struct clk_divider {
461 struct clk_hw hw;
462 void __iomem *reg;
463 u8 shift;
464 u8 width;
465 u8 flags;
466 const struct clk_div_table *table;
467 spinlock_t *lock;
468 };
469
470 #define clk_div_mask(width) ((1 << (width)) - 1)
471 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
472
473 #define CLK_DIVIDER_ONE_BASED BIT(0)
474 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
475 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
476 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
477 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
478 #define CLK_DIVIDER_READ_ONLY BIT(5)
479 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
480 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
481
482 extern const struct clk_ops clk_divider_ops;
483 extern const struct clk_ops clk_divider_ro_ops;
484
485 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
486 unsigned int val, const struct clk_div_table *table,
487 unsigned long flags, unsigned long width);
488 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
489 unsigned long rate, unsigned long *prate,
490 const struct clk_div_table *table,
491 u8 width, unsigned long flags);
492 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
493 unsigned long rate, unsigned long *prate,
494 const struct clk_div_table *table, u8 width,
495 unsigned long flags, unsigned int val);
496 int divider_get_val(unsigned long rate, unsigned long parent_rate,
497 const struct clk_div_table *table, u8 width,
498 unsigned long flags);
499
500 struct clk *clk_register_divider(struct device *dev, const char *name,
501 const char *parent_name, unsigned long flags,
502 void __iomem *reg, u8 shift, u8 width,
503 u8 clk_divider_flags, spinlock_t *lock);
504 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
505 const char *parent_name, unsigned long flags,
506 void __iomem *reg, u8 shift, u8 width,
507 u8 clk_divider_flags, spinlock_t *lock);
508 struct clk *clk_register_divider_table(struct device *dev, const char *name,
509 const char *parent_name, unsigned long flags,
510 void __iomem *reg, u8 shift, u8 width,
511 u8 clk_divider_flags, const struct clk_div_table *table,
512 spinlock_t *lock);
513 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
514 const char *name, const char *parent_name, unsigned long flags,
515 void __iomem *reg, u8 shift, u8 width,
516 u8 clk_divider_flags, const struct clk_div_table *table,
517 spinlock_t *lock);
518 void clk_unregister_divider(struct clk *clk);
519 void clk_hw_unregister_divider(struct clk_hw *hw);
520
521 /**
522 * struct clk_mux - multiplexer clock
523 *
524 * @hw: handle between common and hardware-specific interfaces
525 * @reg: register controlling multiplexer
526 * @table: array of register values corresponding to the parent index
527 * @shift: shift to multiplexer bit field
528 * @mask: mask of mutliplexer bit field
529 * @flags: hardware-specific flags
530 * @lock: register lock
531 *
532 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
533 * and .recalc_rate
534 *
535 * Flags:
536 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
537 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
538 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
539 * register, and mask of mux bits are in higher 16-bit of this register.
540 * While setting the mux bits, higher 16-bit should also be updated to
541 * indicate changing mux bits.
542 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
543 * .get_parent clk_op.
544 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
545 * frequency.
546 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
547 * the mux register. Setting this flag makes the register accesses big
548 * endian.
549 */
550 struct clk_mux {
551 struct clk_hw hw;
552 void __iomem *reg;
553 u32 *table;
554 u32 mask;
555 u8 shift;
556 u8 flags;
557 spinlock_t *lock;
558 };
559
560 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
561
562 #define CLK_MUX_INDEX_ONE BIT(0)
563 #define CLK_MUX_INDEX_BIT BIT(1)
564 #define CLK_MUX_HIWORD_MASK BIT(2)
565 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
566 #define CLK_MUX_ROUND_CLOSEST BIT(4)
567 #define CLK_MUX_BIG_ENDIAN BIT(5)
568
569 extern const struct clk_ops clk_mux_ops;
570 extern const struct clk_ops clk_mux_ro_ops;
571
572 struct clk *clk_register_mux(struct device *dev, const char *name,
573 const char * const *parent_names, u8 num_parents,
574 unsigned long flags,
575 void __iomem *reg, u8 shift, u8 width,
576 u8 clk_mux_flags, spinlock_t *lock);
577 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
578 const char * const *parent_names, u8 num_parents,
579 unsigned long flags,
580 void __iomem *reg, u8 shift, u8 width,
581 u8 clk_mux_flags, spinlock_t *lock);
582
583 struct clk *clk_register_mux_table(struct device *dev, const char *name,
584 const char * const *parent_names, u8 num_parents,
585 unsigned long flags,
586 void __iomem *reg, u8 shift, u32 mask,
587 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
588 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
589 const char * const *parent_names, u8 num_parents,
590 unsigned long flags,
591 void __iomem *reg, u8 shift, u32 mask,
592 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
593
594 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
595 unsigned int val);
596 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
597
598 void clk_unregister_mux(struct clk *clk);
599 void clk_hw_unregister_mux(struct clk_hw *hw);
600
601 void of_fixed_factor_clk_setup(struct device_node *node);
602
603 /**
604 * struct clk_fixed_factor - fixed multiplier and divider clock
605 *
606 * @hw: handle between common and hardware-specific interfaces
607 * @mult: multiplier
608 * @div: divider
609 *
610 * Clock with a fixed multiplier and divider. The output frequency is the
611 * parent clock rate divided by div and multiplied by mult.
612 * Implements .recalc_rate, .set_rate and .round_rate
613 */
614
615 struct clk_fixed_factor {
616 struct clk_hw hw;
617 unsigned int mult;
618 unsigned int div;
619 };
620
621 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
622
623 extern const struct clk_ops clk_fixed_factor_ops;
624 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
625 const char *parent_name, unsigned long flags,
626 unsigned int mult, unsigned int div);
627 void clk_unregister_fixed_factor(struct clk *clk);
628 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
629 const char *name, const char *parent_name, unsigned long flags,
630 unsigned int mult, unsigned int div);
631 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
632
633 /**
634 * struct clk_fractional_divider - adjustable fractional divider clock
635 *
636 * @hw: handle between common and hardware-specific interfaces
637 * @reg: register containing the divider
638 * @mshift: shift to the numerator bit field
639 * @mwidth: width of the numerator bit field
640 * @nshift: shift to the denominator bit field
641 * @nwidth: width of the denominator bit field
642 * @lock: register lock
643 *
644 * Clock with adjustable fractional divider affecting its output frequency.
645 *
646 * Flags:
647 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
648 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
649 * is set then the numerator and denominator are both the value read
650 * plus one.
651 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
652 * used for the divider register. Setting this flag makes the register
653 * accesses big endian.
654 */
655 struct clk_fractional_divider {
656 struct clk_hw hw;
657 void __iomem *reg;
658 u8 mshift;
659 u8 mwidth;
660 u32 mmask;
661 u8 nshift;
662 u8 nwidth;
663 u32 nmask;
664 u8 flags;
665 void (*approximation)(struct clk_hw *hw,
666 unsigned long rate, unsigned long *parent_rate,
667 unsigned long *m, unsigned long *n);
668 spinlock_t *lock;
669 };
670
671 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
672
673 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
674 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
675
676 extern const struct clk_ops clk_fractional_divider_ops;
677 struct clk *clk_register_fractional_divider(struct device *dev,
678 const char *name, const char *parent_name, unsigned long flags,
679 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
680 u8 clk_divider_flags, spinlock_t *lock);
681 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
682 const char *name, const char *parent_name, unsigned long flags,
683 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
684 u8 clk_divider_flags, spinlock_t *lock);
685 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
686
687 /**
688 * struct clk_multiplier - adjustable multiplier clock
689 *
690 * @hw: handle between common and hardware-specific interfaces
691 * @reg: register containing the multiplier
692 * @shift: shift to the multiplier bit field
693 * @width: width of the multiplier bit field
694 * @lock: register lock
695 *
696 * Clock with an adjustable multiplier affecting its output frequency.
697 * Implements .recalc_rate, .set_rate and .round_rate
698 *
699 * Flags:
700 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
701 * from the register, with 0 being a valid value effectively
702 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
703 * set, then a null multiplier will be considered as a bypass,
704 * leaving the parent rate unmodified.
705 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
706 * rounded to the closest integer instead of the down one.
707 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
708 * used for the multiplier register. Setting this flag makes the register
709 * accesses big endian.
710 */
711 struct clk_multiplier {
712 struct clk_hw hw;
713 void __iomem *reg;
714 u8 shift;
715 u8 width;
716 u8 flags;
717 spinlock_t *lock;
718 };
719
720 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
721
722 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
723 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
724 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
725
726 extern const struct clk_ops clk_multiplier_ops;
727
728 /***
729 * struct clk_composite - aggregate clock of mux, divider and gate clocks
730 *
731 * @hw: handle between common and hardware-specific interfaces
732 * @mux_hw: handle between composite and hardware-specific mux clock
733 * @rate_hw: handle between composite and hardware-specific rate clock
734 * @gate_hw: handle between composite and hardware-specific gate clock
735 * @mux_ops: clock ops for mux
736 * @rate_ops: clock ops for rate
737 * @gate_ops: clock ops for gate
738 */
739 struct clk_composite {
740 struct clk_hw hw;
741 struct clk_ops ops;
742
743 struct clk_hw *mux_hw;
744 struct clk_hw *rate_hw;
745 struct clk_hw *gate_hw;
746
747 const struct clk_ops *mux_ops;
748 const struct clk_ops *rate_ops;
749 const struct clk_ops *gate_ops;
750 };
751
752 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
753
754 struct clk *clk_register_composite(struct device *dev, const char *name,
755 const char * const *parent_names, int num_parents,
756 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
757 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
758 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
759 unsigned long flags);
760 void clk_unregister_composite(struct clk *clk);
761 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
762 const char * const *parent_names, int num_parents,
763 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
764 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
765 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
766 unsigned long flags);
767 void clk_hw_unregister_composite(struct clk_hw *hw);
768
769 /**
770 * struct clk_gpio - gpio gated clock
771 *
772 * @hw: handle between common and hardware-specific interfaces
773 * @gpiod: gpio descriptor
774 *
775 * Clock with a gpio control for enabling and disabling the parent clock
776 * or switching between two parents by asserting or deasserting the gpio.
777 *
778 * Implements .enable, .disable and .is_enabled or
779 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
780 * is used.
781 */
782 struct clk_gpio {
783 struct clk_hw hw;
784 struct gpio_desc *gpiod;
785 };
786
787 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
788
789 extern const struct clk_ops clk_gpio_gate_ops;
790 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
791 const char *parent_name, struct gpio_desc *gpiod,
792 unsigned long flags);
793 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
794 const char *parent_name, struct gpio_desc *gpiod,
795 unsigned long flags);
796 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
797
798 extern const struct clk_ops clk_gpio_mux_ops;
799 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
800 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
801 unsigned long flags);
802 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
803 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
804 unsigned long flags);
805 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
806
807 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
808 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
809
810 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
811 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
812 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
813
814 void clk_unregister(struct clk *clk);
815 void devm_clk_unregister(struct device *dev, struct clk *clk);
816
817 void clk_hw_unregister(struct clk_hw *hw);
818 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
819 void clk_sync_state(struct device *dev);
820
821 /* helper functions */
822 const char *__clk_get_name(const struct clk *clk);
823 const char *clk_hw_get_name(const struct clk_hw *hw);
824 #ifdef CONFIG_COMMON_CLK
825 struct clk_hw *__clk_get_hw(struct clk *clk);
826 #else
__clk_get_hw(struct clk * clk)827 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
828 {
829 return (struct clk_hw *)clk;
830 }
831 #endif
832 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
833 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
834 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
835 unsigned int index);
836 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
837 unsigned int __clk_get_enable_count(struct clk *clk);
838 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
839 unsigned long __clk_get_flags(struct clk *clk);
840 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
841 #define clk_hw_can_set_rate_parent(hw) \
842 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
843
844 bool clk_hw_is_prepared(const struct clk_hw *hw);
845 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
846 bool clk_hw_is_enabled(const struct clk_hw *hw);
847 bool __clk_is_enabled(struct clk *clk);
848 struct clk *__clk_lookup(const char *name);
849 int __clk_mux_determine_rate(struct clk_hw *hw,
850 struct clk_rate_request *req);
851 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
852 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
853 struct clk_rate_request *req);
854 int clk_mux_determine_rate_flags(struct clk_hw *hw,
855 struct clk_rate_request *req,
856 unsigned long flags);
857 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
858 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
859 unsigned long max_rate);
860
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)861 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
862 {
863 dst->clk = src->clk;
864 dst->core = src->core;
865 }
866
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)867 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
868 unsigned long *prate,
869 const struct clk_div_table *table,
870 u8 width, unsigned long flags)
871 {
872 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
873 rate, prate, table, width, flags);
874 }
875
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)876 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
877 unsigned long *prate,
878 const struct clk_div_table *table,
879 u8 width, unsigned long flags,
880 unsigned int val)
881 {
882 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
883 rate, prate, table, width, flags,
884 val);
885 }
886
887 /*
888 * FIXME clock api without lock protection
889 */
890 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
891
892 struct clk_onecell_data {
893 struct clk **clks;
894 unsigned int clk_num;
895 };
896
897 struct clk_hw_onecell_data {
898 unsigned int num;
899 struct clk_hw *hws[];
900 };
901
902 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
903
904 /*
905 * Use this macro when you have a driver that requires two initialization
906 * routines, one at of_clk_init(), and one at platform device probe
907 */
908 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
909 static void __init name##_of_clk_init_driver(struct device_node *np) \
910 { \
911 of_node_clear_flag(np, OF_POPULATED); \
912 fn(np); \
913 } \
914 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
915
916 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
917 (&(struct clk_init_data) { \
918 .flags = _flags, \
919 .name = _name, \
920 .parent_names = (const char *[]) { _parent }, \
921 .num_parents = 1, \
922 .ops = _ops, \
923 })
924
925 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
926 (&(struct clk_init_data) { \
927 .flags = _flags, \
928 .name = _name, \
929 .parent_hws = (const struct clk_hw*[]) { _parent }, \
930 .num_parents = 1, \
931 .ops = _ops, \
932 })
933
934 /*
935 * This macro is intended for drivers to be able to share the otherwise
936 * individual struct clk_hw[] compound literals created by the compiler
937 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
938 */
939 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
940 (&(struct clk_init_data) { \
941 .flags = _flags, \
942 .name = _name, \
943 .parent_hws = _parent, \
944 .num_parents = 1, \
945 .ops = _ops, \
946 })
947
948 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
949 (&(struct clk_init_data) { \
950 .flags = _flags, \
951 .name = _name, \
952 .parent_data = (const struct clk_parent_data[]) { \
953 { .fw_name = _parent }, \
954 }, \
955 .num_parents = 1, \
956 .ops = _ops, \
957 })
958
959 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
960 (&(struct clk_init_data) { \
961 .flags = _flags, \
962 .name = _name, \
963 .parent_names = _parents, \
964 .num_parents = ARRAY_SIZE(_parents), \
965 .ops = _ops, \
966 })
967
968 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
969 (&(struct clk_init_data) { \
970 .flags = _flags, \
971 .name = _name, \
972 .parent_hws = _parents, \
973 .num_parents = ARRAY_SIZE(_parents), \
974 .ops = _ops, \
975 })
976
977 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
978 (&(struct clk_init_data) { \
979 .flags = _flags, \
980 .name = _name, \
981 .parent_data = _parents, \
982 .num_parents = ARRAY_SIZE(_parents), \
983 .ops = _ops, \
984 })
985
986 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
987 (&(struct clk_init_data) { \
988 .flags = _flags, \
989 .name = _name, \
990 .parent_names = NULL, \
991 .num_parents = 0, \
992 .ops = _ops, \
993 })
994
995 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
996 _div, _mult, _flags) \
997 struct clk_fixed_factor _struct = { \
998 .div = _div, \
999 .mult = _mult, \
1000 .hw.init = CLK_HW_INIT(_name, \
1001 _parent, \
1002 &clk_fixed_factor_ops, \
1003 _flags), \
1004 }
1005
1006 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1007 _div, _mult, _flags) \
1008 struct clk_fixed_factor _struct = { \
1009 .div = _div, \
1010 .mult = _mult, \
1011 .hw.init = CLK_HW_INIT_HW(_name, \
1012 _parent, \
1013 &clk_fixed_factor_ops, \
1014 _flags), \
1015 }
1016
1017 /*
1018 * This macro allows the driver to reuse the _parent array for multiple
1019 * fixed factor clk declarations.
1020 */
1021 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1022 _div, _mult, _flags) \
1023 struct clk_fixed_factor _struct = { \
1024 .div = _div, \
1025 .mult = _mult, \
1026 .hw.init = CLK_HW_INIT_HWS(_name, \
1027 _parent, \
1028 &clk_fixed_factor_ops, \
1029 _flags), \
1030 }
1031
1032 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1033 _div, _mult, _flags) \
1034 struct clk_fixed_factor _struct = { \
1035 .div = _div, \
1036 .mult = _mult, \
1037 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1038 _parent, \
1039 &clk_fixed_factor_ops, \
1040 _flags), \
1041 }
1042
1043 #ifdef CONFIG_OF
1044 int of_clk_add_provider(struct device_node *np,
1045 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1046 void *data),
1047 void *data);
1048 int of_clk_add_hw_provider(struct device_node *np,
1049 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1050 void *data),
1051 void *data);
1052 int devm_of_clk_add_hw_provider(struct device *dev,
1053 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1054 void *data),
1055 void *data);
1056 void of_clk_del_provider(struct device_node *np);
1057 void devm_of_clk_del_provider(struct device *dev);
1058 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1059 void *data);
1060 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1061 void *data);
1062 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1063 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1064 void *data);
1065 int of_clk_parent_fill(struct device_node *np, const char **parents,
1066 unsigned int size);
1067 int of_clk_detect_critical(struct device_node *np, int index,
1068 unsigned long *flags);
1069
1070 #else /* !CONFIG_OF */
1071
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1072 static inline int of_clk_add_provider(struct device_node *np,
1073 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1074 void *data),
1075 void *data)
1076 {
1077 return 0;
1078 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1079 static inline int of_clk_add_hw_provider(struct device_node *np,
1080 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1081 void *data),
1082 void *data)
1083 {
1084 return 0;
1085 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1086 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1087 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1088 void *data),
1089 void *data)
1090 {
1091 return 0;
1092 }
of_clk_del_provider(struct device_node * np)1093 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1094 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1095 static inline struct clk *of_clk_src_simple_get(
1096 struct of_phandle_args *clkspec, void *data)
1097 {
1098 return ERR_PTR(-ENOENT);
1099 }
1100 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1101 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1102 {
1103 return ERR_PTR(-ENOENT);
1104 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1105 static inline struct clk *of_clk_src_onecell_get(
1106 struct of_phandle_args *clkspec, void *data)
1107 {
1108 return ERR_PTR(-ENOENT);
1109 }
1110 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1111 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1112 {
1113 return ERR_PTR(-ENOENT);
1114 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1115 static inline int of_clk_parent_fill(struct device_node *np,
1116 const char **parents, unsigned int size)
1117 {
1118 return 0;
1119 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1120 static inline int of_clk_detect_critical(struct device_node *np, int index,
1121 unsigned long *flags)
1122 {
1123 return 0;
1124 }
1125 #endif /* CONFIG_OF */
1126
1127 void clk_gate_restore_context(struct clk_hw *hw);
1128
1129 #endif /* CLK_PROVIDER_H */
1130