1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10
11 #include <linux/mutex.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18
19 /**
20 * Standard SPI NAND flash operations
21 */
22
23 #define SPINAND_RESET_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29 #define SPINAND_WR_EN_DIS_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35 #define SPINAND_READID_OP(ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_NO_ADDR, \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41 #define SPINAND_SET_FEATURE_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47 #define SPINAND_GET_FEATURE_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53 #define SPINAND_BLK_ERASE_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59 #define SPINAND_PAGE_READ_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1))
70
71 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
72 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
73 SPI_MEM_OP_ADDR(3, addr, 1), \
74 SPI_MEM_OP_DUMMY(ndummy, 1), \
75 SPI_MEM_OP_DATA_IN(len, buf, 1))
76
77 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
78 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
79 SPI_MEM_OP_ADDR(2, addr, 1), \
80 SPI_MEM_OP_DUMMY(ndummy, 1), \
81 SPI_MEM_OP_DATA_IN(len, buf, 2))
82
83 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
84 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
85 SPI_MEM_OP_ADDR(3, addr, 1), \
86 SPI_MEM_OP_DUMMY(ndummy, 1), \
87 SPI_MEM_OP_DATA_IN(len, buf, 2))
88
89 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
90 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
91 SPI_MEM_OP_ADDR(2, addr, 1), \
92 SPI_MEM_OP_DUMMY(ndummy, 1), \
93 SPI_MEM_OP_DATA_IN(len, buf, 4))
94
95 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
96 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
97 SPI_MEM_OP_ADDR(3, addr, 1), \
98 SPI_MEM_OP_DUMMY(ndummy, 1), \
99 SPI_MEM_OP_DATA_IN(len, buf, 4))
100
101 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
102 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
103 SPI_MEM_OP_ADDR(2, addr, 2), \
104 SPI_MEM_OP_DUMMY(ndummy, 2), \
105 SPI_MEM_OP_DATA_IN(len, buf, 2))
106
107 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
108 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
109 SPI_MEM_OP_ADDR(3, addr, 2), \
110 SPI_MEM_OP_DUMMY(ndummy, 2), \
111 SPI_MEM_OP_DATA_IN(len, buf, 2))
112
113 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
114 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
115 SPI_MEM_OP_ADDR(2, addr, 4), \
116 SPI_MEM_OP_DUMMY(ndummy, 4), \
117 SPI_MEM_OP_DATA_IN(len, buf, 4))
118
119 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
120 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
121 SPI_MEM_OP_ADDR(3, addr, 4), \
122 SPI_MEM_OP_DUMMY(ndummy, 4), \
123 SPI_MEM_OP_DATA_IN(len, buf, 4))
124
125 #define SPINAND_PROG_EXEC_OP(addr) \
126 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
127 SPI_MEM_OP_ADDR(3, addr, 1), \
128 SPI_MEM_OP_NO_DUMMY, \
129 SPI_MEM_OP_NO_DATA)
130
131 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \
132 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
133 SPI_MEM_OP_ADDR(2, addr, 1), \
134 SPI_MEM_OP_NO_DUMMY, \
135 SPI_MEM_OP_DATA_OUT(len, buf, 1))
136
137 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
138 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
139 SPI_MEM_OP_ADDR(2, addr, 1), \
140 SPI_MEM_OP_NO_DUMMY, \
141 SPI_MEM_OP_DATA_OUT(len, buf, 4))
142
143 /**
144 * Standard SPI NAND flash commands
145 */
146 #define SPINAND_CMD_PROG_LOAD_X4 0x32
147 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
148
149 /* feature register */
150 #define REG_BLOCK_LOCK 0xa0
151 #define BL_ALL_UNLOCKED 0x00
152
153 /* configuration register */
154 #define REG_CFG 0xb0
155 #define CFG_OTP_ENABLE BIT(6)
156 #define CFG_ECC_ENABLE BIT(4)
157 #define CFG_QUAD_ENABLE BIT(0)
158
159 /* status register */
160 #define REG_STATUS 0xc0
161 #define STATUS_BUSY BIT(0)
162 #define STATUS_ERASE_FAILED BIT(2)
163 #define STATUS_PROG_FAILED BIT(3)
164 #define STATUS_ECC_MASK GENMASK(5, 4)
165 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
166 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
167 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
168
169 struct spinand_op;
170 struct spinand_device;
171
172 #define SPINAND_MAX_ID_LEN 4
173
174 /**
175 * struct spinand_id - SPI NAND id structure
176 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
177 * be extended if required
178 * @len: ID length
179 *
180 * struct_spinand_id->data contains all bytes returned after a READ_ID command,
181 * including dummy bytes if the chip does not emit ID bytes right after the
182 * READ_ID command. The responsibility to extract real ID bytes is left to
183 * struct_manufacurer_ops->detect().
184 */
185 struct spinand_id {
186 u8 data[SPINAND_MAX_ID_LEN];
187 int len;
188 };
189
190 /**
191 * struct manufacurer_ops - SPI NAND manufacturer specific operations
192 * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
193 * the core calls the struct_manufacurer_ops->detect() hook of each
194 * registered manufacturer until one of them return 1. Note that
195 * the first thing to check in this hook is that the manufacturer ID
196 * in struct_spinand_device->id matches the manufacturer whose
197 * ->detect() hook has been called. Should return 1 if there's a
198 * match, 0 if the manufacturer ID does not match and a negative
199 * error code otherwise. When true is returned, the core assumes
200 * that properties of the NAND chip (spinand->base.memorg and
201 * spinand->base.eccreq) have been filled
202 * @init: initialize a SPI NAND device
203 * @cleanup: cleanup a SPI NAND device
204 *
205 * Each SPI NAND manufacturer driver should implement this interface so that
206 * NAND chips coming from this vendor can be detected and initialized properly.
207 */
208 struct spinand_manufacturer_ops {
209 int (*detect)(struct spinand_device *spinand);
210 int (*init)(struct spinand_device *spinand);
211 void (*cleanup)(struct spinand_device *spinand);
212 };
213
214 /**
215 * struct spinand_manufacturer - SPI NAND manufacturer instance
216 * @id: manufacturer ID
217 * @name: manufacturer name
218 * @ops: manufacturer operations
219 */
220 struct spinand_manufacturer {
221 u8 id;
222 char *name;
223 const struct spinand_manufacturer_ops *ops;
224 };
225
226 /* SPI NAND manufacturers */
227 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
228 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
229 extern const struct spinand_manufacturer micron_spinand_manufacturer;
230 extern const struct spinand_manufacturer paragon_spinand_manufacturer;
231 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
232 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
233
234 /**
235 * struct spinand_op_variants - SPI NAND operation variants
236 * @ops: the list of variants for a given operation
237 * @nops: the number of variants
238 *
239 * Some operations like read-from-cache/write-to-cache have several variants
240 * depending on the number of IO lines you use to transfer data or address
241 * cycles. This structure is a way to describe the different variants supported
242 * by a chip and let the core pick the best one based on the SPI mem controller
243 * capabilities.
244 */
245 struct spinand_op_variants {
246 const struct spi_mem_op *ops;
247 unsigned int nops;
248 };
249
250 #define SPINAND_OP_VARIANTS(name, ...) \
251 const struct spinand_op_variants name = { \
252 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
253 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
254 sizeof(struct spi_mem_op), \
255 }
256
257 /**
258 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
259 * chip
260 * @get_status: get the ECC status. Should return a positive number encoding
261 * the number of corrected bitflips if correction was possible or
262 * -EBADMSG if there are uncorrectable errors. I can also return
263 * other negative error codes if the error is not caused by
264 * uncorrectable bitflips
265 * @ooblayout: the OOB layout used by the on-die ECC implementation
266 */
267 struct spinand_ecc_info {
268 int (*get_status)(struct spinand_device *spinand, u8 status);
269 const struct mtd_ooblayout_ops *ooblayout;
270 };
271
272 #define SPINAND_HAS_QE_BIT BIT(0)
273
274 /**
275 * struct spinand_info - Structure used to describe SPI NAND chips
276 * @model: model name
277 * @devid: device ID
278 * @flags: OR-ing of the SPINAND_XXX flags
279 * @memorg: memory organization
280 * @eccreq: ECC requirements
281 * @eccinfo: on-die ECC info
282 * @op_variants: operations variants
283 * @op_variants.read_cache: variants of the read-cache operation
284 * @op_variants.write_cache: variants of the write-cache operation
285 * @op_variants.update_cache: variants of the update-cache operation
286 * @select_target: function used to select a target/die. Required only for
287 * multi-die chips
288 *
289 * Each SPI NAND manufacturer driver should have a spinand_info table
290 * describing all the chips supported by the driver.
291 */
292 struct spinand_info {
293 const char *model;
294 u16 devid;
295 u32 flags;
296 struct nand_memory_organization memorg;
297 struct nand_ecc_req eccreq;
298 struct spinand_ecc_info eccinfo;
299 struct {
300 const struct spinand_op_variants *read_cache;
301 const struct spinand_op_variants *write_cache;
302 const struct spinand_op_variants *update_cache;
303 } op_variants;
304 int (*select_target)(struct spinand_device *spinand,
305 unsigned int target);
306 };
307
308 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
309 { \
310 .read_cache = __read, \
311 .write_cache = __write, \
312 .update_cache = __update, \
313 }
314
315 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
316 .eccinfo = { \
317 .ooblayout = __ooblayout, \
318 .get_status = __get_status, \
319 }
320
321 #define SPINAND_SELECT_TARGET(__func) \
322 .select_target = __func,
323
324 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
325 __flags, ...) \
326 { \
327 .model = __model, \
328 .devid = __id, \
329 .memorg = __memorg, \
330 .eccreq = __eccreq, \
331 .op_variants = __op_variants, \
332 .flags = __flags, \
333 __VA_ARGS__ \
334 }
335
336 struct spinand_dirmap {
337 struct spi_mem_dirmap_desc *wdesc;
338 struct spi_mem_dirmap_desc *rdesc;
339 };
340
341 /**
342 * struct spinand_device - SPI NAND device instance
343 * @base: NAND device instance
344 * @spimem: pointer to the SPI mem object
345 * @lock: lock used to serialize accesses to the NAND
346 * @id: NAND ID as returned by READ_ID
347 * @flags: NAND flags
348 * @op_templates: various SPI mem op templates
349 * @op_templates.read_cache: read cache op template
350 * @op_templates.write_cache: write cache op template
351 * @op_templates.update_cache: update cache op template
352 * @select_target: select a specific target/die. Usually called before sending
353 * a command addressing a page or an eraseblock embedded in
354 * this die. Only required if your chip exposes several dies
355 * @cur_target: currently selected target/die
356 * @eccinfo: on-die ECC information
357 * @cfg_cache: config register cache. One entry per die
358 * @databuf: bounce buffer for data
359 * @oobbuf: bounce buffer for OOB data
360 * @scratchbuf: buffer used for everything but page accesses. This is needed
361 * because the spi-mem interface explicitly requests that buffers
362 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
363 * the stack
364 * @manufacturer: SPI NAND manufacturer information
365 * @priv: manufacturer private data
366 */
367 struct spinand_device {
368 struct nand_device base;
369 struct spi_mem *spimem;
370 struct mutex lock;
371 struct spinand_id id;
372 u32 flags;
373
374 struct {
375 const struct spi_mem_op *read_cache;
376 const struct spi_mem_op *write_cache;
377 const struct spi_mem_op *update_cache;
378 } op_templates;
379
380 struct spinand_dirmap *dirmaps;
381
382 int (*select_target)(struct spinand_device *spinand,
383 unsigned int target);
384 unsigned int cur_target;
385
386 struct spinand_ecc_info eccinfo;
387
388 u8 *cfg_cache;
389 u8 *databuf;
390 u8 *oobbuf;
391 u8 *scratchbuf;
392 const struct spinand_manufacturer *manufacturer;
393 void *priv;
394 };
395
396 /**
397 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
398 * @mtd: MTD instance
399 *
400 * Return: the SPI NAND device attached to @mtd.
401 */
mtd_to_spinand(struct mtd_info * mtd)402 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
403 {
404 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
405 }
406
407 /**
408 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
409 * @spinand: SPI NAND device
410 *
411 * Return: the MTD device embedded in @spinand.
412 */
spinand_to_mtd(struct spinand_device * spinand)413 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
414 {
415 return nanddev_to_mtd(&spinand->base);
416 }
417
418 /**
419 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
420 * @nand: NAND object
421 *
422 * Return: the SPI NAND device embedding @nand.
423 */
nand_to_spinand(struct nand_device * nand)424 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
425 {
426 return container_of(nand, struct spinand_device, base);
427 }
428
429 /**
430 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
431 * @spinand: SPI NAND device
432 *
433 * Return: the NAND device embedded in @spinand.
434 */
435 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)436 spinand_to_nand(struct spinand_device *spinand)
437 {
438 return &spinand->base;
439 }
440
441 /**
442 * spinand_set_of_node - Attach a DT node to a SPI NAND device
443 * @spinand: SPI NAND device
444 * @np: DT node
445 *
446 * Attach a DT node to a SPI NAND device.
447 */
spinand_set_of_node(struct spinand_device * spinand,struct device_node * np)448 static inline void spinand_set_of_node(struct spinand_device *spinand,
449 struct device_node *np)
450 {
451 nanddev_set_of_node(&spinand->base, np);
452 }
453
454 int spinand_match_and_init(struct spinand_device *dev,
455 const struct spinand_info *table,
456 unsigned int table_size, u16 devid);
457
458 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
459 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
460
461 #endif /* __LINUX_MTD_SPINAND_H */
462