1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 10 memtimer: timer@2a810000 { 11 compatible = "arm,armv7-timer-mem"; 12 reg = <0x0 0x2a810000 0x0 0x10000>; 13 clock-frequency = <50000000>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 ranges; 17 status = "disabled"; 18 frame@2a830000 { 19 frame-number = <1>; 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 21 reg = <0x0 0x2a830000 0x0 0x10000>; 22 }; 23 }; 24 25 mailbox: mhu@2b1f0000 { 26 compatible = "arm,mhu", "arm,primecell"; 27 reg = <0x0 0x2b1f0000 0x0 0x1000>; 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-names = "mhu_lpri_rx", 31 "mhu_hpri_rx"; 32 #mbox-cells = <1>; 33 clocks = <&soc_refclk100mhz>; 34 clock-names = "apb_pclk"; 35 }; 36 37 smmu_pcie: iommu@2b500000 { 38 compatible = "arm,mmu-401", "arm,smmu-v1"; 39 reg = <0x0 0x2b500000 0x0 0x10000>; 40 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 42 #iommu-cells = <1>; 43 #global-interrupts = <1>; 44 dma-coherent; 45 status = "disabled"; 46 }; 47 48 smmu_etr: iommu@2b600000 { 49 compatible = "arm,mmu-401", "arm,smmu-v1"; 50 reg = <0x0 0x2b600000 0x0 0x10000>; 51 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 53 #iommu-cells = <1>; 54 #global-interrupts = <1>; 55 dma-coherent; 56 power-domains = <&scpi_devpd 0>; 57 }; 58 59 gic: interrupt-controller@2c010000 { 60 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 61 reg = <0x0 0x2c010000 0 0x1000>, 62 <0x0 0x2c02f000 0 0x2000>, 63 <0x0 0x2c04f000 0 0x2000>, 64 <0x0 0x2c06f000 0 0x2000>; 65 #address-cells = <2>; 66 #interrupt-cells = <3>; 67 #size-cells = <2>; 68 interrupt-controller; 69 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 70 ranges = <0 0 0 0x2c1c0000 0 0x40000>; 71 72 v2m_0: v2m@0 { 73 compatible = "arm,gic-v2m-frame"; 74 msi-controller; 75 reg = <0 0 0 0x10000>; 76 }; 77 78 v2m@10000 { 79 compatible = "arm,gic-v2m-frame"; 80 msi-controller; 81 reg = <0 0x10000 0 0x10000>; 82 }; 83 84 v2m@20000 { 85 compatible = "arm,gic-v2m-frame"; 86 msi-controller; 87 reg = <0 0x20000 0 0x10000>; 88 }; 89 90 v2m@30000 { 91 compatible = "arm,gic-v2m-frame"; 92 msi-controller; 93 reg = <0 0x30000 0 0x10000>; 94 }; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 103 }; 104 105 /* 106 * Juno TRMs specify the size for these coresight components as 64K. 107 * The actual size is just 4K though 64K is reserved. Access to the 108 * unmapped reserved region results in a DECERR response. 109 */ 110 etf@20010000 { /* etf0 */ 111 compatible = "arm,coresight-tmc", "arm,primecell"; 112 reg = <0 0x20010000 0 0x1000>; 113 114 clocks = <&soc_smc50mhz>; 115 clock-names = "apb_pclk"; 116 power-domains = <&scpi_devpd 0>; 117 118 in-ports { 119 port { 120 etf0_in_port: endpoint { 121 remote-endpoint = <&main_funnel_out_port>; 122 }; 123 }; 124 }; 125 126 out-ports { 127 port { 128 etf0_out_port: endpoint { 129 }; 130 }; 131 }; 132 }; 133 134 tpiu@20030000 { 135 compatible = "arm,coresight-tpiu", "arm,primecell"; 136 reg = <0 0x20030000 0 0x1000>; 137 138 clocks = <&soc_smc50mhz>; 139 clock-names = "apb_pclk"; 140 power-domains = <&scpi_devpd 0>; 141 in-ports { 142 port { 143 tpiu_in_port: endpoint { 144 remote-endpoint = <&replicator_out_port0>; 145 }; 146 }; 147 }; 148 }; 149 150 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 151 main_funnel: funnel@20040000 { 152 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 153 reg = <0 0x20040000 0 0x1000>; 154 155 clocks = <&soc_smc50mhz>; 156 clock-names = "apb_pclk"; 157 power-domains = <&scpi_devpd 0>; 158 159 out-ports { 160 port { 161 main_funnel_out_port: endpoint { 162 remote-endpoint = <&etf0_in_port>; 163 }; 164 }; 165 }; 166 167 main_funnel_in_ports: in-ports { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 port@0 { 172 reg = <0>; 173 main_funnel_in_port0: endpoint { 174 remote-endpoint = <&cluster0_funnel_out_port>; 175 }; 176 }; 177 178 port@1 { 179 reg = <1>; 180 main_funnel_in_port1: endpoint { 181 remote-endpoint = <&cluster1_funnel_out_port>; 182 }; 183 }; 184 }; 185 }; 186 187 etr@20070000 { 188 compatible = "arm,coresight-tmc", "arm,primecell"; 189 reg = <0 0x20070000 0 0x1000>; 190 iommus = <&smmu_etr 0>; 191 192 clocks = <&soc_smc50mhz>; 193 clock-names = "apb_pclk"; 194 power-domains = <&scpi_devpd 0>; 195 arm,scatter-gather; 196 in-ports { 197 port { 198 etr_in_port: endpoint { 199 remote-endpoint = <&replicator_out_port1>; 200 }; 201 }; 202 }; 203 }; 204 205 stm@20100000 { 206 compatible = "arm,coresight-stm", "arm,primecell"; 207 reg = <0 0x20100000 0 0x1000>, 208 <0 0x28000000 0 0x1000000>; 209 reg-names = "stm-base", "stm-stimulus-base"; 210 211 clocks = <&soc_smc50mhz>; 212 clock-names = "apb_pclk"; 213 power-domains = <&scpi_devpd 0>; 214 out-ports { 215 port { 216 stm_out_port: endpoint { 217 }; 218 }; 219 }; 220 }; 221 222 replicator@20120000 { 223 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 224 reg = <0 0x20120000 0 0x1000>; 225 226 clocks = <&soc_smc50mhz>; 227 clock-names = "apb_pclk"; 228 power-domains = <&scpi_devpd 0>; 229 230 out-ports { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 /* replicator output ports */ 235 port@0 { 236 reg = <0>; 237 replicator_out_port0: endpoint { 238 remote-endpoint = <&tpiu_in_port>; 239 }; 240 }; 241 242 port@1 { 243 reg = <1>; 244 replicator_out_port1: endpoint { 245 remote-endpoint = <&etr_in_port>; 246 }; 247 }; 248 }; 249 in-ports { 250 port { 251 replicator_in_port0: endpoint { 252 }; 253 }; 254 }; 255 }; 256 257 cpu_debug0: cpu-debug@22010000 { 258 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 259 reg = <0x0 0x22010000 0x0 0x1000>; 260 261 clocks = <&soc_smc50mhz>; 262 clock-names = "apb_pclk"; 263 power-domains = <&scpi_devpd 0>; 264 }; 265 266 etm0: etm@22040000 { 267 compatible = "arm,coresight-etm4x", "arm,primecell"; 268 reg = <0 0x22040000 0 0x1000>; 269 270 clocks = <&soc_smc50mhz>; 271 clock-names = "apb_pclk"; 272 power-domains = <&scpi_devpd 0>; 273 out-ports { 274 port { 275 cluster0_etm0_out_port: endpoint { 276 remote-endpoint = <&cluster0_funnel_in_port0>; 277 }; 278 }; 279 }; 280 }; 281 282 funnel@220c0000 { /* cluster0 funnel */ 283 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 284 reg = <0 0x220c0000 0 0x1000>; 285 286 clocks = <&soc_smc50mhz>; 287 clock-names = "apb_pclk"; 288 power-domains = <&scpi_devpd 0>; 289 out-ports { 290 port { 291 cluster0_funnel_out_port: endpoint { 292 remote-endpoint = <&main_funnel_in_port0>; 293 }; 294 }; 295 }; 296 297 in-ports { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 301 port@0 { 302 reg = <0>; 303 cluster0_funnel_in_port0: endpoint { 304 remote-endpoint = <&cluster0_etm0_out_port>; 305 }; 306 }; 307 308 port@1 { 309 reg = <1>; 310 cluster0_funnel_in_port1: endpoint { 311 remote-endpoint = <&cluster0_etm1_out_port>; 312 }; 313 }; 314 }; 315 }; 316 317 cpu_debug1: cpu-debug@22110000 { 318 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 319 reg = <0x0 0x22110000 0x0 0x1000>; 320 321 clocks = <&soc_smc50mhz>; 322 clock-names = "apb_pclk"; 323 power-domains = <&scpi_devpd 0>; 324 }; 325 326 etm1: etm@22140000 { 327 compatible = "arm,coresight-etm4x", "arm,primecell"; 328 reg = <0 0x22140000 0 0x1000>; 329 330 clocks = <&soc_smc50mhz>; 331 clock-names = "apb_pclk"; 332 power-domains = <&scpi_devpd 0>; 333 out-ports { 334 port { 335 cluster0_etm1_out_port: endpoint { 336 remote-endpoint = <&cluster0_funnel_in_port1>; 337 }; 338 }; 339 }; 340 }; 341 342 cpu_debug2: cpu-debug@23010000 { 343 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 344 reg = <0x0 0x23010000 0x0 0x1000>; 345 346 clocks = <&soc_smc50mhz>; 347 clock-names = "apb_pclk"; 348 power-domains = <&scpi_devpd 0>; 349 }; 350 351 etm2: etm@23040000 { 352 compatible = "arm,coresight-etm4x", "arm,primecell"; 353 reg = <0 0x23040000 0 0x1000>; 354 355 clocks = <&soc_smc50mhz>; 356 clock-names = "apb_pclk"; 357 power-domains = <&scpi_devpd 0>; 358 out-ports { 359 port { 360 cluster1_etm0_out_port: endpoint { 361 remote-endpoint = <&cluster1_funnel_in_port0>; 362 }; 363 }; 364 }; 365 }; 366 367 funnel@230c0000 { /* cluster1 funnel */ 368 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 369 reg = <0 0x230c0000 0 0x1000>; 370 371 clocks = <&soc_smc50mhz>; 372 clock-names = "apb_pclk"; 373 power-domains = <&scpi_devpd 0>; 374 out-ports { 375 port { 376 cluster1_funnel_out_port: endpoint { 377 remote-endpoint = <&main_funnel_in_port1>; 378 }; 379 }; 380 }; 381 382 in-ports { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 port@0 { 387 reg = <0>; 388 cluster1_funnel_in_port0: endpoint { 389 remote-endpoint = <&cluster1_etm0_out_port>; 390 }; 391 }; 392 393 port@1 { 394 reg = <1>; 395 cluster1_funnel_in_port1: endpoint { 396 remote-endpoint = <&cluster1_etm1_out_port>; 397 }; 398 }; 399 port@2 { 400 reg = <2>; 401 cluster1_funnel_in_port2: endpoint { 402 remote-endpoint = <&cluster1_etm2_out_port>; 403 }; 404 }; 405 port@3 { 406 reg = <3>; 407 cluster1_funnel_in_port3: endpoint { 408 remote-endpoint = <&cluster1_etm3_out_port>; 409 }; 410 }; 411 }; 412 }; 413 414 cpu_debug3: cpu-debug@23110000 { 415 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 416 reg = <0x0 0x23110000 0x0 0x1000>; 417 418 clocks = <&soc_smc50mhz>; 419 clock-names = "apb_pclk"; 420 power-domains = <&scpi_devpd 0>; 421 }; 422 423 etm3: etm@23140000 { 424 compatible = "arm,coresight-etm4x", "arm,primecell"; 425 reg = <0 0x23140000 0 0x1000>; 426 427 clocks = <&soc_smc50mhz>; 428 clock-names = "apb_pclk"; 429 power-domains = <&scpi_devpd 0>; 430 out-ports { 431 port { 432 cluster1_etm1_out_port: endpoint { 433 remote-endpoint = <&cluster1_funnel_in_port1>; 434 }; 435 }; 436 }; 437 }; 438 439 cpu_debug4: cpu-debug@23210000 { 440 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 441 reg = <0x0 0x23210000 0x0 0x1000>; 442 443 clocks = <&soc_smc50mhz>; 444 clock-names = "apb_pclk"; 445 power-domains = <&scpi_devpd 0>; 446 }; 447 448 etm4: etm@23240000 { 449 compatible = "arm,coresight-etm4x", "arm,primecell"; 450 reg = <0 0x23240000 0 0x1000>; 451 452 clocks = <&soc_smc50mhz>; 453 clock-names = "apb_pclk"; 454 power-domains = <&scpi_devpd 0>; 455 out-ports { 456 port { 457 cluster1_etm2_out_port: endpoint { 458 remote-endpoint = <&cluster1_funnel_in_port2>; 459 }; 460 }; 461 }; 462 }; 463 464 cpu_debug5: cpu-debug@23310000 { 465 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 466 reg = <0x0 0x23310000 0x0 0x1000>; 467 468 clocks = <&soc_smc50mhz>; 469 clock-names = "apb_pclk"; 470 power-domains = <&scpi_devpd 0>; 471 }; 472 473 etm5: etm@23340000 { 474 compatible = "arm,coresight-etm4x", "arm,primecell"; 475 reg = <0 0x23340000 0 0x1000>; 476 477 clocks = <&soc_smc50mhz>; 478 clock-names = "apb_pclk"; 479 power-domains = <&scpi_devpd 0>; 480 out-ports { 481 port { 482 cluster1_etm3_out_port: endpoint { 483 remote-endpoint = <&cluster1_funnel_in_port3>; 484 }; 485 }; 486 }; 487 }; 488 489 sram: sram@2e000000 { 490 compatible = "arm,juno-sram-ns", "mmio-sram"; 491 reg = <0x0 0x2e000000 0x0 0x8000>; 492 493 #address-cells = <1>; 494 #size-cells = <1>; 495 ranges = <0 0x0 0x2e000000 0x8000>; 496 497 cpu_scp_lpri: scp-shmem@0 { 498 compatible = "arm,juno-scp-shmem"; 499 reg = <0x0 0x200>; 500 }; 501 502 cpu_scp_hpri: scp-shmem@200 { 503 compatible = "arm,juno-scp-shmem"; 504 reg = <0x200 0x200>; 505 }; 506 }; 507 508 pcie_ctlr: pcie@40000000 { 509 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 510 device_type = "pci"; 511 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 512 bus-range = <0 255>; 513 linux,pci-domain = <0>; 514 #address-cells = <3>; 515 #size-cells = <2>; 516 dma-coherent; 517 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 518 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 519 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 520 #interrupt-cells = <1>; 521 interrupt-map-mask = <0 0 0 7>; 522 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 523 <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 524 <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 525 <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 526 msi-parent = <&v2m_0>; 527 status = "disabled"; 528 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 529 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 530 }; 531 532 scpi { 533 compatible = "arm,scpi"; 534 mboxes = <&mailbox 1>; 535 shmem = <&cpu_scp_hpri>; 536 537 clocks { 538 compatible = "arm,scpi-clocks"; 539 540 scpi_dvfs: scpi-dvfs { 541 compatible = "arm,scpi-dvfs-clocks"; 542 #clock-cells = <1>; 543 clock-indices = <0>, <1>, <2>; 544 clock-output-names = "atlclk", "aplclk","gpuclk"; 545 }; 546 scpi_clk: scpi-clk { 547 compatible = "arm,scpi-variable-clocks"; 548 #clock-cells = <1>; 549 clock-indices = <3>; 550 clock-output-names = "pxlclk"; 551 }; 552 }; 553 554 scpi_devpd: scpi-power-domains { 555 compatible = "arm,scpi-power-domains"; 556 num-domains = <2>; 557 #power-domain-cells = <1>; 558 }; 559 560 scpi_sensors0: sensors { 561 compatible = "arm,scpi-sensors"; 562 #thermal-sensor-cells = <1>; 563 }; 564 }; 565 566 thermal-zones { 567 pmic { 568 polling-delay = <1000>; 569 polling-delay-passive = <100>; 570 thermal-sensors = <&scpi_sensors0 0>; 571 }; 572 573 soc { 574 polling-delay = <1000>; 575 polling-delay-passive = <100>; 576 thermal-sensors = <&scpi_sensors0 3>; 577 }; 578 579 big_cluster_thermal_zone: big-cluster { 580 polling-delay = <1000>; 581 polling-delay-passive = <100>; 582 thermal-sensors = <&scpi_sensors0 21>; 583 status = "disabled"; 584 }; 585 586 little_cluster_thermal_zone: little-cluster { 587 polling-delay = <1000>; 588 polling-delay-passive = <100>; 589 thermal-sensors = <&scpi_sensors0 22>; 590 status = "disabled"; 591 }; 592 593 gpu0_thermal_zone: gpu0 { 594 polling-delay = <1000>; 595 polling-delay-passive = <100>; 596 thermal-sensors = <&scpi_sensors0 23>; 597 status = "disabled"; 598 }; 599 600 gpu1_thermal_zone: gpu1 { 601 polling-delay = <1000>; 602 polling-delay-passive = <100>; 603 thermal-sensors = <&scpi_sensors0 24>; 604 status = "disabled"; 605 }; 606 }; 607 608 smmu_dma: iommu@7fb00000 { 609 compatible = "arm,mmu-401", "arm,smmu-v1"; 610 reg = <0x0 0x7fb00000 0x0 0x10000>; 611 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 613 #iommu-cells = <1>; 614 #global-interrupts = <1>; 615 dma-coherent; 616 status = "disabled"; 617 }; 618 619 smmu_hdlcd1: iommu@7fb10000 { 620 compatible = "arm,mmu-401", "arm,smmu-v1"; 621 reg = <0x0 0x7fb10000 0x0 0x10000>; 622 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 624 #iommu-cells = <1>; 625 #global-interrupts = <1>; 626 }; 627 628 smmu_hdlcd0: iommu@7fb20000 { 629 compatible = "arm,mmu-401", "arm,smmu-v1"; 630 reg = <0x0 0x7fb20000 0x0 0x10000>; 631 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 633 #iommu-cells = <1>; 634 #global-interrupts = <1>; 635 }; 636 637 smmu_usb: iommu@7fb30000 { 638 compatible = "arm,mmu-401", "arm,smmu-v1"; 639 reg = <0x0 0x7fb30000 0x0 0x10000>; 640 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 642 #iommu-cells = <1>; 643 #global-interrupts = <1>; 644 dma-coherent; 645 }; 646 647 dma@7ff00000 { 648 compatible = "arm,pl330", "arm,primecell"; 649 reg = <0x0 0x7ff00000 0 0x1000>; 650 #dma-cells = <1>; 651 #dma-channels = <8>; 652 #dma-requests = <32>; 653 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 662 iommus = <&smmu_dma 0>, 663 <&smmu_dma 1>, 664 <&smmu_dma 2>, 665 <&smmu_dma 3>, 666 <&smmu_dma 4>, 667 <&smmu_dma 5>, 668 <&smmu_dma 6>, 669 <&smmu_dma 7>, 670 <&smmu_dma 8>; 671 clocks = <&soc_faxiclk>; 672 clock-names = "apb_pclk"; 673 }; 674 675 hdlcd@7ff50000 { 676 compatible = "arm,hdlcd"; 677 reg = <0 0x7ff50000 0 0x1000>; 678 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 679 iommus = <&smmu_hdlcd1 0>; 680 clocks = <&scpi_clk 3>; 681 clock-names = "pxlclk"; 682 683 port { 684 hdlcd1_output: endpoint { 685 remote-endpoint = <&tda998x_1_input>; 686 }; 687 }; 688 }; 689 690 hdlcd@7ff60000 { 691 compatible = "arm,hdlcd"; 692 reg = <0 0x7ff60000 0 0x1000>; 693 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 694 iommus = <&smmu_hdlcd0 0>; 695 clocks = <&scpi_clk 3>; 696 clock-names = "pxlclk"; 697 698 port { 699 hdlcd0_output: endpoint { 700 remote-endpoint = <&tda998x_0_input>; 701 }; 702 }; 703 }; 704 705 soc_uart0: uart@7ff80000 { 706 compatible = "arm,pl011", "arm,primecell"; 707 reg = <0x0 0x7ff80000 0x0 0x1000>; 708 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 710 clock-names = "uartclk", "apb_pclk"; 711 }; 712 713 i2c@7ffa0000 { 714 compatible = "snps,designware-i2c"; 715 reg = <0x0 0x7ffa0000 0x0 0x1000>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 719 clock-frequency = <400000>; 720 i2c-sda-hold-time-ns = <500>; 721 clocks = <&soc_smc50mhz>; 722 723 hdmi-transmitter@70 { 724 compatible = "nxp,tda998x"; 725 reg = <0x70>; 726 port { 727 tda998x_0_input: endpoint { 728 remote-endpoint = <&hdlcd0_output>; 729 }; 730 }; 731 }; 732 733 hdmi-transmitter@71 { 734 compatible = "nxp,tda998x"; 735 reg = <0x71>; 736 port { 737 tda998x_1_input: endpoint { 738 remote-endpoint = <&hdlcd1_output>; 739 }; 740 }; 741 }; 742 }; 743 744 ohci@7ffb0000 { 745 compatible = "generic-ohci"; 746 reg = <0x0 0x7ffb0000 0x0 0x10000>; 747 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 748 iommus = <&smmu_usb 0>; 749 clocks = <&soc_usb48mhz>; 750 }; 751 752 ehci@7ffc0000 { 753 compatible = "generic-ehci"; 754 reg = <0x0 0x7ffc0000 0x0 0x10000>; 755 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 756 iommus = <&smmu_usb 0>; 757 clocks = <&soc_usb48mhz>; 758 }; 759 760 memory-controller@7ffd0000 { 761 compatible = "arm,pl354", "arm,primecell"; 762 reg = <0 0x7ffd0000 0 0x1000>; 763 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&soc_smc50mhz>; 766 clock-names = "apb_pclk"; 767 }; 768 769 memory@80000000 { 770 device_type = "memory"; 771 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 772 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 773 <0x00000008 0x80000000 0x1 0x80000000>; 774 }; 775 776 smb@8000000 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <1>; 780 ranges = <0 0 0 0x08000000 0x04000000>, 781 <1 0 0 0x14000000 0x04000000>, 782 <2 0 0 0x18000000 0x04000000>, 783 <3 0 0 0x1c000000 0x04000000>, 784 <4 0 0 0x0c000000 0x04000000>, 785 <5 0 0 0x10000000 0x04000000>; 786 787 #interrupt-cells = <1>; 788 interrupt-map-mask = <0 0 15>; 789 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 790 <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 791 <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 792 <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 793 <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 794 <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 795 <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 796 <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 797 <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 798 <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 799 <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 800 <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 801 <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 802 }; 803 804 site2: tlx@60000000 { 805 compatible = "simple-bus"; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 ranges = <0 0 0x60000000 0x10000000>; 809 #interrupt-cells = <1>; 810 interrupt-map-mask = <0 0>; 811 interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 812 }; 813}; 814