1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/clock/qcom,gcc-sdm845.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 spi5 = &spi5; 53 spi6 = &spi6; 54 spi7 = &spi7; 55 spi8 = &spi8; 56 spi9 = &spi9; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 spi12 = &spi12; 60 spi13 = &spi13; 61 spi14 = &spi14; 62 spi15 = &spi15; 63 }; 64 65 chosen { }; 66 67 memory@80000000 { 68 device_type = "memory"; 69 /* We expect the bootloader to fill in the size */ 70 reg = <0 0x80000000 0 0>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 hyp_mem: memory@85700000 { 79 reg = <0 0x85700000 0 0x600000>; 80 no-map; 81 }; 82 83 xbl_mem: memory@85e00000 { 84 reg = <0 0x85e00000 0 0x100000>; 85 no-map; 86 }; 87 88 aop_mem: memory@85fc0000 { 89 reg = <0 0x85fc0000 0 0x20000>; 90 no-map; 91 }; 92 93 aop_cmd_db_mem: memory@85fe0000 { 94 compatible = "qcom,cmd-db"; 95 reg = <0x0 0x85fe0000 0 0x20000>; 96 no-map; 97 }; 98 99 smem_mem: memory@86000000 { 100 reg = <0x0 0x86000000 0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@86200000 { 105 reg = <0 0x86200000 0 0x2d00000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@88f00000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0 0x88f00000 0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 118 qseecom_mem: memory@8ab00000 { 119 reg = <0 0x8ab00000 0 0x1400000>; 120 no-map; 121 }; 122 123 camera_mem: memory@8bf00000 { 124 reg = <0 0x8bf00000 0 0x500000>; 125 no-map; 126 }; 127 128 ipa_fw_mem: memory@8c400000 { 129 reg = <0 0x8c400000 0 0x10000>; 130 no-map; 131 }; 132 133 ipa_gsi_mem: memory@8c410000 { 134 reg = <0 0x8c410000 0 0x5000>; 135 no-map; 136 }; 137 138 gpu_mem: memory@8c415000 { 139 reg = <0 0x8c415000 0 0x2000>; 140 no-map; 141 }; 142 143 adsp_mem: memory@8c500000 { 144 reg = <0 0x8c500000 0 0x1a00000>; 145 no-map; 146 }; 147 148 wlan_msa_mem: memory@8df00000 { 149 reg = <0 0x8df00000 0 0x100000>; 150 no-map; 151 }; 152 153 mpss_region: memory@8e000000 { 154 reg = <0 0x8e000000 0 0x7800000>; 155 no-map; 156 }; 157 158 venus_mem: memory@95800000 { 159 reg = <0 0x95800000 0 0x500000>; 160 no-map; 161 }; 162 163 cdsp_mem: memory@95d00000 { 164 reg = <0 0x95d00000 0 0x800000>; 165 no-map; 166 }; 167 168 mba_region: memory@96500000 { 169 reg = <0 0x96500000 0 0x200000>; 170 no-map; 171 }; 172 173 slpi_mem: memory@96700000 { 174 reg = <0 0x96700000 0 0x1400000>; 175 no-map; 176 }; 177 178 spss_mem: memory@97b00000 { 179 reg = <0 0x97b00000 0 0x100000>; 180 no-map; 181 }; 182 }; 183 184 cpus { 185 #address-cells = <2>; 186 #size-cells = <0>; 187 188 CPU0: cpu@0 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x0>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 capacity-dmips-mhz = <607>; 197 dynamic-power-coefficient = <100>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 next-level-cache = <&L2_0>; 201 L2_0: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 L3_0: l3-cache { 205 compatible = "cache"; 206 }; 207 }; 208 }; 209 210 CPU1: cpu@100 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo385"; 213 reg = <0x0 0x100>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 capacity-dmips-mhz = <607>; 219 dynamic-power-coefficient = <100>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 next-level-cache = <&L2_100>; 223 L2_100: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU2: cpu@200 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo385"; 232 reg = <0x0 0x200>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 capacity-dmips-mhz = <607>; 238 dynamic-power-coefficient = <100>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 next-level-cache = <&L2_200>; 242 L2_200: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU3: cpu@300 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo385"; 251 reg = <0x0 0x300>; 252 enable-method = "psci"; 253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 254 &LITTLE_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 capacity-dmips-mhz = <607>; 257 dynamic-power-coefficient = <100>; 258 qcom,freq-domain = <&cpufreq_hw 0>; 259 #cooling-cells = <2>; 260 next-level-cache = <&L2_300>; 261 L2_300: l2-cache { 262 compatible = "cache"; 263 next-level-cache = <&L3_0>; 264 }; 265 }; 266 267 CPU4: cpu@400 { 268 device_type = "cpu"; 269 compatible = "qcom,kryo385"; 270 reg = <0x0 0x400>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 dynamic-power-coefficient = <396>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 next-level-cache = <&L2_400>; 280 L2_400: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU5: cpu@500 { 287 device_type = "cpu"; 288 compatible = "qcom,kryo385"; 289 reg = <0x0 0x500>; 290 enable-method = "psci"; 291 capacity-dmips-mhz = <1024>; 292 cpu-idle-states = <&BIG_CPU_SLEEP_0 293 &BIG_CPU_SLEEP_1 294 &CLUSTER_SLEEP_0>; 295 dynamic-power-coefficient = <396>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 #cooling-cells = <2>; 298 next-level-cache = <&L2_500>; 299 L2_500: l2-cache { 300 compatible = "cache"; 301 next-level-cache = <&L3_0>; 302 }; 303 }; 304 305 CPU6: cpu@600 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo385"; 308 reg = <0x0 0x600>; 309 enable-method = "psci"; 310 capacity-dmips-mhz = <1024>; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 dynamic-power-coefficient = <396>; 315 qcom,freq-domain = <&cpufreq_hw 1>; 316 #cooling-cells = <2>; 317 next-level-cache = <&L2_600>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 next-level-cache = <&L3_0>; 321 }; 322 }; 323 324 CPU7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo385"; 327 reg = <0x0 0x700>; 328 enable-method = "psci"; 329 capacity-dmips-mhz = <1024>; 330 cpu-idle-states = <&BIG_CPU_SLEEP_0 331 &BIG_CPU_SLEEP_1 332 &CLUSTER_SLEEP_0>; 333 dynamic-power-coefficient = <396>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 next-level-cache = <&L2_700>; 337 L2_700: l2-cache { 338 compatible = "cache"; 339 next-level-cache = <&L3_0>; 340 }; 341 }; 342 343 cpu-map { 344 cluster0 { 345 core0 { 346 cpu = <&CPU0>; 347 }; 348 349 core1 { 350 cpu = <&CPU1>; 351 }; 352 353 core2 { 354 cpu = <&CPU2>; 355 }; 356 357 core3 { 358 cpu = <&CPU3>; 359 }; 360 361 core4 { 362 cpu = <&CPU4>; 363 }; 364 365 core5 { 366 cpu = <&CPU5>; 367 }; 368 369 core6 { 370 cpu = <&CPU6>; 371 }; 372 373 core7 { 374 cpu = <&CPU7>; 375 }; 376 }; 377 }; 378 379 idle-states { 380 entry-method = "psci"; 381 382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 383 compatible = "arm,idle-state"; 384 idle-state-name = "little-power-down"; 385 arm,psci-suspend-param = <0x40000003>; 386 entry-latency-us = <350>; 387 exit-latency-us = <461>; 388 min-residency-us = <1890>; 389 local-timer-stop; 390 }; 391 392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 393 compatible = "arm,idle-state"; 394 idle-state-name = "little-rail-power-down"; 395 arm,psci-suspend-param = <0x40000004>; 396 entry-latency-us = <360>; 397 exit-latency-us = <531>; 398 min-residency-us = <3934>; 399 local-timer-stop; 400 }; 401 402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 403 compatible = "arm,idle-state"; 404 idle-state-name = "big-power-down"; 405 arm,psci-suspend-param = <0x40000003>; 406 entry-latency-us = <264>; 407 exit-latency-us = <621>; 408 min-residency-us = <952>; 409 local-timer-stop; 410 }; 411 412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 413 compatible = "arm,idle-state"; 414 idle-state-name = "big-rail-power-down"; 415 arm,psci-suspend-param = <0x40000004>; 416 entry-latency-us = <702>; 417 exit-latency-us = <1061>; 418 min-residency-us = <4488>; 419 local-timer-stop; 420 }; 421 422 CLUSTER_SLEEP_0: cluster-sleep-0 { 423 compatible = "arm,idle-state"; 424 idle-state-name = "cluster-power-down"; 425 arm,psci-suspend-param = <0x400000F4>; 426 entry-latency-us = <3263>; 427 exit-latency-us = <6562>; 428 min-residency-us = <9987>; 429 local-timer-stop; 430 }; 431 }; 432 }; 433 434 pmu { 435 compatible = "arm,armv8-pmuv3"; 436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 timer { 440 compatible = "arm,armv8-timer"; 441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 445 }; 446 447 clocks { 448 xo_board: xo-board { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <38400000>; 452 clock-output-names = "xo_board"; 453 }; 454 455 sleep_clk: sleep-clk { 456 compatible = "fixed-clock"; 457 #clock-cells = <0>; 458 clock-frequency = <32764>; 459 }; 460 }; 461 462 firmware { 463 scm { 464 compatible = "qcom,scm-sdm845", "qcom,scm"; 465 }; 466 }; 467 468 adsp_pas: remoteproc-adsp { 469 compatible = "qcom,sdm845-adsp-pas"; 470 471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 476 interrupt-names = "wdog", "fatal", "ready", 477 "handover", "stop-ack"; 478 479 clocks = <&rpmhcc RPMH_CXO_CLK>; 480 clock-names = "xo"; 481 482 memory-region = <&adsp_mem>; 483 484 qcom,smem-states = <&adsp_smp2p_out 0>; 485 qcom,smem-state-names = "stop"; 486 487 status = "disabled"; 488 489 glink-edge { 490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 491 label = "lpass"; 492 qcom,remote-pid = <2>; 493 mboxes = <&apss_shared 8>; 494 fastrpc { 495 compatible = "qcom,fastrpc"; 496 qcom,glink-channels = "fastrpcglink-apps-dsp"; 497 label = "adsp"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 compute-cb@3 { 502 compatible = "qcom,fastrpc-compute-cb"; 503 reg = <3>; 504 iommus = <&apps_smmu 0x1823 0x0>; 505 }; 506 507 compute-cb@4 { 508 compatible = "qcom,fastrpc-compute-cb"; 509 reg = <4>; 510 iommus = <&apps_smmu 0x1824 0x0>; 511 }; 512 }; 513 }; 514 }; 515 516 cdsp_pas: remoteproc-cdsp { 517 compatible = "qcom,sdm845-cdsp-pas"; 518 519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 524 interrupt-names = "wdog", "fatal", "ready", 525 "handover", "stop-ack"; 526 527 clocks = <&rpmhcc RPMH_CXO_CLK>; 528 clock-names = "xo"; 529 530 memory-region = <&cdsp_mem>; 531 532 qcom,smem-states = <&cdsp_smp2p_out 0>; 533 qcom,smem-state-names = "stop"; 534 535 status = "disabled"; 536 537 glink-edge { 538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 539 label = "turing"; 540 qcom,remote-pid = <5>; 541 mboxes = <&apss_shared 4>; 542 fastrpc { 543 compatible = "qcom,fastrpc"; 544 qcom,glink-channels = "fastrpcglink-apps-dsp"; 545 label = "cdsp"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 compute-cb@1 { 550 compatible = "qcom,fastrpc-compute-cb"; 551 reg = <1>; 552 iommus = <&apps_smmu 0x1401 0x30>; 553 }; 554 555 compute-cb@2 { 556 compatible = "qcom,fastrpc-compute-cb"; 557 reg = <2>; 558 iommus = <&apps_smmu 0x1402 0x30>; 559 }; 560 561 compute-cb@3 { 562 compatible = "qcom,fastrpc-compute-cb"; 563 reg = <3>; 564 iommus = <&apps_smmu 0x1403 0x30>; 565 }; 566 567 compute-cb@4 { 568 compatible = "qcom,fastrpc-compute-cb"; 569 reg = <4>; 570 iommus = <&apps_smmu 0x1404 0x30>; 571 }; 572 573 compute-cb@5 { 574 compatible = "qcom,fastrpc-compute-cb"; 575 reg = <5>; 576 iommus = <&apps_smmu 0x1405 0x30>; 577 }; 578 579 compute-cb@6 { 580 compatible = "qcom,fastrpc-compute-cb"; 581 reg = <6>; 582 iommus = <&apps_smmu 0x1406 0x30>; 583 }; 584 585 compute-cb@7 { 586 compatible = "qcom,fastrpc-compute-cb"; 587 reg = <7>; 588 iommus = <&apps_smmu 0x1407 0x30>; 589 }; 590 591 compute-cb@8 { 592 compatible = "qcom,fastrpc-compute-cb"; 593 reg = <8>; 594 iommus = <&apps_smmu 0x1408 0x30>; 595 }; 596 }; 597 }; 598 }; 599 600 tcsr_mutex: hwlock { 601 compatible = "qcom,tcsr-mutex"; 602 syscon = <&tcsr_mutex_regs 0 0x1000>; 603 #hwlock-cells = <1>; 604 }; 605 606 smem { 607 compatible = "qcom,smem"; 608 memory-region = <&smem_mem>; 609 hwlocks = <&tcsr_mutex 3>; 610 }; 611 612 smp2p-cdsp { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <94>, <432>; 615 616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 617 618 mboxes = <&apss_shared 6>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <5>; 622 623 cdsp_smp2p_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 cdsp_smp2p_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-lpass { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <443>, <429>; 639 640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&apss_shared 10>; 643 644 qcom,local-pid = <0>; 645 qcom,remote-pid = <2>; 646 647 adsp_smp2p_out: master-kernel { 648 qcom,entry-name = "master-kernel"; 649 #qcom,smem-state-cells = <1>; 650 }; 651 652 adsp_smp2p_in: slave-kernel { 653 qcom,entry-name = "slave-kernel"; 654 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-mpss { 661 compatible = "qcom,smp2p"; 662 qcom,smem = <435>, <428>; 663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&apss_shared 14>; 665 qcom,local-pid = <0>; 666 qcom,remote-pid = <1>; 667 668 modem_smp2p_out: master-kernel { 669 qcom,entry-name = "master-kernel"; 670 #qcom,smem-state-cells = <1>; 671 }; 672 673 modem_smp2p_in: slave-kernel { 674 qcom,entry-name = "slave-kernel"; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 }; 678 }; 679 680 smp2p-slpi { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <481>, <430>; 683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 684 mboxes = <&apss_shared 26>; 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <3>; 687 688 slpi_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 slpi_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 psci { 701 compatible = "arm,psci-1.0"; 702 method = "smc"; 703 }; 704 705 soc: soc@0 { 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges = <0 0 0 0 0x10 0>; 709 dma-ranges = <0 0 0 0 0x10 0>; 710 compatible = "simple-bus"; 711 712 gcc: clock-controller@100000 { 713 compatible = "qcom,gcc-sdm845"; 714 reg = <0 0x00100000 0 0x1f0000>; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 #power-domain-cells = <1>; 718 }; 719 720 qfprom@784000 { 721 compatible = "qcom,qfprom"; 722 reg = <0 0x00784000 0 0x8ff>; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 726 qusb2p_hstx_trim: hstx-trim-primary@1eb { 727 reg = <0x1eb 0x1>; 728 bits = <1 4>; 729 }; 730 731 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 732 reg = <0x1eb 0x2>; 733 bits = <6 4>; 734 }; 735 }; 736 737 rng: rng@793000 { 738 compatible = "qcom,prng-ee"; 739 reg = <0 0x00793000 0 0x1000>; 740 clocks = <&gcc GCC_PRNG_AHB_CLK>; 741 clock-names = "core"; 742 }; 743 744 qupv3_id_0: geniqup@8c0000 { 745 compatible = "qcom,geni-se-qup"; 746 reg = <0 0x008c0000 0 0x6000>; 747 clock-names = "m-ahb", "s-ahb"; 748 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 749 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 750 #address-cells = <2>; 751 #size-cells = <2>; 752 ranges; 753 status = "disabled"; 754 755 i2c0: i2c@880000 { 756 compatible = "qcom,geni-i2c"; 757 reg = <0 0x00880000 0 0x4000>; 758 clock-names = "se"; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&qup_i2c0_default>; 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 spi0: spi@880000 { 769 compatible = "qcom,geni-spi"; 770 reg = <0 0x00880000 0 0x4000>; 771 clock-names = "se"; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&qup_spi0_default>; 775 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "disabled"; 779 }; 780 781 uart0: serial@880000 { 782 compatible = "qcom,geni-uart"; 783 reg = <0 0x00880000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_uart0_default>; 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 789 status = "disabled"; 790 }; 791 792 i2c1: i2c@884000 { 793 compatible = "qcom,geni-i2c"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&qup_i2c1_default>; 799 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 spi1: spi@884000 { 806 compatible = "qcom,geni-spi"; 807 reg = <0 0x00884000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_spi1_default>; 812 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 uart1: serial@884000 { 819 compatible = "qcom,geni-uart"; 820 reg = <0 0x00884000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_uart1_default>; 825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 826 status = "disabled"; 827 }; 828 829 i2c2: i2c@888000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0 0x00888000 0 0x4000>; 832 clock-names = "se"; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_i2c2_default>; 836 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 spi2: spi@888000 { 843 compatible = "qcom,geni-spi"; 844 reg = <0 0x00888000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_spi2_default>; 849 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 uart2: serial@888000 { 856 compatible = "qcom,geni-uart"; 857 reg = <0 0x00888000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_uart2_default>; 862 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 }; 865 866 i2c3: i2c@88c000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x0088c000 0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c3_default>; 873 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 status = "disabled"; 877 }; 878 879 spi3: spi@88c000 { 880 compatible = "qcom,geni-spi"; 881 reg = <0 0x0088c000 0 0x4000>; 882 clock-names = "se"; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_spi3_default>; 886 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 status = "disabled"; 890 }; 891 892 uart3: serial@88c000 { 893 compatible = "qcom,geni-uart"; 894 reg = <0 0x0088c000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_uart3_default>; 899 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 900 status = "disabled"; 901 }; 902 903 i2c4: i2c@890000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00890000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c4_default>; 910 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 916 spi4: spi@890000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00890000 0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_spi4_default>; 923 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 uart4: serial@890000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0 0x00890000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart4_default>; 936 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 937 status = "disabled"; 938 }; 939 940 i2c5: i2c@894000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00894000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c5_default>; 947 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 spi5: spi@894000 { 954 compatible = "qcom,geni-spi"; 955 reg = <0 0x00894000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_spi5_default>; 960 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 uart5: serial@894000 { 967 compatible = "qcom,geni-uart"; 968 reg = <0 0x00894000 0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_uart5_default>; 973 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 974 status = "disabled"; 975 }; 976 977 i2c6: i2c@898000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00898000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c6_default>; 984 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 spi6: spi@898000 { 991 compatible = "qcom,geni-spi"; 992 reg = <0 0x00898000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_spi6_default>; 997 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 uart6: serial@898000 { 1004 compatible = "qcom,geni-uart"; 1005 reg = <0 0x00898000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_uart6_default>; 1010 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c7: i2c@89c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0089c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c7_default>; 1021 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi7: spi@89c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x0089c000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_spi7_default>; 1034 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 uart7: serial@89c000 { 1041 compatible = "qcom,geni-uart"; 1042 reg = <0 0x0089c000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_uart7_default>; 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 qupv3_id_1: geniqup@ac0000 { 1053 compatible = "qcom,geni-se-qup"; 1054 reg = <0 0x00ac0000 0 0x6000>; 1055 clock-names = "m-ahb", "s-ahb"; 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1058 #address-cells = <2>; 1059 #size-cells = <2>; 1060 ranges; 1061 status = "disabled"; 1062 1063 i2c8: i2c@a80000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00a80000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c8_default>; 1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 spi8: spi@a80000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00a80000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi8_default>; 1083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 status = "disabled"; 1087 }; 1088 1089 uart8: serial@a80000 { 1090 compatible = "qcom,geni-uart"; 1091 reg = <0 0x00a80000 0 0x4000>; 1092 clock-names = "se"; 1093 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&qup_uart8_default>; 1096 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1097 status = "disabled"; 1098 }; 1099 1100 i2c9: i2c@a84000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a84000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c9_default>; 1107 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi9: spi@a84000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00a84000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi9_default>; 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 uart9: serial@a84000 { 1127 compatible = "qcom,geni-debug-uart"; 1128 reg = <0 0x00a84000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_uart9_default>; 1133 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c10: i2c@a88000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00a88000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c10_default>; 1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 spi10: spi@a88000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x00a88000 0 0x4000>; 1153 clock-names = "se"; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi10_default>; 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 uart10: serial@a88000 { 1164 compatible = "qcom,geni-uart"; 1165 reg = <0 0x00a88000 0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_uart10_default>; 1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c11: i2c@a8c000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0 0x00a8c000 0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c11_default>; 1181 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 spi11: spi@a8c000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0 0x00a8c000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_spi11_default>; 1194 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 uart11: serial@a8c000 { 1201 compatible = "qcom,geni-uart"; 1202 reg = <0 0x00a8c000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_uart11_default>; 1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c12: i2c@a90000 { 1212 compatible = "qcom,geni-i2c"; 1213 reg = <0 0x00a90000 0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_i2c12_default>; 1218 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 spi12: spi@a90000 { 1225 compatible = "qcom,geni-spi"; 1226 reg = <0 0x00a90000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_spi12_default>; 1231 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 uart12: serial@a90000 { 1238 compatible = "qcom,geni-uart"; 1239 reg = <0 0x00a90000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_uart12_default>; 1244 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1245 status = "disabled"; 1246 }; 1247 1248 i2c13: i2c@a94000 { 1249 compatible = "qcom,geni-i2c"; 1250 reg = <0 0x00a94000 0 0x4000>; 1251 clock-names = "se"; 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_i2c13_default>; 1255 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi13: spi@a94000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a94000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi13_default>; 1268 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 uart13: serial@a94000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x00a94000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart13_default>; 1281 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1282 status = "disabled"; 1283 }; 1284 1285 i2c14: i2c@a98000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a98000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c14_default>; 1292 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 spi14: spi@a98000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a98000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi14_default>; 1305 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 uart14: serial@a98000 { 1312 compatible = "qcom,geni-uart"; 1313 reg = <0 0x00a98000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_uart14_default>; 1318 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c15: i2c@a9c000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a9c000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c15_default>; 1329 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 spi15: spi@a9c000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a9c000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_spi15_default>; 1342 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 uart15: serial@a9c000 { 1349 compatible = "qcom,geni-uart"; 1350 reg = <0 0x00a9c000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_uart15_default>; 1355 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1356 status = "disabled"; 1357 }; 1358 }; 1359 1360 cache-controller@1100000 { 1361 compatible = "qcom,sdm845-llcc"; 1362 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1363 reg-names = "llcc_base", "llcc_broadcast_base"; 1364 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1365 }; 1366 1367 pcie0: pci@1c00000 { 1368 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1369 reg = <0 0x01c00000 0 0x2000>, 1370 <0 0x60000000 0 0xf1d>, 1371 <0 0x60000f20 0 0xa8>, 1372 <0 0x60100000 0 0x100000>; 1373 reg-names = "parf", "dbi", "elbi", "config"; 1374 device_type = "pci"; 1375 linux,pci-domain = <0>; 1376 bus-range = <0x00 0xff>; 1377 num-lanes = <1>; 1378 1379 #address-cells = <3>; 1380 #size-cells = <2>; 1381 1382 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1383 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1384 1385 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "msi"; 1387 #interrupt-cells = <1>; 1388 interrupt-map-mask = <0 0 0 0x7>; 1389 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1390 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1391 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1392 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1393 1394 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1395 <&gcc GCC_PCIE_0_AUX_CLK>, 1396 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1397 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1398 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1399 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1400 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1401 clock-names = "pipe", 1402 "aux", 1403 "cfg", 1404 "bus_master", 1405 "bus_slave", 1406 "slave_q2a", 1407 "tbu"; 1408 1409 iommus = <&apps_smmu 0x1c10 0xf>; 1410 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1411 <0x100 &apps_smmu 0x1c11 0x1>, 1412 <0x200 &apps_smmu 0x1c12 0x1>, 1413 <0x300 &apps_smmu 0x1c13 0x1>, 1414 <0x400 &apps_smmu 0x1c14 0x1>, 1415 <0x500 &apps_smmu 0x1c15 0x1>, 1416 <0x600 &apps_smmu 0x1c16 0x1>, 1417 <0x700 &apps_smmu 0x1c17 0x1>, 1418 <0x800 &apps_smmu 0x1c18 0x1>, 1419 <0x900 &apps_smmu 0x1c19 0x1>, 1420 <0xa00 &apps_smmu 0x1c1a 0x1>, 1421 <0xb00 &apps_smmu 0x1c1b 0x1>, 1422 <0xc00 &apps_smmu 0x1c1c 0x1>, 1423 <0xd00 &apps_smmu 0x1c1d 0x1>, 1424 <0xe00 &apps_smmu 0x1c1e 0x1>, 1425 <0xf00 &apps_smmu 0x1c1f 0x1>; 1426 1427 resets = <&gcc GCC_PCIE_0_BCR>; 1428 reset-names = "pci"; 1429 1430 power-domains = <&gcc PCIE_0_GDSC>; 1431 1432 phys = <&pcie0_lane>; 1433 phy-names = "pciephy"; 1434 1435 status = "disabled"; 1436 }; 1437 1438 pcie0_phy: phy@1c06000 { 1439 compatible = "qcom,sdm845-qmp-pcie-phy"; 1440 reg = <0 0x01c06000 0 0x18c>; 1441 #address-cells = <2>; 1442 #size-cells = <2>; 1443 ranges; 1444 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1445 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1446 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1447 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1448 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1449 1450 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1451 reset-names = "phy"; 1452 1453 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1454 assigned-clock-rates = <100000000>; 1455 1456 status = "disabled"; 1457 1458 pcie0_lane: lanes@1c06200 { 1459 reg = <0 0x01c06200 0 0x128>, 1460 <0 0x01c06400 0 0x1fc>, 1461 <0 0x01c06800 0 0x218>, 1462 <0 0x01c06600 0 0x70>; 1463 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1464 clock-names = "pipe0"; 1465 1466 #phy-cells = <0>; 1467 clock-output-names = "pcie_0_pipe_clk"; 1468 }; 1469 }; 1470 1471 pcie1: pci@1c08000 { 1472 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1473 reg = <0 0x01c08000 0 0x2000>, 1474 <0 0x40000000 0 0xf1d>, 1475 <0 0x40000f20 0 0xa8>, 1476 <0 0x40100000 0 0x100000>; 1477 reg-names = "parf", "dbi", "elbi", "config"; 1478 device_type = "pci"; 1479 linux,pci-domain = <1>; 1480 bus-range = <0x00 0xff>; 1481 num-lanes = <1>; 1482 1483 #address-cells = <3>; 1484 #size-cells = <2>; 1485 1486 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1487 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1488 1489 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1490 interrupt-names = "msi"; 1491 #interrupt-cells = <1>; 1492 interrupt-map-mask = <0 0 0 0x7>; 1493 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1494 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1495 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1496 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1497 1498 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1499 <&gcc GCC_PCIE_1_AUX_CLK>, 1500 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1501 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1502 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1503 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1504 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1505 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1506 clock-names = "pipe", 1507 "aux", 1508 "cfg", 1509 "bus_master", 1510 "bus_slave", 1511 "slave_q2a", 1512 "ref", 1513 "tbu"; 1514 1515 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1516 assigned-clock-rates = <19200000>; 1517 1518 iommus = <&apps_smmu 0x1c00 0xf>; 1519 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1520 <0x100 &apps_smmu 0x1c01 0x1>, 1521 <0x200 &apps_smmu 0x1c02 0x1>, 1522 <0x300 &apps_smmu 0x1c03 0x1>, 1523 <0x400 &apps_smmu 0x1c04 0x1>, 1524 <0x500 &apps_smmu 0x1c05 0x1>, 1525 <0x600 &apps_smmu 0x1c06 0x1>, 1526 <0x700 &apps_smmu 0x1c07 0x1>, 1527 <0x800 &apps_smmu 0x1c08 0x1>, 1528 <0x900 &apps_smmu 0x1c09 0x1>, 1529 <0xa00 &apps_smmu 0x1c0a 0x1>, 1530 <0xb00 &apps_smmu 0x1c0b 0x1>, 1531 <0xc00 &apps_smmu 0x1c0c 0x1>, 1532 <0xd00 &apps_smmu 0x1c0d 0x1>, 1533 <0xe00 &apps_smmu 0x1c0e 0x1>, 1534 <0xf00 &apps_smmu 0x1c0f 0x1>; 1535 1536 resets = <&gcc GCC_PCIE_1_BCR>; 1537 reset-names = "pci"; 1538 1539 power-domains = <&gcc PCIE_1_GDSC>; 1540 1541 interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>; 1542 interconnect-names = "pcie-mem"; 1543 1544 phys = <&pcie1_lane>; 1545 phy-names = "pciephy"; 1546 1547 status = "disabled"; 1548 }; 1549 1550 pcie1_phy: phy@1c0a000 { 1551 compatible = "qcom,sdm845-qhp-pcie-phy"; 1552 reg = <0 0x01c0a000 0 0x800>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges; 1556 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1557 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1558 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1559 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1560 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1561 1562 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1563 reset-names = "phy"; 1564 1565 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1566 assigned-clock-rates = <100000000>; 1567 1568 status = "disabled"; 1569 1570 pcie1_lane: lanes@1c06200 { 1571 reg = <0 0x01c0a800 0 0x800>, 1572 <0 0x01c0a800 0 0x800>, 1573 <0 0x01c0b800 0 0x400>; 1574 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1575 clock-names = "pipe0"; 1576 1577 #phy-cells = <0>; 1578 clock-output-names = "pcie_1_pipe_clk"; 1579 }; 1580 }; 1581 1582 ufs_mem_hc: ufshc@1d84000 { 1583 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1584 "jedec,ufs-2.0"; 1585 reg = <0 0x01d84000 0 0x2500>; 1586 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1587 phys = <&ufs_mem_phy_lanes>; 1588 phy-names = "ufsphy"; 1589 lanes-per-direction = <2>; 1590 power-domains = <&gcc UFS_PHY_GDSC>; 1591 #reset-cells = <1>; 1592 1593 iommus = <&apps_smmu 0x100 0xf>; 1594 1595 clock-names = 1596 "core_clk", 1597 "bus_aggr_clk", 1598 "iface_clk", 1599 "core_clk_unipro", 1600 "ref_clk", 1601 "tx_lane0_sync_clk", 1602 "rx_lane0_sync_clk", 1603 "rx_lane1_sync_clk"; 1604 clocks = 1605 <&gcc GCC_UFS_PHY_AXI_CLK>, 1606 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1607 <&gcc GCC_UFS_PHY_AHB_CLK>, 1608 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1609 <&rpmhcc RPMH_CXO_CLK>, 1610 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1611 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1612 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1613 freq-table-hz = 1614 <50000000 200000000>, 1615 <0 0>, 1616 <0 0>, 1617 <37500000 150000000>, 1618 <0 0>, 1619 <0 0>, 1620 <0 0>, 1621 <0 0>; 1622 1623 status = "disabled"; 1624 }; 1625 1626 ufs_mem_phy: phy@1d87000 { 1627 compatible = "qcom,sdm845-qmp-ufs-phy"; 1628 reg = <0 0x01d87000 0 0x18c>; 1629 #address-cells = <2>; 1630 #size-cells = <2>; 1631 ranges; 1632 clock-names = "ref", 1633 "ref_aux"; 1634 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1635 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1636 1637 resets = <&ufs_mem_hc 0>; 1638 reset-names = "ufsphy"; 1639 status = "disabled"; 1640 1641 ufs_mem_phy_lanes: lanes@1d87400 { 1642 reg = <0 0x01d87400 0 0x108>, 1643 <0 0x01d87600 0 0x1e0>, 1644 <0 0x01d87c00 0 0x1dc>, 1645 <0 0x01d87800 0 0x108>, 1646 <0 0x01d87a00 0 0x1e0>; 1647 #phy-cells = <0>; 1648 }; 1649 }; 1650 1651 tcsr_mutex_regs: syscon@1f40000 { 1652 compatible = "syscon"; 1653 reg = <0 0x01f40000 0 0x40000>; 1654 }; 1655 1656 tlmm: pinctrl@3400000 { 1657 compatible = "qcom,sdm845-pinctrl"; 1658 reg = <0 0x03400000 0 0xc00000>; 1659 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1660 gpio-controller; 1661 #gpio-cells = <2>; 1662 interrupt-controller; 1663 #interrupt-cells = <2>; 1664 gpio-ranges = <&tlmm 0 0 150>; 1665 1666 qspi_clk: qspi-clk { 1667 pinmux { 1668 pins = "gpio95"; 1669 function = "qspi_clk"; 1670 }; 1671 }; 1672 1673 qspi_cs0: qspi-cs0 { 1674 pinmux { 1675 pins = "gpio90"; 1676 function = "qspi_cs"; 1677 }; 1678 }; 1679 1680 qspi_cs1: qspi-cs1 { 1681 pinmux { 1682 pins = "gpio89"; 1683 function = "qspi_cs"; 1684 }; 1685 }; 1686 1687 qspi_data01: qspi-data01 { 1688 pinmux-data { 1689 pins = "gpio91", "gpio92"; 1690 function = "qspi_data"; 1691 }; 1692 }; 1693 1694 qspi_data12: qspi-data12 { 1695 pinmux-data { 1696 pins = "gpio93", "gpio94"; 1697 function = "qspi_data"; 1698 }; 1699 }; 1700 1701 qup_i2c0_default: qup-i2c0-default { 1702 pinmux { 1703 pins = "gpio0", "gpio1"; 1704 function = "qup0"; 1705 }; 1706 }; 1707 1708 qup_i2c1_default: qup-i2c1-default { 1709 pinmux { 1710 pins = "gpio17", "gpio18"; 1711 function = "qup1"; 1712 }; 1713 }; 1714 1715 qup_i2c2_default: qup-i2c2-default { 1716 pinmux { 1717 pins = "gpio27", "gpio28"; 1718 function = "qup2"; 1719 }; 1720 }; 1721 1722 qup_i2c3_default: qup-i2c3-default { 1723 pinmux { 1724 pins = "gpio41", "gpio42"; 1725 function = "qup3"; 1726 }; 1727 }; 1728 1729 qup_i2c4_default: qup-i2c4-default { 1730 pinmux { 1731 pins = "gpio89", "gpio90"; 1732 function = "qup4"; 1733 }; 1734 }; 1735 1736 qup_i2c5_default: qup-i2c5-default { 1737 pinmux { 1738 pins = "gpio85", "gpio86"; 1739 function = "qup5"; 1740 }; 1741 }; 1742 1743 qup_i2c6_default: qup-i2c6-default { 1744 pinmux { 1745 pins = "gpio45", "gpio46"; 1746 function = "qup6"; 1747 }; 1748 }; 1749 1750 qup_i2c7_default: qup-i2c7-default { 1751 pinmux { 1752 pins = "gpio93", "gpio94"; 1753 function = "qup7"; 1754 }; 1755 }; 1756 1757 qup_i2c8_default: qup-i2c8-default { 1758 pinmux { 1759 pins = "gpio65", "gpio66"; 1760 function = "qup8"; 1761 }; 1762 }; 1763 1764 qup_i2c9_default: qup-i2c9-default { 1765 pinmux { 1766 pins = "gpio6", "gpio7"; 1767 function = "qup9"; 1768 }; 1769 }; 1770 1771 qup_i2c10_default: qup-i2c10-default { 1772 pinmux { 1773 pins = "gpio55", "gpio56"; 1774 function = "qup10"; 1775 }; 1776 }; 1777 1778 qup_i2c11_default: qup-i2c11-default { 1779 pinmux { 1780 pins = "gpio31", "gpio32"; 1781 function = "qup11"; 1782 }; 1783 }; 1784 1785 qup_i2c12_default: qup-i2c12-default { 1786 pinmux { 1787 pins = "gpio49", "gpio50"; 1788 function = "qup12"; 1789 }; 1790 }; 1791 1792 qup_i2c13_default: qup-i2c13-default { 1793 pinmux { 1794 pins = "gpio105", "gpio106"; 1795 function = "qup13"; 1796 }; 1797 }; 1798 1799 qup_i2c14_default: qup-i2c14-default { 1800 pinmux { 1801 pins = "gpio33", "gpio34"; 1802 function = "qup14"; 1803 }; 1804 }; 1805 1806 qup_i2c15_default: qup-i2c15-default { 1807 pinmux { 1808 pins = "gpio81", "gpio82"; 1809 function = "qup15"; 1810 }; 1811 }; 1812 1813 qup_spi0_default: qup-spi0-default { 1814 pinmux { 1815 pins = "gpio0", "gpio1", 1816 "gpio2", "gpio3"; 1817 function = "qup0"; 1818 }; 1819 }; 1820 1821 qup_spi1_default: qup-spi1-default { 1822 pinmux { 1823 pins = "gpio17", "gpio18", 1824 "gpio19", "gpio20"; 1825 function = "qup1"; 1826 }; 1827 }; 1828 1829 qup_spi2_default: qup-spi2-default { 1830 pinmux { 1831 pins = "gpio27", "gpio28", 1832 "gpio29", "gpio30"; 1833 function = "qup2"; 1834 }; 1835 }; 1836 1837 qup_spi3_default: qup-spi3-default { 1838 pinmux { 1839 pins = "gpio41", "gpio42", 1840 "gpio43", "gpio44"; 1841 function = "qup3"; 1842 }; 1843 }; 1844 1845 qup_spi4_default: qup-spi4-default { 1846 pinmux { 1847 pins = "gpio89", "gpio90", 1848 "gpio91", "gpio92"; 1849 function = "qup4"; 1850 }; 1851 }; 1852 1853 qup_spi5_default: qup-spi5-default { 1854 pinmux { 1855 pins = "gpio85", "gpio86", 1856 "gpio87", "gpio88"; 1857 function = "qup5"; 1858 }; 1859 }; 1860 1861 qup_spi6_default: qup-spi6-default { 1862 pinmux { 1863 pins = "gpio45", "gpio46", 1864 "gpio47", "gpio48"; 1865 function = "qup6"; 1866 }; 1867 }; 1868 1869 qup_spi7_default: qup-spi7-default { 1870 pinmux { 1871 pins = "gpio93", "gpio94", 1872 "gpio95", "gpio96"; 1873 function = "qup7"; 1874 }; 1875 }; 1876 1877 qup_spi8_default: qup-spi8-default { 1878 pinmux { 1879 pins = "gpio65", "gpio66", 1880 "gpio67", "gpio68"; 1881 function = "qup8"; 1882 }; 1883 }; 1884 1885 qup_spi9_default: qup-spi9-default { 1886 pinmux { 1887 pins = "gpio6", "gpio7", 1888 "gpio4", "gpio5"; 1889 function = "qup9"; 1890 }; 1891 }; 1892 1893 qup_spi10_default: qup-spi10-default { 1894 pinmux { 1895 pins = "gpio55", "gpio56", 1896 "gpio53", "gpio54"; 1897 function = "qup10"; 1898 }; 1899 }; 1900 1901 qup_spi11_default: qup-spi11-default { 1902 pinmux { 1903 pins = "gpio31", "gpio32", 1904 "gpio33", "gpio34"; 1905 function = "qup11"; 1906 }; 1907 }; 1908 1909 qup_spi12_default: qup-spi12-default { 1910 pinmux { 1911 pins = "gpio49", "gpio50", 1912 "gpio51", "gpio52"; 1913 function = "qup12"; 1914 }; 1915 }; 1916 1917 qup_spi13_default: qup-spi13-default { 1918 pinmux { 1919 pins = "gpio105", "gpio106", 1920 "gpio107", "gpio108"; 1921 function = "qup13"; 1922 }; 1923 }; 1924 1925 qup_spi14_default: qup-spi14-default { 1926 pinmux { 1927 pins = "gpio33", "gpio34", 1928 "gpio31", "gpio32"; 1929 function = "qup14"; 1930 }; 1931 }; 1932 1933 qup_spi15_default: qup-spi15-default { 1934 pinmux { 1935 pins = "gpio81", "gpio82", 1936 "gpio83", "gpio84"; 1937 function = "qup15"; 1938 }; 1939 }; 1940 1941 qup_uart0_default: qup-uart0-default { 1942 pinmux { 1943 pins = "gpio2", "gpio3"; 1944 function = "qup0"; 1945 }; 1946 }; 1947 1948 qup_uart1_default: qup-uart1-default { 1949 pinmux { 1950 pins = "gpio19", "gpio20"; 1951 function = "qup1"; 1952 }; 1953 }; 1954 1955 qup_uart2_default: qup-uart2-default { 1956 pinmux { 1957 pins = "gpio29", "gpio30"; 1958 function = "qup2"; 1959 }; 1960 }; 1961 1962 qup_uart3_default: qup-uart3-default { 1963 pinmux { 1964 pins = "gpio43", "gpio44"; 1965 function = "qup3"; 1966 }; 1967 }; 1968 1969 qup_uart4_default: qup-uart4-default { 1970 pinmux { 1971 pins = "gpio91", "gpio92"; 1972 function = "qup4"; 1973 }; 1974 }; 1975 1976 qup_uart5_default: qup-uart5-default { 1977 pinmux { 1978 pins = "gpio87", "gpio88"; 1979 function = "qup5"; 1980 }; 1981 }; 1982 1983 qup_uart6_default: qup-uart6-default { 1984 pinmux { 1985 pins = "gpio47", "gpio48"; 1986 function = "qup6"; 1987 }; 1988 }; 1989 1990 qup_uart7_default: qup-uart7-default { 1991 pinmux { 1992 pins = "gpio95", "gpio96"; 1993 function = "qup7"; 1994 }; 1995 }; 1996 1997 qup_uart8_default: qup-uart8-default { 1998 pinmux { 1999 pins = "gpio67", "gpio68"; 2000 function = "qup8"; 2001 }; 2002 }; 2003 2004 qup_uart9_default: qup-uart9-default { 2005 pinmux { 2006 pins = "gpio4", "gpio5"; 2007 function = "qup9"; 2008 }; 2009 }; 2010 2011 qup_uart10_default: qup-uart10-default { 2012 pinmux { 2013 pins = "gpio53", "gpio54"; 2014 function = "qup10"; 2015 }; 2016 }; 2017 2018 qup_uart11_default: qup-uart11-default { 2019 pinmux { 2020 pins = "gpio33", "gpio34"; 2021 function = "qup11"; 2022 }; 2023 }; 2024 2025 qup_uart12_default: qup-uart12-default { 2026 pinmux { 2027 pins = "gpio51", "gpio52"; 2028 function = "qup12"; 2029 }; 2030 }; 2031 2032 qup_uart13_default: qup-uart13-default { 2033 pinmux { 2034 pins = "gpio107", "gpio108"; 2035 function = "qup13"; 2036 }; 2037 }; 2038 2039 qup_uart14_default: qup-uart14-default { 2040 pinmux { 2041 pins = "gpio31", "gpio32"; 2042 function = "qup14"; 2043 }; 2044 }; 2045 2046 qup_uart15_default: qup-uart15-default { 2047 pinmux { 2048 pins = "gpio83", "gpio84"; 2049 function = "qup15"; 2050 }; 2051 }; 2052 }; 2053 2054 mss_pil: remoteproc@4080000 { 2055 compatible = "qcom,sdm845-mss-pil"; 2056 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2057 reg-names = "qdsp6", "rmb"; 2058 2059 interrupts-extended = 2060 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2061 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2062 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2063 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2064 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2065 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2066 interrupt-names = "wdog", "fatal", "ready", 2067 "handover", "stop-ack", 2068 "shutdown-ack"; 2069 2070 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2071 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2072 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2073 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2074 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2075 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2076 <&gcc GCC_PRNG_AHB_CLK>, 2077 <&rpmhcc RPMH_CXO_CLK>; 2078 clock-names = "iface", "bus", "mem", "gpll0_mss", 2079 "snoc_axi", "mnoc_axi", "prng", "xo"; 2080 2081 qcom,smem-states = <&modem_smp2p_out 0>; 2082 qcom,smem-state-names = "stop"; 2083 2084 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2085 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2086 reset-names = "mss_restart", "pdc_reset"; 2087 2088 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2089 2090 power-domains = <&aoss_qmp 2>, 2091 <&rpmhpd SDM845_CX>, 2092 <&rpmhpd SDM845_MX>, 2093 <&rpmhpd SDM845_MSS>; 2094 power-domain-names = "load_state", "cx", "mx", "mss"; 2095 2096 mba { 2097 memory-region = <&mba_region>; 2098 }; 2099 2100 mpss { 2101 memory-region = <&mpss_region>; 2102 }; 2103 2104 glink-edge { 2105 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2106 label = "modem"; 2107 qcom,remote-pid = <1>; 2108 mboxes = <&apss_shared 12>; 2109 }; 2110 }; 2111 2112 gpucc: clock-controller@5090000 { 2113 compatible = "qcom,sdm845-gpucc"; 2114 reg = <0 0x05090000 0 0x9000>; 2115 #clock-cells = <1>; 2116 #reset-cells = <1>; 2117 #power-domain-cells = <1>; 2118 clocks = <&rpmhcc RPMH_CXO_CLK>; 2119 clock-names = "xo"; 2120 }; 2121 2122 stm@6002000 { 2123 compatible = "arm,coresight-stm", "arm,primecell"; 2124 reg = <0 0x06002000 0 0x1000>, 2125 <0 0x16280000 0 0x180000>; 2126 reg-names = "stm-base", "stm-stimulus-base"; 2127 2128 clocks = <&aoss_qmp>; 2129 clock-names = "apb_pclk"; 2130 2131 out-ports { 2132 port { 2133 stm_out: endpoint { 2134 remote-endpoint = 2135 <&funnel0_in7>; 2136 }; 2137 }; 2138 }; 2139 }; 2140 2141 funnel@6041000 { 2142 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2143 reg = <0 0x06041000 0 0x1000>; 2144 2145 clocks = <&aoss_qmp>; 2146 clock-names = "apb_pclk"; 2147 2148 out-ports { 2149 port { 2150 funnel0_out: endpoint { 2151 remote-endpoint = 2152 <&merge_funnel_in0>; 2153 }; 2154 }; 2155 }; 2156 2157 in-ports { 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 2161 port@7 { 2162 reg = <7>; 2163 funnel0_in7: endpoint { 2164 remote-endpoint = <&stm_out>; 2165 }; 2166 }; 2167 }; 2168 }; 2169 2170 funnel@6043000 { 2171 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2172 reg = <0 0x06043000 0 0x1000>; 2173 2174 clocks = <&aoss_qmp>; 2175 clock-names = "apb_pclk"; 2176 2177 out-ports { 2178 port { 2179 funnel2_out: endpoint { 2180 remote-endpoint = 2181 <&merge_funnel_in2>; 2182 }; 2183 }; 2184 }; 2185 2186 in-ports { 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 2190 port@5 { 2191 reg = <5>; 2192 funnel2_in5: endpoint { 2193 remote-endpoint = 2194 <&apss_merge_funnel_out>; 2195 }; 2196 }; 2197 }; 2198 }; 2199 2200 funnel@6045000 { 2201 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2202 reg = <0 0x06045000 0 0x1000>; 2203 2204 clocks = <&aoss_qmp>; 2205 clock-names = "apb_pclk"; 2206 2207 out-ports { 2208 port { 2209 merge_funnel_out: endpoint { 2210 remote-endpoint = <&etf_in>; 2211 }; 2212 }; 2213 }; 2214 2215 in-ports { 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 2219 port@0 { 2220 reg = <0>; 2221 merge_funnel_in0: endpoint { 2222 remote-endpoint = 2223 <&funnel0_out>; 2224 }; 2225 }; 2226 2227 port@2 { 2228 reg = <2>; 2229 merge_funnel_in2: endpoint { 2230 remote-endpoint = 2231 <&funnel2_out>; 2232 }; 2233 }; 2234 }; 2235 }; 2236 2237 replicator@6046000 { 2238 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2239 reg = <0 0x06046000 0 0x1000>; 2240 2241 clocks = <&aoss_qmp>; 2242 clock-names = "apb_pclk"; 2243 2244 out-ports { 2245 port { 2246 replicator_out: endpoint { 2247 remote-endpoint = <&etr_in>; 2248 }; 2249 }; 2250 }; 2251 2252 in-ports { 2253 port { 2254 replicator_in: endpoint { 2255 remote-endpoint = <&etf_out>; 2256 }; 2257 }; 2258 }; 2259 }; 2260 2261 etf@6047000 { 2262 compatible = "arm,coresight-tmc", "arm,primecell"; 2263 reg = <0 0x06047000 0 0x1000>; 2264 2265 clocks = <&aoss_qmp>; 2266 clock-names = "apb_pclk"; 2267 2268 out-ports { 2269 port { 2270 etf_out: endpoint { 2271 remote-endpoint = 2272 <&replicator_in>; 2273 }; 2274 }; 2275 }; 2276 2277 in-ports { 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 2281 port@1 { 2282 reg = <1>; 2283 etf_in: endpoint { 2284 remote-endpoint = 2285 <&merge_funnel_out>; 2286 }; 2287 }; 2288 }; 2289 }; 2290 2291 etr@6048000 { 2292 compatible = "arm,coresight-tmc", "arm,primecell"; 2293 reg = <0 0x06048000 0 0x1000>; 2294 2295 clocks = <&aoss_qmp>; 2296 clock-names = "apb_pclk"; 2297 arm,scatter-gather; 2298 2299 in-ports { 2300 port { 2301 etr_in: endpoint { 2302 remote-endpoint = 2303 <&replicator_out>; 2304 }; 2305 }; 2306 }; 2307 }; 2308 2309 etm@7040000 { 2310 compatible = "arm,coresight-etm4x", "arm,primecell"; 2311 reg = <0 0x07040000 0 0x1000>; 2312 2313 cpu = <&CPU0>; 2314 2315 clocks = <&aoss_qmp>; 2316 clock-names = "apb_pclk"; 2317 2318 out-ports { 2319 port { 2320 etm0_out: endpoint { 2321 remote-endpoint = 2322 <&apss_funnel_in0>; 2323 }; 2324 }; 2325 }; 2326 }; 2327 2328 etm@7140000 { 2329 compatible = "arm,coresight-etm4x", "arm,primecell"; 2330 reg = <0 0x07140000 0 0x1000>; 2331 2332 cpu = <&CPU1>; 2333 2334 clocks = <&aoss_qmp>; 2335 clock-names = "apb_pclk"; 2336 2337 out-ports { 2338 port { 2339 etm1_out: endpoint { 2340 remote-endpoint = 2341 <&apss_funnel_in1>; 2342 }; 2343 }; 2344 }; 2345 }; 2346 2347 etm@7240000 { 2348 compatible = "arm,coresight-etm4x", "arm,primecell"; 2349 reg = <0 0x07240000 0 0x1000>; 2350 2351 cpu = <&CPU2>; 2352 2353 clocks = <&aoss_qmp>; 2354 clock-names = "apb_pclk"; 2355 2356 out-ports { 2357 port { 2358 etm2_out: endpoint { 2359 remote-endpoint = 2360 <&apss_funnel_in2>; 2361 }; 2362 }; 2363 }; 2364 }; 2365 2366 etm@7340000 { 2367 compatible = "arm,coresight-etm4x", "arm,primecell"; 2368 reg = <0 0x07340000 0 0x1000>; 2369 2370 cpu = <&CPU3>; 2371 2372 clocks = <&aoss_qmp>; 2373 clock-names = "apb_pclk"; 2374 2375 out-ports { 2376 port { 2377 etm3_out: endpoint { 2378 remote-endpoint = 2379 <&apss_funnel_in3>; 2380 }; 2381 }; 2382 }; 2383 }; 2384 2385 etm@7440000 { 2386 compatible = "arm,coresight-etm4x", "arm,primecell"; 2387 reg = <0 0x07440000 0 0x1000>; 2388 2389 cpu = <&CPU4>; 2390 2391 clocks = <&aoss_qmp>; 2392 clock-names = "apb_pclk"; 2393 2394 out-ports { 2395 port { 2396 etm4_out: endpoint { 2397 remote-endpoint = 2398 <&apss_funnel_in4>; 2399 }; 2400 }; 2401 }; 2402 }; 2403 2404 etm@7540000 { 2405 compatible = "arm,coresight-etm4x", "arm,primecell"; 2406 reg = <0 0x07540000 0 0x1000>; 2407 2408 cpu = <&CPU5>; 2409 2410 clocks = <&aoss_qmp>; 2411 clock-names = "apb_pclk"; 2412 2413 out-ports { 2414 port { 2415 etm5_out: endpoint { 2416 remote-endpoint = 2417 <&apss_funnel_in5>; 2418 }; 2419 }; 2420 }; 2421 }; 2422 2423 etm@7640000 { 2424 compatible = "arm,coresight-etm4x", "arm,primecell"; 2425 reg = <0 0x07640000 0 0x1000>; 2426 2427 cpu = <&CPU6>; 2428 2429 clocks = <&aoss_qmp>; 2430 clock-names = "apb_pclk"; 2431 2432 out-ports { 2433 port { 2434 etm6_out: endpoint { 2435 remote-endpoint = 2436 <&apss_funnel_in6>; 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 etm@7740000 { 2443 compatible = "arm,coresight-etm4x", "arm,primecell"; 2444 reg = <0 0x07740000 0 0x1000>; 2445 2446 cpu = <&CPU7>; 2447 2448 clocks = <&aoss_qmp>; 2449 clock-names = "apb_pclk"; 2450 2451 out-ports { 2452 port { 2453 etm7_out: endpoint { 2454 remote-endpoint = 2455 <&apss_funnel_in7>; 2456 }; 2457 }; 2458 }; 2459 }; 2460 2461 funnel@7800000 { /* APSS Funnel */ 2462 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2463 reg = <0 0x07800000 0 0x1000>; 2464 2465 clocks = <&aoss_qmp>; 2466 clock-names = "apb_pclk"; 2467 2468 out-ports { 2469 port { 2470 apss_funnel_out: endpoint { 2471 remote-endpoint = 2472 <&apss_merge_funnel_in>; 2473 }; 2474 }; 2475 }; 2476 2477 in-ports { 2478 #address-cells = <1>; 2479 #size-cells = <0>; 2480 2481 port@0 { 2482 reg = <0>; 2483 apss_funnel_in0: endpoint { 2484 remote-endpoint = 2485 <&etm0_out>; 2486 }; 2487 }; 2488 2489 port@1 { 2490 reg = <1>; 2491 apss_funnel_in1: endpoint { 2492 remote-endpoint = 2493 <&etm1_out>; 2494 }; 2495 }; 2496 2497 port@2 { 2498 reg = <2>; 2499 apss_funnel_in2: endpoint { 2500 remote-endpoint = 2501 <&etm2_out>; 2502 }; 2503 }; 2504 2505 port@3 { 2506 reg = <3>; 2507 apss_funnel_in3: endpoint { 2508 remote-endpoint = 2509 <&etm3_out>; 2510 }; 2511 }; 2512 2513 port@4 { 2514 reg = <4>; 2515 apss_funnel_in4: endpoint { 2516 remote-endpoint = 2517 <&etm4_out>; 2518 }; 2519 }; 2520 2521 port@5 { 2522 reg = <5>; 2523 apss_funnel_in5: endpoint { 2524 remote-endpoint = 2525 <&etm5_out>; 2526 }; 2527 }; 2528 2529 port@6 { 2530 reg = <6>; 2531 apss_funnel_in6: endpoint { 2532 remote-endpoint = 2533 <&etm6_out>; 2534 }; 2535 }; 2536 2537 port@7 { 2538 reg = <7>; 2539 apss_funnel_in7: endpoint { 2540 remote-endpoint = 2541 <&etm7_out>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 funnel@7810000 { 2548 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2549 reg = <0 0x07810000 0 0x1000>; 2550 2551 clocks = <&aoss_qmp>; 2552 clock-names = "apb_pclk"; 2553 2554 out-ports { 2555 port { 2556 apss_merge_funnel_out: endpoint { 2557 remote-endpoint = 2558 <&funnel2_in5>; 2559 }; 2560 }; 2561 }; 2562 2563 in-ports { 2564 port { 2565 apss_merge_funnel_in: endpoint { 2566 remote-endpoint = 2567 <&apss_funnel_out>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 sdhc_2: sdhci@8804000 { 2574 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2575 reg = <0 0x08804000 0 0x1000>; 2576 2577 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2579 interrupt-names = "hc_irq", "pwr_irq"; 2580 2581 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2582 <&gcc GCC_SDCC2_APPS_CLK>; 2583 clock-names = "iface", "core"; 2584 iommus = <&apps_smmu 0xa0 0xf>; 2585 2586 status = "disabled"; 2587 }; 2588 2589 qspi: spi@88df000 { 2590 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2591 reg = <0 0x088df000 0 0x600>; 2592 #address-cells = <1>; 2593 #size-cells = <0>; 2594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2596 <&gcc GCC_QSPI_CORE_CLK>; 2597 clock-names = "iface", "core"; 2598 status = "disabled"; 2599 }; 2600 2601 usb_1_hsphy: phy@88e2000 { 2602 compatible = "qcom,sdm845-qusb2-phy"; 2603 reg = <0 0x088e2000 0 0x400>; 2604 status = "disabled"; 2605 #phy-cells = <0>; 2606 2607 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2608 <&rpmhcc RPMH_CXO_CLK>; 2609 clock-names = "cfg_ahb", "ref"; 2610 2611 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2612 2613 nvmem-cells = <&qusb2p_hstx_trim>; 2614 }; 2615 2616 usb_2_hsphy: phy@88e3000 { 2617 compatible = "qcom,sdm845-qusb2-phy"; 2618 reg = <0 0x088e3000 0 0x400>; 2619 status = "disabled"; 2620 #phy-cells = <0>; 2621 2622 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2623 <&rpmhcc RPMH_CXO_CLK>; 2624 clock-names = "cfg_ahb", "ref"; 2625 2626 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2627 2628 nvmem-cells = <&qusb2s_hstx_trim>; 2629 }; 2630 2631 usb_1_qmpphy: phy@88e9000 { 2632 compatible = "qcom,sdm845-qmp-usb3-phy"; 2633 reg = <0 0x088e9000 0 0x18c>, 2634 <0 0x088e8000 0 0x10>; 2635 reg-names = "reg-base", "dp_com"; 2636 status = "disabled"; 2637 #clock-cells = <1>; 2638 #address-cells = <2>; 2639 #size-cells = <2>; 2640 ranges; 2641 2642 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2643 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2644 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2645 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2646 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2647 2648 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2649 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2650 reset-names = "phy", "common"; 2651 2652 usb_1_ssphy: lanes@88e9200 { 2653 reg = <0 0x088e9200 0 0x128>, 2654 <0 0x088e9400 0 0x200>, 2655 <0 0x088e9c00 0 0x218>, 2656 <0 0x088e9600 0 0x128>, 2657 <0 0x088e9800 0 0x200>, 2658 <0 0x088e9a00 0 0x100>; 2659 #phy-cells = <0>; 2660 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2661 clock-names = "pipe0"; 2662 clock-output-names = "usb3_phy_pipe_clk_src"; 2663 }; 2664 }; 2665 2666 usb_2_qmpphy: phy@88eb000 { 2667 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 2668 reg = <0 0x088eb000 0 0x18c>; 2669 status = "disabled"; 2670 #clock-cells = <1>; 2671 #address-cells = <2>; 2672 #size-cells = <2>; 2673 ranges; 2674 2675 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2676 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2677 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2678 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2679 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2680 2681 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2682 <&gcc GCC_USB3_PHY_SEC_BCR>; 2683 reset-names = "phy", "common"; 2684 2685 usb_2_ssphy: lane@88eb200 { 2686 reg = <0 0x088eb200 0 0x128>, 2687 <0 0x088eb400 0 0x1fc>, 2688 <0 0x088eb800 0 0x218>, 2689 <0 0x088eb600 0 0x70>; 2690 #phy-cells = <0>; 2691 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2692 clock-names = "pipe0"; 2693 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2694 }; 2695 }; 2696 2697 usb_1: usb@a6f8800 { 2698 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2699 reg = <0 0x0a6f8800 0 0x400>; 2700 status = "disabled"; 2701 #address-cells = <2>; 2702 #size-cells = <2>; 2703 ranges; 2704 dma-ranges; 2705 2706 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2707 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2708 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2709 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2710 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2711 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2712 "sleep"; 2713 2714 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2715 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2716 assigned-clock-rates = <19200000>, <150000000>; 2717 2718 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2722 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2723 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2724 2725 power-domains = <&gcc USB30_PRIM_GDSC>; 2726 2727 resets = <&gcc GCC_USB30_PRIM_BCR>; 2728 2729 usb_1_dwc3: dwc3@a600000 { 2730 compatible = "snps,dwc3"; 2731 reg = <0 0x0a600000 0 0xcd00>; 2732 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2733 iommus = <&apps_smmu 0x740 0>; 2734 snps,dis_u2_susphy_quirk; 2735 snps,dis_enblslpm_quirk; 2736 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2737 phy-names = "usb2-phy", "usb3-phy"; 2738 }; 2739 }; 2740 2741 usb_2: usb@a8f8800 { 2742 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2743 reg = <0 0x0a8f8800 0 0x400>; 2744 status = "disabled"; 2745 #address-cells = <2>; 2746 #size-cells = <2>; 2747 ranges; 2748 dma-ranges; 2749 2750 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2751 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2752 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2753 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2754 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2755 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2756 "sleep"; 2757 2758 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2759 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2760 assigned-clock-rates = <19200000>, <150000000>; 2761 2762 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 2766 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2767 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2768 2769 power-domains = <&gcc USB30_SEC_GDSC>; 2770 2771 resets = <&gcc GCC_USB30_SEC_BCR>; 2772 2773 usb_2_dwc3: dwc3@a800000 { 2774 compatible = "snps,dwc3"; 2775 reg = <0 0x0a800000 0 0xcd00>; 2776 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2777 iommus = <&apps_smmu 0x760 0>; 2778 snps,dis_u2_susphy_quirk; 2779 snps,dis_enblslpm_quirk; 2780 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2781 phy-names = "usb2-phy", "usb3-phy"; 2782 }; 2783 }; 2784 2785 video-codec@aa00000 { 2786 compatible = "qcom,sdm845-venus"; 2787 reg = <0 0x0aa00000 0 0xff000>; 2788 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2789 power-domains = <&videocc VENUS_GDSC>; 2790 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2791 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2792 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; 2793 clock-names = "core", "iface", "bus"; 2794 iommus = <&apps_smmu 0x10a0 0x8>, 2795 <&apps_smmu 0x10b0 0x0>; 2796 memory-region = <&venus_mem>; 2797 2798 video-core0 { 2799 compatible = "venus-decoder"; 2800 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2801 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2802 clock-names = "core", "bus"; 2803 power-domains = <&videocc VCODEC0_GDSC>; 2804 }; 2805 2806 video-core1 { 2807 compatible = "venus-encoder"; 2808 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 2809 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 2810 clock-names = "core", "bus"; 2811 power-domains = <&videocc VCODEC1_GDSC>; 2812 }; 2813 }; 2814 2815 videocc: clock-controller@ab00000 { 2816 compatible = "qcom,sdm845-videocc"; 2817 reg = <0 0x0ab00000 0 0x10000>; 2818 #clock-cells = <1>; 2819 #power-domain-cells = <1>; 2820 #reset-cells = <1>; 2821 }; 2822 2823 mdss: mdss@ae00000 { 2824 compatible = "qcom,sdm845-mdss"; 2825 reg = <0 0x0ae00000 0 0x1000>; 2826 reg-names = "mdss"; 2827 2828 power-domains = <&dispcc MDSS_GDSC>; 2829 2830 clocks = <&gcc GCC_DISP_AHB_CLK>, 2831 <&gcc GCC_DISP_AXI_CLK>, 2832 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2833 clock-names = "iface", "bus", "core"; 2834 2835 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2836 assigned-clock-rates = <300000000>; 2837 2838 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2839 interrupt-controller; 2840 #interrupt-cells = <1>; 2841 2842 iommus = <&apps_smmu 0x880 0x8>, 2843 <&apps_smmu 0xc80 0x8>; 2844 2845 status = "disabled"; 2846 2847 #address-cells = <2>; 2848 #size-cells = <2>; 2849 ranges; 2850 2851 mdss_mdp: mdp@ae01000 { 2852 compatible = "qcom,sdm845-dpu"; 2853 reg = <0 0x0ae01000 0 0x8f000>, 2854 <0 0x0aeb0000 0 0x2008>; 2855 reg-names = "mdp", "vbif"; 2856 2857 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2858 <&dispcc DISP_CC_MDSS_AXI_CLK>, 2859 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2860 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2861 clock-names = "iface", "bus", "core", "vsync"; 2862 2863 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2864 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2865 assigned-clock-rates = <300000000>, 2866 <19200000>; 2867 2868 interrupt-parent = <&mdss>; 2869 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2870 2871 status = "disabled"; 2872 2873 ports { 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 2877 port@0 { 2878 reg = <0>; 2879 dpu_intf1_out: endpoint { 2880 remote-endpoint = <&dsi0_in>; 2881 }; 2882 }; 2883 2884 port@1 { 2885 reg = <1>; 2886 dpu_intf2_out: endpoint { 2887 remote-endpoint = <&dsi1_in>; 2888 }; 2889 }; 2890 }; 2891 }; 2892 2893 dsi0: dsi@ae94000 { 2894 compatible = "qcom,mdss-dsi-ctrl"; 2895 reg = <0 0x0ae94000 0 0x400>; 2896 reg-names = "dsi_ctrl"; 2897 2898 interrupt-parent = <&mdss>; 2899 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2900 2901 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2902 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2903 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2904 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2905 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2906 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2907 clock-names = "byte", 2908 "byte_intf", 2909 "pixel", 2910 "core", 2911 "iface", 2912 "bus"; 2913 2914 phys = <&dsi0_phy>; 2915 phy-names = "dsi"; 2916 2917 status = "disabled"; 2918 2919 ports { 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 2923 port@0 { 2924 reg = <0>; 2925 dsi0_in: endpoint { 2926 remote-endpoint = <&dpu_intf1_out>; 2927 }; 2928 }; 2929 2930 port@1 { 2931 reg = <1>; 2932 dsi0_out: endpoint { 2933 }; 2934 }; 2935 }; 2936 }; 2937 2938 dsi0_phy: dsi-phy@ae94400 { 2939 compatible = "qcom,dsi-phy-10nm"; 2940 reg = <0 0x0ae94400 0 0x200>, 2941 <0 0x0ae94600 0 0x280>, 2942 <0 0x0ae94a00 0 0x1e0>; 2943 reg-names = "dsi_phy", 2944 "dsi_phy_lane", 2945 "dsi_pll"; 2946 2947 #clock-cells = <1>; 2948 #phy-cells = <0>; 2949 2950 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2951 <&rpmhcc RPMH_CXO_CLK>; 2952 clock-names = "iface", "ref"; 2953 2954 status = "disabled"; 2955 }; 2956 2957 dsi1: dsi@ae96000 { 2958 compatible = "qcom,mdss-dsi-ctrl"; 2959 reg = <0 0x0ae96000 0 0x400>; 2960 reg-names = "dsi_ctrl"; 2961 2962 interrupt-parent = <&mdss>; 2963 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2964 2965 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2966 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2967 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2968 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2969 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2970 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2971 clock-names = "byte", 2972 "byte_intf", 2973 "pixel", 2974 "core", 2975 "iface", 2976 "bus"; 2977 2978 phys = <&dsi1_phy>; 2979 phy-names = "dsi"; 2980 2981 status = "disabled"; 2982 2983 ports { 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 port@0 { 2988 reg = <0>; 2989 dsi1_in: endpoint { 2990 remote-endpoint = <&dpu_intf2_out>; 2991 }; 2992 }; 2993 2994 port@1 { 2995 reg = <1>; 2996 dsi1_out: endpoint { 2997 }; 2998 }; 2999 }; 3000 }; 3001 3002 dsi1_phy: dsi-phy@ae96400 { 3003 compatible = "qcom,dsi-phy-10nm"; 3004 reg = <0 0x0ae96400 0 0x200>, 3005 <0 0x0ae96600 0 0x280>, 3006 <0 0x0ae96a00 0 0x10e>; 3007 reg-names = "dsi_phy", 3008 "dsi_phy_lane", 3009 "dsi_pll"; 3010 3011 #clock-cells = <1>; 3012 #phy-cells = <0>; 3013 3014 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3015 <&rpmhcc RPMH_CXO_CLK>; 3016 clock-names = "iface", "ref"; 3017 3018 status = "disabled"; 3019 }; 3020 }; 3021 3022 gpu@5000000 { 3023 compatible = "qcom,adreno-630.2", "qcom,adreno"; 3024 #stream-id-cells = <16>; 3025 3026 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 3027 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 3028 3029 /* 3030 * Look ma, no clocks! The GPU clocks and power are 3031 * controlled entirely by the GMU 3032 */ 3033 3034 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3035 3036 iommus = <&adreno_smmu 0>; 3037 3038 operating-points-v2 = <&gpu_opp_table>; 3039 3040 qcom,gmu = <&gmu>; 3041 3042 zap_shader: zap-shader { 3043 memory-region = <&gpu_mem>; 3044 }; 3045 3046 gpu_opp_table: opp-table { 3047 compatible = "operating-points-v2"; 3048 3049 opp-710000000 { 3050 opp-hz = /bits/ 64 <710000000>; 3051 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3052 }; 3053 3054 opp-675000000 { 3055 opp-hz = /bits/ 64 <675000000>; 3056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3057 }; 3058 3059 opp-596000000 { 3060 opp-hz = /bits/ 64 <596000000>; 3061 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3062 }; 3063 3064 opp-520000000 { 3065 opp-hz = /bits/ 64 <520000000>; 3066 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3067 }; 3068 3069 opp-414000000 { 3070 opp-hz = /bits/ 64 <414000000>; 3071 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3072 }; 3073 3074 opp-342000000 { 3075 opp-hz = /bits/ 64 <342000000>; 3076 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3077 }; 3078 3079 opp-257000000 { 3080 opp-hz = /bits/ 64 <257000000>; 3081 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3082 }; 3083 }; 3084 }; 3085 3086 adreno_smmu: iommu@5040000 { 3087 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 3088 reg = <0 0x5040000 0 0x10000>; 3089 #iommu-cells = <1>; 3090 #global-interrupts = <2>; 3091 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 3094 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 3095 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 3096 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 3097 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 3098 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 3099 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 3100 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 3101 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3102 <&gcc GCC_GPU_CFG_AHB_CLK>; 3103 clock-names = "bus", "iface"; 3104 3105 power-domains = <&gpucc GPU_CX_GDSC>; 3106 }; 3107 3108 gmu: gmu@506a000 { 3109 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 3110 3111 reg = <0 0x506a000 0 0x30000>, 3112 <0 0xb280000 0 0x10000>, 3113 <0 0xb480000 0 0x10000>; 3114 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 3115 3116 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3118 interrupt-names = "hfi", "gmu"; 3119 3120 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3121 <&gpucc GPU_CC_CXO_CLK>, 3122 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3123 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3124 clock-names = "gmu", "cxo", "axi", "memnoc"; 3125 3126 power-domains = <&gpucc GPU_CX_GDSC>, 3127 <&gpucc GPU_GX_GDSC>; 3128 power-domain-names = "cx", "gx"; 3129 3130 iommus = <&adreno_smmu 5>; 3131 3132 operating-points-v2 = <&gmu_opp_table>; 3133 3134 gmu_opp_table: opp-table { 3135 compatible = "operating-points-v2"; 3136 3137 opp-400000000 { 3138 opp-hz = /bits/ 64 <400000000>; 3139 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3140 }; 3141 3142 opp-200000000 { 3143 opp-hz = /bits/ 64 <200000000>; 3144 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3145 }; 3146 }; 3147 }; 3148 3149 dispcc: clock-controller@af00000 { 3150 compatible = "qcom,sdm845-dispcc"; 3151 reg = <0 0x0af00000 0 0x10000>; 3152 clocks = <&gcc GCC_DISP_GPLL0_CLK_SRC>; 3153 #clock-cells = <1>; 3154 #reset-cells = <1>; 3155 #power-domain-cells = <1>; 3156 }; 3157 3158 pdc_reset: reset-controller@b2e0000 { 3159 compatible = "qcom,sdm845-pdc-global"; 3160 reg = <0 0x0b2e0000 0 0x20000>; 3161 #reset-cells = <1>; 3162 }; 3163 3164 tsens0: thermal-sensor@c263000 { 3165 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3166 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3167 <0 0x0c222000 0 0x1ff>; /* SROT */ 3168 #qcom,sensors = <13>; 3169 #thermal-sensor-cells = <1>; 3170 }; 3171 3172 tsens1: thermal-sensor@c265000 { 3173 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3174 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3175 <0 0x0c223000 0 0x1ff>; /* SROT */ 3176 #qcom,sensors = <8>; 3177 #thermal-sensor-cells = <1>; 3178 }; 3179 3180 aoss_reset: reset-controller@c2a0000 { 3181 compatible = "qcom,sdm845-aoss-cc"; 3182 reg = <0 0x0c2a0000 0 0x31000>; 3183 #reset-cells = <1>; 3184 }; 3185 3186 aoss_qmp: qmp@c300000 { 3187 compatible = "qcom,sdm845-aoss-qmp"; 3188 reg = <0 0x0c300000 0 0x100000>; 3189 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3190 mboxes = <&apss_shared 0>; 3191 3192 #clock-cells = <0>; 3193 #power-domain-cells = <1>; 3194 3195 cx_cdev: cx { 3196 #cooling-cells = <2>; 3197 }; 3198 3199 ebi_cdev: ebi { 3200 #cooling-cells = <2>; 3201 }; 3202 }; 3203 3204 spmi_bus: spmi@c440000 { 3205 compatible = "qcom,spmi-pmic-arb"; 3206 reg = <0 0x0c440000 0 0x1100>, 3207 <0 0x0c600000 0 0x2000000>, 3208 <0 0x0e600000 0 0x100000>, 3209 <0 0x0e700000 0 0xa0000>, 3210 <0 0x0c40a000 0 0x26000>; 3211 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3212 interrupt-names = "periph_irq"; 3213 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3214 qcom,ee = <0>; 3215 qcom,channel = <0>; 3216 #address-cells = <2>; 3217 #size-cells = <0>; 3218 interrupt-controller; 3219 #interrupt-cells = <4>; 3220 cell-index = <0>; 3221 }; 3222 3223 apps_smmu: iommu@15000000 { 3224 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3225 reg = <0 0x15000000 0 0x80000>; 3226 #iommu-cells = <2>; 3227 qcom,smmu-500-fw-impl-safe-errata; 3228 #global-interrupts = <1>; 3229 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3294 }; 3295 3296 lpasscc: clock-controller@17014000 { 3297 compatible = "qcom,sdm845-lpasscc"; 3298 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3299 reg-names = "cc", "qdsp6ss"; 3300 #clock-cells = <1>; 3301 status = "disabled"; 3302 }; 3303 3304 apss_shared: mailbox@17990000 { 3305 compatible = "qcom,sdm845-apss-shared"; 3306 reg = <0 0x17990000 0 0x1000>; 3307 #mbox-cells = <1>; 3308 }; 3309 3310 apps_rsc: rsc@179c0000 { 3311 label = "apps_rsc"; 3312 compatible = "qcom,rpmh-rsc"; 3313 reg = <0 0x179c0000 0 0x10000>, 3314 <0 0x179d0000 0 0x10000>, 3315 <0 0x179e0000 0 0x10000>; 3316 reg-names = "drv-0", "drv-1", "drv-2"; 3317 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3320 qcom,tcs-offset = <0xd00>; 3321 qcom,drv-id = <2>; 3322 qcom,tcs-config = <ACTIVE_TCS 2>, 3323 <SLEEP_TCS 3>, 3324 <WAKE_TCS 3>, 3325 <CONTROL_TCS 1>; 3326 3327 rpmhcc: clock-controller { 3328 compatible = "qcom,sdm845-rpmh-clk"; 3329 #clock-cells = <1>; 3330 clock-names = "xo"; 3331 clocks = <&xo_board>; 3332 }; 3333 3334 rpmhpd: power-controller { 3335 compatible = "qcom,sdm845-rpmhpd"; 3336 #power-domain-cells = <1>; 3337 operating-points-v2 = <&rpmhpd_opp_table>; 3338 3339 rpmhpd_opp_table: opp-table { 3340 compatible = "operating-points-v2"; 3341 3342 rpmhpd_opp_ret: opp1 { 3343 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3344 }; 3345 3346 rpmhpd_opp_min_svs: opp2 { 3347 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3348 }; 3349 3350 rpmhpd_opp_low_svs: opp3 { 3351 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3352 }; 3353 3354 rpmhpd_opp_svs: opp4 { 3355 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3356 }; 3357 3358 rpmhpd_opp_svs_l1: opp5 { 3359 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3360 }; 3361 3362 rpmhpd_opp_nom: opp6 { 3363 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3364 }; 3365 3366 rpmhpd_opp_nom_l1: opp7 { 3367 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3368 }; 3369 3370 rpmhpd_opp_nom_l2: opp8 { 3371 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3372 }; 3373 3374 rpmhpd_opp_turbo: opp9 { 3375 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3376 }; 3377 3378 rpmhpd_opp_turbo_l1: opp10 { 3379 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3380 }; 3381 }; 3382 }; 3383 3384 rsc_hlos: interconnect { 3385 compatible = "qcom,sdm845-rsc-hlos"; 3386 #interconnect-cells = <1>; 3387 }; 3388 }; 3389 3390 intc: interrupt-controller@17a00000 { 3391 compatible = "arm,gic-v3"; 3392 #address-cells = <2>; 3393 #size-cells = <2>; 3394 ranges; 3395 #interrupt-cells = <3>; 3396 interrupt-controller; 3397 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3398 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3399 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3400 3401 gic-its@17a40000 { 3402 compatible = "arm,gic-v3-its"; 3403 msi-controller; 3404 #msi-cells = <1>; 3405 reg = <0 0x17a40000 0 0x20000>; 3406 status = "disabled"; 3407 }; 3408 }; 3409 3410 timer@17c90000 { 3411 #address-cells = <2>; 3412 #size-cells = <2>; 3413 ranges; 3414 compatible = "arm,armv7-timer-mem"; 3415 reg = <0 0x17c90000 0 0x1000>; 3416 3417 frame@17ca0000 { 3418 frame-number = <0>; 3419 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3421 reg = <0 0x17ca0000 0 0x1000>, 3422 <0 0x17cb0000 0 0x1000>; 3423 }; 3424 3425 frame@17cc0000 { 3426 frame-number = <1>; 3427 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3428 reg = <0 0x17cc0000 0 0x1000>; 3429 status = "disabled"; 3430 }; 3431 3432 frame@17cd0000 { 3433 frame-number = <2>; 3434 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3435 reg = <0 0x17cd0000 0 0x1000>; 3436 status = "disabled"; 3437 }; 3438 3439 frame@17ce0000 { 3440 frame-number = <3>; 3441 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3442 reg = <0 0x17ce0000 0 0x1000>; 3443 status = "disabled"; 3444 }; 3445 3446 frame@17cf0000 { 3447 frame-number = <4>; 3448 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3449 reg = <0 0x17cf0000 0 0x1000>; 3450 status = "disabled"; 3451 }; 3452 3453 frame@17d00000 { 3454 frame-number = <5>; 3455 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3456 reg = <0 0x17d00000 0 0x1000>; 3457 status = "disabled"; 3458 }; 3459 3460 frame@17d10000 { 3461 frame-number = <6>; 3462 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3463 reg = <0 0x17d10000 0 0x1000>; 3464 status = "disabled"; 3465 }; 3466 }; 3467 3468 cpufreq_hw: cpufreq@17d43000 { 3469 compatible = "qcom,cpufreq-hw"; 3470 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 3471 reg-names = "freq-domain0", "freq-domain1"; 3472 3473 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3474 clock-names = "xo", "alternate"; 3475 3476 #freq-domain-cells = <1>; 3477 }; 3478 3479 wifi: wifi@18800000 { 3480 compatible = "qcom,wcn3990-wifi"; 3481 status = "disabled"; 3482 reg = <0 0x18800000 0 0x800000>; 3483 reg-names = "membase"; 3484 memory-region = <&wlan_msa_mem>; 3485 clock-names = "cxo_ref_clk_pin"; 3486 clocks = <&rpmhcc RPMH_RF_CLK2>; 3487 interrupts = 3488 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3500 iommus = <&apps_smmu 0x0040 0x1>; 3501 }; 3502 }; 3503 3504 thermal-zones { 3505 cpu0-thermal { 3506 polling-delay-passive = <250>; 3507 polling-delay = <1000>; 3508 3509 thermal-sensors = <&tsens0 1>; 3510 3511 trips { 3512 cpu0_alert0: trip-point0 { 3513 temperature = <90000>; 3514 hysteresis = <2000>; 3515 type = "passive"; 3516 }; 3517 3518 cpu0_alert1: trip-point1 { 3519 temperature = <95000>; 3520 hysteresis = <2000>; 3521 type = "passive"; 3522 }; 3523 3524 cpu0_crit: cpu_crit { 3525 temperature = <110000>; 3526 hysteresis = <1000>; 3527 type = "critical"; 3528 }; 3529 }; 3530 3531 cooling-maps { 3532 map0 { 3533 trip = <&cpu0_alert0>; 3534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3538 }; 3539 map1 { 3540 trip = <&cpu0_alert1>; 3541 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3542 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3543 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3544 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3545 }; 3546 }; 3547 }; 3548 3549 cpu1-thermal { 3550 polling-delay-passive = <250>; 3551 polling-delay = <1000>; 3552 3553 thermal-sensors = <&tsens0 2>; 3554 3555 trips { 3556 cpu1_alert0: trip-point0 { 3557 temperature = <90000>; 3558 hysteresis = <2000>; 3559 type = "passive"; 3560 }; 3561 3562 cpu1_alert1: trip-point1 { 3563 temperature = <95000>; 3564 hysteresis = <2000>; 3565 type = "passive"; 3566 }; 3567 3568 cpu1_crit: cpu_crit { 3569 temperature = <110000>; 3570 hysteresis = <1000>; 3571 type = "critical"; 3572 }; 3573 }; 3574 3575 cooling-maps { 3576 map0 { 3577 trip = <&cpu1_alert0>; 3578 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3579 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3580 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3581 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3582 }; 3583 map1 { 3584 trip = <&cpu1_alert1>; 3585 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3586 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3587 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3588 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3589 }; 3590 }; 3591 }; 3592 3593 cpu2-thermal { 3594 polling-delay-passive = <250>; 3595 polling-delay = <1000>; 3596 3597 thermal-sensors = <&tsens0 3>; 3598 3599 trips { 3600 cpu2_alert0: trip-point0 { 3601 temperature = <90000>; 3602 hysteresis = <2000>; 3603 type = "passive"; 3604 }; 3605 3606 cpu2_alert1: trip-point1 { 3607 temperature = <95000>; 3608 hysteresis = <2000>; 3609 type = "passive"; 3610 }; 3611 3612 cpu2_crit: cpu_crit { 3613 temperature = <110000>; 3614 hysteresis = <1000>; 3615 type = "critical"; 3616 }; 3617 }; 3618 3619 cooling-maps { 3620 map0 { 3621 trip = <&cpu2_alert0>; 3622 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3623 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3624 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3625 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3626 }; 3627 map1 { 3628 trip = <&cpu2_alert1>; 3629 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3630 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3631 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3633 }; 3634 }; 3635 }; 3636 3637 cpu3-thermal { 3638 polling-delay-passive = <250>; 3639 polling-delay = <1000>; 3640 3641 thermal-sensors = <&tsens0 4>; 3642 3643 trips { 3644 cpu3_alert0: trip-point0 { 3645 temperature = <90000>; 3646 hysteresis = <2000>; 3647 type = "passive"; 3648 }; 3649 3650 cpu3_alert1: trip-point1 { 3651 temperature = <95000>; 3652 hysteresis = <2000>; 3653 type = "passive"; 3654 }; 3655 3656 cpu3_crit: cpu_crit { 3657 temperature = <110000>; 3658 hysteresis = <1000>; 3659 type = "critical"; 3660 }; 3661 }; 3662 3663 cooling-maps { 3664 map0 { 3665 trip = <&cpu3_alert0>; 3666 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3667 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3669 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3670 }; 3671 map1 { 3672 trip = <&cpu3_alert1>; 3673 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3677 }; 3678 }; 3679 }; 3680 3681 cpu4-thermal { 3682 polling-delay-passive = <250>; 3683 polling-delay = <1000>; 3684 3685 thermal-sensors = <&tsens0 7>; 3686 3687 trips { 3688 cpu4_alert0: trip-point0 { 3689 temperature = <90000>; 3690 hysteresis = <2000>; 3691 type = "passive"; 3692 }; 3693 3694 cpu4_alert1: trip-point1 { 3695 temperature = <95000>; 3696 hysteresis = <2000>; 3697 type = "passive"; 3698 }; 3699 3700 cpu4_crit: cpu_crit { 3701 temperature = <110000>; 3702 hysteresis = <1000>; 3703 type = "critical"; 3704 }; 3705 }; 3706 3707 cooling-maps { 3708 map0 { 3709 trip = <&cpu4_alert0>; 3710 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3711 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3712 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3713 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3714 }; 3715 map1 { 3716 trip = <&cpu4_alert1>; 3717 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3721 }; 3722 }; 3723 }; 3724 3725 cpu5-thermal { 3726 polling-delay-passive = <250>; 3727 polling-delay = <1000>; 3728 3729 thermal-sensors = <&tsens0 8>; 3730 3731 trips { 3732 cpu5_alert0: trip-point0 { 3733 temperature = <90000>; 3734 hysteresis = <2000>; 3735 type = "passive"; 3736 }; 3737 3738 cpu5_alert1: trip-point1 { 3739 temperature = <95000>; 3740 hysteresis = <2000>; 3741 type = "passive"; 3742 }; 3743 3744 cpu5_crit: cpu_crit { 3745 temperature = <110000>; 3746 hysteresis = <1000>; 3747 type = "critical"; 3748 }; 3749 }; 3750 3751 cooling-maps { 3752 map0 { 3753 trip = <&cpu5_alert0>; 3754 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3755 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3758 }; 3759 map1 { 3760 trip = <&cpu5_alert1>; 3761 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3765 }; 3766 }; 3767 }; 3768 3769 cpu6-thermal { 3770 polling-delay-passive = <250>; 3771 polling-delay = <1000>; 3772 3773 thermal-sensors = <&tsens0 9>; 3774 3775 trips { 3776 cpu6_alert0: trip-point0 { 3777 temperature = <90000>; 3778 hysteresis = <2000>; 3779 type = "passive"; 3780 }; 3781 3782 cpu6_alert1: trip-point1 { 3783 temperature = <95000>; 3784 hysteresis = <2000>; 3785 type = "passive"; 3786 }; 3787 3788 cpu6_crit: cpu_crit { 3789 temperature = <110000>; 3790 hysteresis = <1000>; 3791 type = "critical"; 3792 }; 3793 }; 3794 3795 cooling-maps { 3796 map0 { 3797 trip = <&cpu6_alert0>; 3798 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3802 }; 3803 map1 { 3804 trip = <&cpu6_alert1>; 3805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3809 }; 3810 }; 3811 }; 3812 3813 cpu7-thermal { 3814 polling-delay-passive = <250>; 3815 polling-delay = <1000>; 3816 3817 thermal-sensors = <&tsens0 10>; 3818 3819 trips { 3820 cpu7_alert0: trip-point0 { 3821 temperature = <90000>; 3822 hysteresis = <2000>; 3823 type = "passive"; 3824 }; 3825 3826 cpu7_alert1: trip-point1 { 3827 temperature = <95000>; 3828 hysteresis = <2000>; 3829 type = "passive"; 3830 }; 3831 3832 cpu7_crit: cpu_crit { 3833 temperature = <110000>; 3834 hysteresis = <1000>; 3835 type = "critical"; 3836 }; 3837 }; 3838 3839 cooling-maps { 3840 map0 { 3841 trip = <&cpu7_alert0>; 3842 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3846 }; 3847 map1 { 3848 trip = <&cpu7_alert1>; 3849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3853 }; 3854 }; 3855 }; 3856 3857 aoss0-thermal { 3858 polling-delay-passive = <250>; 3859 polling-delay = <1000>; 3860 3861 thermal-sensors = <&tsens0 0>; 3862 3863 trips { 3864 aoss0_alert0: trip-point0 { 3865 temperature = <90000>; 3866 hysteresis = <2000>; 3867 type = "hot"; 3868 }; 3869 }; 3870 }; 3871 3872 cluster0-thermal { 3873 polling-delay-passive = <250>; 3874 polling-delay = <1000>; 3875 3876 thermal-sensors = <&tsens0 5>; 3877 3878 trips { 3879 cluster0_alert0: trip-point0 { 3880 temperature = <90000>; 3881 hysteresis = <2000>; 3882 type = "hot"; 3883 }; 3884 cluster0_crit: cluster0_crit { 3885 temperature = <110000>; 3886 hysteresis = <2000>; 3887 type = "critical"; 3888 }; 3889 }; 3890 }; 3891 3892 cluster1-thermal { 3893 polling-delay-passive = <250>; 3894 polling-delay = <1000>; 3895 3896 thermal-sensors = <&tsens0 6>; 3897 3898 trips { 3899 cluster1_alert0: trip-point0 { 3900 temperature = <90000>; 3901 hysteresis = <2000>; 3902 type = "hot"; 3903 }; 3904 cluster1_crit: cluster1_crit { 3905 temperature = <110000>; 3906 hysteresis = <2000>; 3907 type = "critical"; 3908 }; 3909 }; 3910 }; 3911 3912 gpu-thermal-top { 3913 polling-delay-passive = <250>; 3914 polling-delay = <1000>; 3915 3916 thermal-sensors = <&tsens0 11>; 3917 3918 trips { 3919 gpu1_alert0: trip-point0 { 3920 temperature = <90000>; 3921 hysteresis = <2000>; 3922 type = "hot"; 3923 }; 3924 }; 3925 }; 3926 3927 gpu-thermal-bottom { 3928 polling-delay-passive = <250>; 3929 polling-delay = <1000>; 3930 3931 thermal-sensors = <&tsens0 12>; 3932 3933 trips { 3934 gpu2_alert0: trip-point0 { 3935 temperature = <90000>; 3936 hysteresis = <2000>; 3937 type = "hot"; 3938 }; 3939 }; 3940 }; 3941 3942 aoss1-thermal { 3943 polling-delay-passive = <250>; 3944 polling-delay = <1000>; 3945 3946 thermal-sensors = <&tsens1 0>; 3947 3948 trips { 3949 aoss1_alert0: trip-point0 { 3950 temperature = <90000>; 3951 hysteresis = <2000>; 3952 type = "hot"; 3953 }; 3954 }; 3955 }; 3956 3957 q6-modem-thermal { 3958 polling-delay-passive = <250>; 3959 polling-delay = <1000>; 3960 3961 thermal-sensors = <&tsens1 1>; 3962 3963 trips { 3964 q6_modem_alert0: trip-point0 { 3965 temperature = <90000>; 3966 hysteresis = <2000>; 3967 type = "hot"; 3968 }; 3969 }; 3970 }; 3971 3972 mem-thermal { 3973 polling-delay-passive = <250>; 3974 polling-delay = <1000>; 3975 3976 thermal-sensors = <&tsens1 2>; 3977 3978 trips { 3979 mem_alert0: trip-point0 { 3980 temperature = <90000>; 3981 hysteresis = <2000>; 3982 type = "hot"; 3983 }; 3984 }; 3985 }; 3986 3987 wlan-thermal { 3988 polling-delay-passive = <250>; 3989 polling-delay = <1000>; 3990 3991 thermal-sensors = <&tsens1 3>; 3992 3993 trips { 3994 wlan_alert0: trip-point0 { 3995 temperature = <90000>; 3996 hysteresis = <2000>; 3997 type = "hot"; 3998 }; 3999 }; 4000 }; 4001 4002 q6-hvx-thermal { 4003 polling-delay-passive = <250>; 4004 polling-delay = <1000>; 4005 4006 thermal-sensors = <&tsens1 4>; 4007 4008 trips { 4009 q6_hvx_alert0: trip-point0 { 4010 temperature = <90000>; 4011 hysteresis = <2000>; 4012 type = "hot"; 4013 }; 4014 }; 4015 }; 4016 4017 camera-thermal { 4018 polling-delay-passive = <250>; 4019 polling-delay = <1000>; 4020 4021 thermal-sensors = <&tsens1 5>; 4022 4023 trips { 4024 camera_alert0: trip-point0 { 4025 temperature = <90000>; 4026 hysteresis = <2000>; 4027 type = "hot"; 4028 }; 4029 }; 4030 }; 4031 4032 video-thermal { 4033 polling-delay-passive = <250>; 4034 polling-delay = <1000>; 4035 4036 thermal-sensors = <&tsens1 6>; 4037 4038 trips { 4039 video_alert0: trip-point0 { 4040 temperature = <90000>; 4041 hysteresis = <2000>; 4042 type = "hot"; 4043 }; 4044 }; 4045 }; 4046 4047 modem-thermal { 4048 polling-delay-passive = <250>; 4049 polling-delay = <1000>; 4050 4051 thermal-sensors = <&tsens1 7>; 4052 4053 trips { 4054 modem_alert0: trip-point0 { 4055 temperature = <90000>; 4056 hysteresis = <2000>; 4057 type = "hot"; 4058 }; 4059 }; 4060 }; 4061 }; 4062}; 4063