| /arch/arm/boot/compressed/ |
| D | head-sharpsl.S | 36 mrc p15, 0, r4, c0, c0 @ Get Processor ID
54 ldr r6, [r1, #0] @ Load Chip ID
97 .word 0x69052d00 @ PXA255 Processor ID
99 .word 0x69054100 @ PXA270 Processor ID
101 .word 0x57411002 @ w100 Chip ID
103 .word 0x08010000 @ w100 Chip ID Reg Address
147 ldrb r2, [r1, #20] @ NAND Manufacturer ID
148 ldrb r3, [r1, #20] @ NAND Chip ID
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| /arch/arm/mm/ |
| D | cache-v4.S | 40 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
59 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
115 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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| D | proc-v7-2level.S | 47 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
49 bfi r1, r2, #8, #24 @ insert into new context ID
54 mcr p15, 0, r1, c13, c0, 1 @ set context ID
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| D | proc-v6.S | 106 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
109 orr r1, r1, r2 @ insert into new context ID
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
141 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
157 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
161 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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| D | proc-v7.S | 135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
156 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
159 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
163 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
807 .long 0x510f0400 @ Required ID value
808 .long 0xff0ffc00 @ Mask for ID
823 .long 0x000f0000 @ Required ID value
824 .long 0x000f0000 @ Mask for ID
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| D | proc-v7m.S | 231 .long 0x000f0000 @ Required ID value
232 .long 0x000f0000 @ Mask for ID
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| D | proc-sa1100.S | 175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
190 mcr p15, 0, r4, c3, c0, 0 @ domain ID
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| /arch/arm/mach-omap2/ |
| D | omap-smc.S | 46 mov r1, #0x0 @ Process ID
48 mov r12, #0x00 @ Secure Service ID
67 mov r12, r0 @ Copy the secure service ID
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| D | sleep34xx.S | 91 mov r0, #25 @ set service ID for PPA
92 mov r12, r0 @ copy secure service ID in r12
412 mov r0, #40 @ set service ID for PPA
413 mov r12, r0 @ copy secure Service ID in r12
421 mov r0, #42 @ set service ID for PPA
422 mov r12, r0 @ copy secure Service ID in r12
434 @ set service ID for PPA
436 mov r12, r0 @ copy service ID in r12
437 mov r1, #0 @ set task ID for ROM code in r1
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| D | sleep44xx.S | 261 mov r1, #0x0 @ Process ID
264 mov r12, #0x00 @ Secure Service ID
301 mov r1, #0x0 @ Process ID
304 mov r12, #0x00 @ Secure Service ID
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| /arch/mips/include/asm/mach-pmcs-msp71xx/ |
| D | msp_pci.h | 13 #define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) argument
|
| /arch/arm/mach-shmobile/ |
| D | headsmp-scu.S | 22 and r1, r1, #3 @ mask out cpu ID
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| /arch/arm/boot/dts/ |
| D | omap3-cpu-thermal.dtsi | 18 /* sensor ID */
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| D | dra7-iva-thermal.dtsi | 17 /* sensor ID */
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| D | dra7-dspeve-thermal.dtsi | 17 /* sensor ID */
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| D | omap5-gpu-thermal.dtsi | 18 /* sensor ID */
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| D | omap5-core-thermal.dtsi | 18 /* sensor ID */
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| D | omap4-cpu-thermal.dtsi | 18 /* sensor ID */
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| /arch/arm/ |
| D | Kconfig-nommu | 32 hex 'Hard wire the processor ID'
36 If processor has no CP15 register, this processor ID is
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| /arch/sparc/kernel/ |
| D | dtlb_prot.S | 30 sllx %g5, PAGE_SHIFT, %g5 ! Clear context ID bits
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| /arch/x86/kernel/apic/ |
| D | io_apic.c | 1292 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); in print_IO_APIC()
1500 reg_00.bits.ID); in setup_ioapic_ids_from_mpc_nocheck()
1501 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; in setup_ioapic_ids_from_mpc_nocheck()
1546 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) in setup_ioapic_ids_from_mpc_nocheck()
1553 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); in setup_ioapic_ids_from_mpc_nocheck()
1564 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) in setup_ioapic_ids_from_mpc_nocheck()
2409 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { in resume_ioapic_id()
2410 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); in resume_ioapic_id()
2502 "%d\n", ioapic, apic_id, reg_00.bits.ID); in io_apic_get_unique_id()
2503 apic_id = reg_00.bits.ID; in io_apic_get_unique_id()
[all …]
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| /arch/x86/kernel/ |
| D | head_32.S | 238 popfl # set EFLAGS=ID
241 testl $X86_EFLAGS_ID,%eax # did EFLAGS.ID remained set?
242 jz .Lenable_paging # hw disallowed setting of ID bit
317 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
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| /arch/arm/mach-mvebu/ |
| D | pmsu_ll.S | 19 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
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| /arch/arm/common/ |
| D | vlock.S | 49 @ r1: CPU ID (0-based index within cluster)
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| /arch/arm/plat-omap/ |
| D | Kconfig | 102 int "Service ID for the support routine to set L2 AUX control"
106 PPA routine service ID for setting L2 auxiliary control register.
|