| /arch/c6x/lib/ |
| D | csum_64plus.S | 51 || ADD .L1 A16,A9,A9
64 || MVK .L1 1,A2
74 ADD .L1 A16,A9,A9
77 || ADD .L1 A8,A9,A9
84 ZERO .L1 A7
116 || ZERO .L1 A7
204 || ADD .L1 A3,A5,A5
294 MV .L1 A0,A3
311 MVK .L1 2,A0
312 AND .L1 A4,A0,A0
[all …]
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| D | memcpy_64plus.S | 13 AND .L1 0x1,A6,A0
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| /arch/arc/kernel/ |
| D | entry-compact.S | 152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implies both L2 and L1 active
167 ; need to check STATUS32_L2 to determine if L1 was active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
335 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
[all …]
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| /arch/arm/mm/ |
| D | proc-xsc3.S | 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
245 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
269 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| /arch/powerpc/perf/ |
| D | power8-pmu.c | 133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| D | power9-pmu.c | 163 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
164 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
165 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
166 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
167 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
168 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
169 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| /arch/powerpc/boot/dts/ |
| D | sbc8548-pre.dtsi | 34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
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| D | amigaone.dts | 27 d-cache-size = <32768>; // L1, 32K
28 i-cache-size = <32768>; // L1, 32K
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| D | tqm8xx.dts | 33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
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| D | mpc866ads.dts | 26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
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| D | tqm5200.dts | 27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
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| D | mpc7448hpc2.dts | 36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
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| D | charon.dts | 30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
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| /arch/c6x/kernel/ |
| D | head.S | 58 CMPEQ .L1 A10,A0,A0
81 L1: BNOP .S2 L1,5 label
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| /arch/hexagon/lib/ |
| D | memset.S | 159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1: label
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| /arch/m68k/lib/ |
| D | divsi3.S | 95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
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| D | udivsi3.S | 144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
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| /arch/alpha/boot/ |
| D | main.c | 60 #define L1 ((unsigned long *) 0x200802000) macro
72 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | bootp.c | 66 #define L1 ((unsigned long *) 0x200802000) macro
78 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | bootpz.c | 114 #define L1 ((unsigned long *) 0x200802000) macro
126 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| /arch/riscv/lib/ |
| D | tishift.S | 10 beqz a2, .L1
21 .L1: label
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| /arch/sparc/net/ |
| D | bpf_jit_64.h | 21 #define L1 0x11 macro
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| /arch/m68k/fpsp040/ |
| D | setox.S | 104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
[all …]
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| /arch/arm/mach-omap2/ |
| D | sram243x.S | 39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
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| D | sram242x.S | 39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
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