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Searched refs:bus (Results 1 – 25 of 1811) sorted by relevance

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/arch/powerpc/platforms/pasemi/
Dgpio_mdio.c34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) argument
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin) argument
37 static inline void mdio_lo(struct mii_bus *bus) in mdio_lo() argument
39 out_le32(gpio_regs+0x10, 1 << MDIO_PIN(bus)); in mdio_lo()
42 static inline void mdio_hi(struct mii_bus *bus) in mdio_hi() argument
44 out_le32(gpio_regs, 1 << MDIO_PIN(bus)); in mdio_hi()
47 static inline void mdc_lo(struct mii_bus *bus) in mdc_lo() argument
49 out_le32(gpio_regs+0x10, 1 << MDC_PIN(bus)); in mdc_lo()
52 static inline void mdc_hi(struct mii_bus *bus) in mdc_hi() argument
54 out_le32(gpio_regs, 1 << MDC_PIN(bus)); in mdc_hi()
[all …]
Dpci.c25 #define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) argument
27 static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset) in pa_pxp_offset_valid() argument
33 if (bus == 0 && devfn == 0) in pa_pxp_offset_valid()
40 u8 bus, u8 devfn, int offset) in pa_pxp_cfg_addr() argument
42 return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset); in pa_pxp_cfg_addr()
57 static int workaround_5945(struct pci_bus *bus, unsigned int devfn, in workaround_5945() argument
65 if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset)) in workaround_5945()
68 hose = pci_bus_to_host(bus); in workaround_5945()
70 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3); in workaround_5945()
77 dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10); in workaround_5945()
[all …]
/arch/powerpc/kernel/
Dpci-hotplug.c20 static struct pci_bus *find_bus_among_children(struct pci_bus *bus, in find_bus_among_children() argument
26 if (pci_bus_to_OF_node(bus) == dn) in find_bus_among_children()
27 return bus; in find_bus_among_children()
29 list_for_each_entry(tmp, &bus->children, node) { in find_bus_among_children()
42 if (!pdn || !pdn->phb || !pdn->phb->bus) in pci_find_bus_by_node()
45 return find_bus_among_children(pdn->phb->bus, dn); in pci_find_bus_by_node()
57 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_release_device()
79 void pci_hp_remove_devices(struct pci_bus *bus) in pci_hp_remove_devices() argument
85 list_for_each_entry(child_bus, &bus->children, node) in pci_hp_remove_devices()
89 pci_domain_nr(bus), bus->number); in pci_hp_remove_devices()
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Dio-workarounds.c34 struct iowa_bus *bus = &iowa_busses[i]; in iowa_pci_find() local
35 struct pci_controller *phb = bus->phb; in iowa_pci_find()
41 return bus; in iowa_pci_find()
48 return bus; in iowa_pci_find()
59 struct iowa_bus *bus; in iowa_mem_find_bus() local
65 bus = &iowa_busses[token - 1]; in iowa_mem_find_bus()
84 bus = iowa_pci_find(vaddr, paddr); in iowa_mem_find_bus()
86 if (bus == NULL) in iowa_mem_find_bus()
90 return bus; in iowa_mem_find_bus()
115 struct iowa_bus *bus; \
[all …]
Dpci_of_scan.c165 pcibios_bus_to_resource(dev->bus, res, &region); in of_pci_parse_addrs()
176 struct pci_bus *bus, int devfn) in of_create_pci_dev() argument
180 dev = pci_alloc_dev(bus); in of_create_pci_dev()
188 dev->dev.parent = bus->bridge; in of_create_pci_dev()
189 dev->dev.bus = &pci_bus_type; in of_create_pci_dev()
203 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), in of_create_pci_dev()
204 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); in of_create_pci_dev()
236 pci_device_add(dev, bus); in of_create_pci_dev()
253 struct pci_bus *bus; in of_scan_pci_bridge() local
278 bus = pci_find_bus(pci_domain_nr(dev->bus), in of_scan_pci_bridge()
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Dpci-common.c210 resource_size_t pcibios_window_alignment(struct pci_bus *bus, in pcibios_window_alignment() argument
213 struct pci_controller *phb = pci_bus_to_host(bus); in pcibios_window_alignment()
216 return phb->controller_ops.window_alignment(bus, type); in pcibios_window_alignment()
226 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) in pcibios_setup_bridge() argument
228 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_setup_bridge()
231 hose->controller_ops.setup_bridge(bus, type); in pcibios_setup_bridge()
236 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_reset_secondary_bus()
341 int pci_domain_nr(struct pci_bus *bus) in pci_domain_nr() argument
343 struct pci_controller *hose = pci_bus_to_host(bus); in pci_domain_nr()
436 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
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Dpci_64.c65 pci_bus_add_devices(hose->bus); in pcibios_init()
78 int pcibios_unmap_io_space(struct pci_bus *bus) in pcibios_unmap_io_space() argument
82 WARN_ON(bus == NULL); in pcibios_unmap_io_space()
94 if (bus->self) { in pcibios_unmap_io_space()
96 struct resource *res = bus->resource[0]; in pcibios_unmap_io_space()
100 pci_name(bus->self)); in pcibios_unmap_io_space()
110 hose = pci_bus_to_host(bus); in pcibios_unmap_io_space()
177 int pcibios_map_io_space(struct pci_bus *bus) in pcibios_map_io_space() argument
179 WARN_ON(bus == NULL); in pcibios_map_io_space()
184 if (bus->self) { in pcibios_map_io_space()
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/arch/powerpc/platforms/powermac/
Dlow_i2c.c92 int (*open)(struct pmac_i2c_bus *bus);
93 void (*close)(struct pmac_i2c_bus *bus);
94 int (*xfer)(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
383 static int kw_i2c_open(struct pmac_i2c_bus *bus) in kw_i2c_open() argument
385 struct pmac_i2c_host_kw *host = bus->hostdata; in kw_i2c_open()
390 static void kw_i2c_close(struct pmac_i2c_bus *bus) in kw_i2c_close() argument
392 struct pmac_i2c_host_kw *host = bus->hostdata; in kw_i2c_close()
396 static int kw_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize, in kw_i2c_xfer() argument
399 struct pmac_i2c_host_kw *host = bus->hostdata; in kw_i2c_xfer()
401 int use_irq = host->irq && !bus->polled; in kw_i2c_xfer()
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/arch/mips/pci/
Dops-rc32434.c41 #define PCI_CFG_SET(bus, slot, func, off) \ argument
43 ((bus) << 16) | ((slot)<<11) | \
47 struct pci_bus *bus, unsigned int devfn, in config_access() argument
54 PCI_CFG_SET(bus->number, slot, func, where); in config_access()
72 static int read_config_byte(struct pci_bus *bus, unsigned int devfn, in read_config_byte() argument
78 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); in read_config_byte()
83 static int read_config_word(struct pci_bus *bus, unsigned int devfn, in read_config_word() argument
89 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); in read_config_word()
94 static int read_config_dword(struct pci_bus *bus, unsigned int devfn, in read_config_dword() argument
104 if (bus->number == 0 && PCI_SLOT(devfn) > 21) in read_config_dword()
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Dpci-xlp.c60 #define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) argument
63 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, in pci_cfg_read_32bit() argument
72 if (bus->number == 0) { in pci_cfg_read_32bit()
77 } else if (bus->parent->number == 0) { /* SoC bus */ in pci_cfg_read_32bit()
83 } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) { in pci_cfg_read_32bit()
87 pci_cfg_addr(bus->number, devfn, where)); in pci_cfg_read_32bit()
92 static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, in pci_cfg_write_32bit() argument
98 pci_cfg_addr(bus->number, devfn, where & ~3)); in pci_cfg_write_32bit()
102 static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, in nlm_pcibios_read() argument
112 data = pci_cfg_read_32bit(bus, devfn, where); in nlm_pcibios_read()
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/arch/arm/boot/dts/
Dibm-power9-dual.dtsi22 cfam0_i2c0: i2c-bus@0 {
26 cfam0_i2c1: i2c-bus@1 {
30 cfam0_i2c2: i2c-bus@2 {
34 cfam0_i2c3: i2c-bus@3 {
38 cfam0_i2c4: i2c-bus@4 {
42 cfam0_i2c5: i2c-bus@5 {
46 cfam0_i2c6: i2c-bus@6 {
50 cfam0_i2c7: i2c-bus@7 {
54 cfam0_i2c8: i2c-bus@8 {
58 cfam0_i2c9: i2c-bus@9 {
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/arch/x86/kernel/
Daperture_64.c130 static u32 __init find_cap(int bus, int slot, int func, int cap) in find_cap() argument
135 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & in find_cap()
139 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); in find_cap()
144 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); in find_cap()
149 pos = read_pci_config_byte(bus, slot, func, in find_cap()
156 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) in read_agp() argument
165 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func); in read_agp()
166 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); in read_agp()
169 bus, slot, func); in read_agp()
185 aper_low = read_pci_config(bus, slot, func, 0x10); in read_agp()
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/arch/alpha/kernel/
Dsys_nautilus.c76 dev->bus->self && dev->bus->self->device == 0x700f) in nautilus_map_irq()
85 struct pci_bus *bus = pci_isa_hose->bus; in nautilus_kill_arch() local
93 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8); in nautilus_kill_arch()
94 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80); in nautilus_kill_arch()
104 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport); in nautilus_kill_arch()
108 pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport); in nautilus_kill_arch()
210 struct pci_bus *bus; in nautilus_init_pci() local
237 bus = hose->bus = bridge->bus; in nautilus_init_pci()
238 pcibios_claim_one_bus(bus); in nautilus_init_pci()
240 irongate = pci_get_domain_bus_and_slot(pci_domain_nr(bus), 0, 0); in nautilus_init_pci()
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/arch/arm64/kernel/
Dpci.c37 int raw_pci_read(unsigned int domain, unsigned int bus, in raw_pci_read() argument
40 struct pci_bus *b = pci_find_bus(domain, bus); in raw_pci_read()
47 int raw_pci_write(unsigned int domain, unsigned int bus, in raw_pci_write() argument
50 struct pci_bus *b = pci_find_bus(domain, bus); in raw_pci_write()
59 int pcibus_to_node(struct pci_bus *bus) in pcibus_to_node() argument
61 return dev_to_node(&bus->dev); in pcibus_to_node()
74 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) in acpi_pci_bus_find_domain_nr() argument
76 struct pci_config_window *cfg = bus->sysdata; in acpi_pci_bus_find_domain_nr()
86 struct pci_config_window *cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare()
88 struct device *bus_dev = &bridge->bus->dev; in pcibios_root_bridge_prepare()
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/arch/x86/include/asm/
Dpci.h41 static inline int pci_domain_nr(struct pci_bus *bus) in pci_domain_nr() argument
43 struct pci_sysdata *sd = bus->sysdata; in pci_domain_nr()
48 static inline int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
50 return pci_domain_nr(bus); in pci_proc_domain()
55 static inline void *_pci_root_bus_fwnode(struct pci_bus *bus) in _pci_root_bus_fwnode() argument
57 struct pci_sysdata *sd = bus->sysdata; in _pci_root_bus_fwnode()
65 static inline bool is_vmd(struct pci_bus *bus) in is_vmd() argument
68 struct pci_sysdata *sd = bus->sysdata; in is_vmd()
93 void pcibios_scan_root(int bus);
132 static inline int __pcibus_to_node(const struct pci_bus *bus) in __pcibus_to_node() argument
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/arch/x86/pci/
Dearly.c11 u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config() argument
14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
19 u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_byte() argument
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
27 u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_16() argument
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
35 void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, in write_pci_config() argument
38 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
42 void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val) in write_pci_config_byte() argument
44 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_byte()
[all …]
Dintel_mid_pci.c63 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) in fixed_bar_cap() argument
74 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, in fixed_bar_cap()
83 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number, in fixed_bar_cap()
95 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, in pci_device_update_fixed() argument
102 domain = pci_domain_nr(bus); in pci_device_update_fixed()
103 busnum = bus->number; in pci_device_update_fixed()
149 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) in type1_access_ok() argument
161 if (bus == 0 && (devfn == PCI_DEVFN(2, 0) in type1_access_ok()
168 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, in pci_read() argument
171 if (type1_access_ok(bus->number, devfn, where)) in pci_read()
[all …]
Di386.c136 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) in skip_isa_ioresource_align()
233 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
238 if (bus->self) in pcibios_allocate_bus_resources()
239 pcibios_allocate_bridge_resources(bus->self); in pcibios_allocate_bus_resources()
240 list_for_each_entry(child, &bus->children, node) in pcibios_allocate_bus_resources()
307 static void pcibios_allocate_resources(struct pci_bus *bus, int pass) in pcibios_allocate_resources() argument
312 list_for_each_entry(dev, &bus->devices, bus_list) { in pcibios_allocate_resources()
341 static void pcibios_allocate_rom_resources(struct pci_bus *bus) in pcibios_allocate_rom_resources() argument
346 list_for_each_entry(dev, &bus->devices, bus_list) { in pcibios_allocate_rom_resources()
357 struct pci_bus *bus; in pcibios_assign_resources() local
[all …]
Dnumachip.c21 static inline char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) in pci_dev_base() argument
23 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base()
26 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
30 static int pci_mmcfg_read_numachip(unsigned int seg, unsigned int bus, in pci_mmcfg_read_numachip() argument
36 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) { in pci_mmcfg_read_numachip()
42 if (unlikely(bus == 0 && devfn >= limit)) { in pci_mmcfg_read_numachip()
48 addr = pci_dev_base(seg, bus, devfn); in pci_mmcfg_read_numachip()
70 static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus, in pci_mmcfg_write_numachip() argument
76 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) in pci_mmcfg_write_numachip()
80 if (unlikely(bus == 0 && devfn >= limit)) in pci_mmcfg_write_numachip()
[all …]
/arch/powerpc/include/asm/
Dpmac_low_i2c.h64 extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
65 extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
66 extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
67 extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
68 extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
71 extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
87 extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
88 extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
89 extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
90 extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
Dpci-bridge.h19 void (*dma_bus_setup)(struct pci_bus *bus);
23 int (*probe_mode)(struct pci_bus *bus);
34 resource_size_t (*window_alignment)(struct pci_bus *bus,
36 void (*setup_bridge)(struct pci_bus *bus,
53 struct pci_bus *bus; member
134 extern int early_read_config_byte(struct pci_controller *hose, int bus,
136 extern int early_read_config_word(struct pci_controller *hose, int bus,
138 extern int early_read_config_dword(struct pci_controller *hose, int bus,
140 extern int early_write_config_byte(struct pci_controller *hose, int bus,
142 extern int early_write_config_word(struct pci_controller *hose, int bus,
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/arch/mips/lib/
Diomap-pci.c19 struct pci_controller *ctrl = dev->bus->sysdata; in __pci_ioport_map()
24 struct pci_bus *bus = dev->bus; in __pci_ioport_map() local
27 while (bus->parent) in __pci_ioport_map()
28 bus = bus->parent; in __pci_ioport_map()
32 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number); in __pci_ioport_map()
/arch/arm/mach-orion5x/
Dpci.c49 static int pcie_valid_config(int bus, int dev) in pcie_valid_config() argument
56 if (bus == 0 && dev == 0) in pcie_valid_config()
62 if (bus == 0 && dev != 1) in pcie_valid_config()
76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, in pcie_rd_conf() argument
82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { in pcie_rd_conf()
88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); in pcie_rd_conf()
94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, in pcie_rd_conf_wa() argument
99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { in pcie_rd_conf_wa()
115 bus, devfn, where, size, val); in pcie_rd_conf_wa()
120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, in pcie_wr_conf() argument
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/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
35 compatible = "samsung,exynos-bus";
37 clock-names = "bus";
43 compatible = "samsung,exynos-bus";
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/arch/sh/drivers/pci/
Dops-sh7786.c20 struct pci_bus *bus, unsigned int devfn, int where, u32 *data) in sh7786_pcie_config_access() argument
22 struct pci_channel *chan = bus->sysdata; in sh7786_pcie_config_access()
27 type = !!bus->parent; in sh7786_pcie_config_access()
30 if (bus->number > 255 || dev > 31 || func > 7) in sh7786_pcie_config_access()
48 if (pci_is_root_bus(bus)) { in sh7786_pcie_config_access()
64 pci_write_reg(chan, (bus->number << 24) | (dev << 19) | in sh7786_pcie_config_access()
89 static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, in sh7786_pcie_read() argument
102 ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, in sh7786_pcie_read()
116 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x " in sh7786_pcie_read()
117 "where=0x%04x size=%d val=0x%08lx\n", bus->number, in sh7786_pcie_read()
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