| /arch/arm/include/asm/ |
| D | kvm_hyp.h | 40 #define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
41 #define CPACR __ACCESS_CP15(c1, 0, c0, 2)
42 #define HCR __ACCESS_CP15(c1, 4, c1, 0)
43 #define HDCR __ACCESS_CP15(c1, 4, c1, 1)
44 #define HCPTR __ACCESS_CP15(c1, 4, c1, 2)
45 #define HSTR __ACCESS_CP15(c1, 4, c1, 3)
48 #define VTCR __ACCESS_CP15(c2, 4, c1, 2)
52 #define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
53 #define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
60 #define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
[all …]
|
| /arch/arm/common/ |
| D | secure_cntvoff.S | 21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
|
| /arch/arm/include/asm/hardware/ |
| D | cp14.h | 46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
58 #define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
74 #define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
90 #define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
106 #define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
121 #define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
122 #define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
123 #define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
124 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
125 #define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
[all …]
|
| /arch/arm/mach-iop32x/include/mach/ |
| D | entry-macro.S | 11 mrc p15, 0, \tmp, c15, c1, 0
13 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
14 mrc p15, 0, \tmp, c15, c1, 0
27 mrc p15, 0, \tmp1, c15, c1, 0
30 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
|
| /arch/s390/boot/ |
| D | string.c | 10 unsigned char c1, c2; in strncmp() local
13 c1 = *cs++; in strncmp()
15 if (c1 != c2) in strncmp()
16 return c1 < c2 ? -1 : 1; in strncmp()
17 if (!c1) in strncmp()
|
| /arch/arm/mm/ |
| D | proc-v6.S | 39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
144 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
145 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
146 mrc p15, 0, r9, c1, c0, 0 @ control register
168 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
169 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
197 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
[all …]
|
| D | proc-v7.S | 32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
147 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
148 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
179 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
181 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
182 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
[all …]
|
| D | proc-sa110.S | 37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
70 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
102 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
170 mrc p15, 0, r0, c1, c0 @ get control register v4
|
| D | proc-arm720.S | 43 mrc p15, 0, r0, c1, c0, 0
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
97 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 mrc p15, 0, r0, c1, c0 @ get control register
142 mrc p15, 0, r0, c1, c0 @ get control register
|
| D | proc-fa526.S | 36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
145 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
155 mrc p15, 0, r0, c1, c0 @ get control register v4
|
| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
109 mrc p15, 0, r0, c1, c0 @ get control register
|
| D | proc-sa1100.S | 41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
177 mrc p15, 0, r6, c1, c0, 0 @ control reg
208 mrc p15, 0, r0, c1, c0 @ get control register v4
|
| D | proc-xsc3.S | 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
417 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
420 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
421 mrc p15, 0, r9, c1, c0, 0 @ control reg
435 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
440 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
|
| D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
346 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
349 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
350 mrc p15, 0, r9, c1, c0, 0 @ control reg
364 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
369 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
| /arch/mips/include/asm/sibyte/ |
| D | board.h | 29 #define setleds(t0, t1, c0, c1, c2, c3) \
33 li t1, c1; \
40 #define setleds(t0, t1, c0, c1, c2, c3)
|
| /arch/arm/mach-omap2/ |
| D | sleep44xx.S | 88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
189 mrc p15, 0, r0, c1, c0, 0
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
204 mcreq p15, 0, r0, c1, c0, 1
270 mrc p15, 0, r0, c1, c0, 1
[all …]
|
| /arch/arm/kernel/ |
| D | iwmmxt.S | 74 XSC(mrc p15, 0, r2, c15, c1, 0)
75 PJ4(mrc p15, 0, r2, c1, c0, 2)
82 XSC(mcr p15, 0, r2, c15, c1, 0)
84 PJ4(mcr p15, 0, r2, c1, c0, 2)
211 XSC(mrc p15, 0, r4, c15, c1, 0)
213 XSC(mcr p15, 0, r4, c15, c1, 0)
214 PJ4(mrc p15, 0, r4, c1, c0, 2)
216 PJ4(mcr p15, 0, r4, c1, c0, 2)
226 XSC(mcr p15, 0, r4, c15, c1, 0)
228 PJ4(mcr p15, 0, r4, c1, c0, 2)
[all …]
|
| /arch/arm/boot/compressed/ |
| D | big-endian.S | 11 mrc p15, 0, r0, c1, c0, 0 @ read control reg
13 mcr p15, 0, r0, c1, c0, 0 @ write control reg
|
| D | string.c | 93 unsigned char c1, c2; in strcmp() local
97 c1 = *cs++; in strcmp()
99 res = c1 - c2; in strcmp()
102 } while (c1); in strcmp()
|
| /arch/arm/kvm/hyp/ |
| D | entry.S | 100 mrc p15, 4, r1, c1, c1, 2 @ HCPTR
102 mcr p15, 4, r1, c1, c1, 2 @ HCPTR
|
| /arch/x86/boot/ |
| D | string.c | 66 unsigned char c1, c2; in strncmp() local
69 c1 = *cs++; in strncmp()
71 if (c1 != c2) in strncmp()
72 return c1 < c2 ? -1 : 1; in strncmp()
73 if (!c1) in strncmp()
|
| /arch/arm/mach-spear/ |
| D | headsmp.S | 32 mrc p15, 0, r0, c1, c0, 1
34 mcr p15, 0, r0, c1, c0, 1
|
| /arch/arm/mach-tegra/ |
| D | sleep.S | 38 mrc p15, 0, r2, c1, c0, 0
41 mcrne p15, 0, r2, c1, c0, 0
114 mrc p15, 0, r3, c1, c0, 0
118 mcr p15, 0, r3, c1, c0, 0
|
| /arch/arm/include/debug/ |
| D | icedcc.S | 21 mrc p14, 0, \rx, c0, c1, 0
31 mrc p14, 0, \rx, c0, c1, 0
64 mcr p14, 0, \rd, c1, c0, 0
|
| /arch/arm/kvm/ |
| D | init.S | 96 mrc p15, 4, r0, c1, c0, 0 @ HSCR
99 mrc p15, 0, r1, c1, c0, 0 @ SCTLR
106 mcr p15, 4, r0, c1, c0, 0 @ HSCR
129 mrc p15, 4, r1, c1, c0, 0 @ HSCTLR
132 mcr p15, 4, r1, c1, c0, 0 @ HSCTLR
|