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Searched refs:dcache (Results 1 – 25 of 43) sorted by relevance

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/arch/sh/kernel/cpu/sh2/
Dprobe.c34 boot_cpu_data.dcache.ways = 4; in cpu_probe()
35 boot_cpu_data.dcache.way_incr = (1<<12); in cpu_probe()
36 boot_cpu_data.dcache.sets = 256; in cpu_probe()
37 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
38 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
39 boot_cpu_data.dcache.flags = 0; in cpu_probe()
56 boot_cpu_data.dcache.ways = 1; in cpu_probe()
57 boot_cpu_data.dcache.sets = 256; in cpu_probe()
58 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
59 boot_cpu_data.dcache.linesz = 32; in cpu_probe()
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/arch/sh/kernel/cpu/sh3/
Dprobe.c50 boot_cpu_data.dcache.ways = 4; in cpu_probe()
51 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
52 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
53 boot_cpu_data.dcache.flags = 0; in cpu_probe()
60 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
61 boot_cpu_data.dcache.entry_mask = 0x7f0; in cpu_probe()
62 boot_cpu_data.dcache.sets = 128; in cpu_probe()
67 boot_cpu_data.dcache.way_incr = (1 << 12); in cpu_probe()
68 boot_cpu_data.dcache.entry_mask = 0xff0; in cpu_probe()
69 boot_cpu_data.dcache.sets = 256; in cpu_probe()
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/arch/mips/mm/
Dc-octeon.c187 c->dcache.linesz = 128; in probe_octeon()
189 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
191 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
192 c->dcache.ways = 64; in probe_octeon()
194 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
195 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; in probe_octeon()
206 c->dcache.linesz = 128; in probe_octeon()
207 c->dcache.ways = 32; in probe_octeon()
208 c->dcache.sets = 8; in probe_octeon()
209 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
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Dc-r4k.c1094 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1095 c->dcache.ways = 2; in probe_pcache()
1096 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1108 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1109 c->dcache.ways = 2; in probe_pcache()
1110 c->dcache.waybit = 0; in probe_pcache()
1122 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1123 c->dcache.ways = 4; in probe_pcache()
1124 c->dcache.waybit = 0; in probe_pcache()
1142 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
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Dc-tx39.c308 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
309 current_cpu_data.dcache.linesz = 4; in tx39_probe_cache()
314 current_cpu_data.dcache.ways = 2; in tx39_probe_cache()
315 current_cpu_data.dcache.linesz = 16; in tx39_probe_cache()
321 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
322 current_cpu_data.dcache.linesz = 16; in tx39_probe_cache()
388 (dcache_size / current_cpu_data.dcache.ways) - 1, in tx39_cache_init()
398 current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways; in tx39_cache_init()
402 current_cpu_data.dcache.sets = in tx39_cache_init()
403 current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz; in tx39_cache_init()
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/arch/sh/kernel/cpu/
Dinit.c128 waysize = current_cpu_data.dcache.sets; in cache_init()
139 waysize <<= current_cpu_data.dcache.entry_shift; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
155 addr += current_cpu_data.dcache.linesz) in cache_init()
158 addrstart += current_cpu_data.dcache.way_incr; in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
204 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); in detect_cache_shape()
206 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) in detect_cache_shape()
313 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - in cpu_init()
314 current_cpu_data.dcache.linesz; in cpu_init()
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/arch/sh/kernel/cpu/sh2a/
Dprobe.c43 boot_cpu_data.dcache.ways = 4; in cpu_probe()
44 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
45 boot_cpu_data.dcache.sets = 128; in cpu_probe()
46 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
47 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
48 boot_cpu_data.dcache.flags = 0; in cpu_probe()
56 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/arch/sh/mm/
Dcache-sh7705.c36 ways = current_cpu_data.dcache.ways; in cache_wback_all()
37 waysize = current_cpu_data.dcache.sets; in cache_wback_all()
38 waysize <<= current_cpu_data.dcache.entry_shift; in cache_wback_all()
47 addr += current_cpu_data.dcache.linesz) { in cache_wback_all()
58 addrstart += current_cpu_data.dcache.way_incr; in cache_wback_all()
104 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
105 waysize = current_cpu_data.dcache.sets; in __flush_dcache_page()
106 waysize <<= current_cpu_data.dcache.entry_shift; in __flush_dcache_page()
115 addr += current_cpu_data.dcache.linesz) { in __flush_dcache_page()
125 addrstart += current_cpu_data.dcache.way_incr; in __flush_dcache_page()
Dcache.c64 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in copy_to_user_page()
71 if (boot_cpu_data.dcache.n_aliases) in copy_to_user_page()
83 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in copy_from_user_page()
90 if (boot_cpu_data.dcache.n_aliases) in copy_from_user_page()
102 if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) && in copy_user_highpage()
142 if (!boot_cpu_data.dcache.n_aliases) in __update_cache()
158 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in __flush_anon_page()
179 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_mm()
187 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_dup_mm()
268 boot_cpu_data.dcache.ways, in emit_cache_params()
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Dcache-sh4.c154 (current_cpu_data.dcache.sets << in flush_dcache_all()
155 current_cpu_data.dcache.entry_shift) * in flush_dcache_all()
156 current_cpu_data.dcache.ways; in flush_dcache_all()
158 entry_offset = 1 << current_cpu_data.dcache.entry_shift; in flush_dcache_all()
242 map_coherent = (current_cpu_data.dcache.n_aliases && in sh4_flush_cache_page()
293 if (boot_cpu_data.dcache.n_aliases == 0) in sh4_flush_cache_range()
321 struct cache_info *dcache; in __flush_cache_one() local
326 dcache = &boot_cpu_data.dcache; in __flush_cache_one()
328 way_count = dcache->ways; in __flush_cache_one()
329 way_incr = dcache->way_incr; in __flush_cache_one()
Dcache-sh5.c249 cpu_data->dcache.entry_mask) >> in sh64_dcache_purge_sets()
250 cpu_data->dcache.entry_shift; in sh64_dcache_purge_sets()
254 set_offset &= (cpu_data->dcache.sets - 1); in sh64_dcache_purge_sets()
256 (set_offset << cpu_data->dcache.entry_shift); in sh64_dcache_purge_sets()
265 eaddr1 = eaddr0 + cpu_data->dcache.way_size * in sh64_dcache_purge_sets()
266 cpu_data->dcache.ways; in sh64_dcache_purge_sets()
269 eaddr += cpu_data->dcache.way_size) { in sh64_dcache_purge_sets()
274 eaddr1 = eaddr0 + cpu_data->dcache.way_size * in sh64_dcache_purge_sets()
275 cpu_data->dcache.ways; in sh64_dcache_purge_sets()
278 eaddr += cpu_data->dcache.way_size) { in sh64_dcache_purge_sets()
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Dcache-sh3.c46 for (j = 0; j < current_cpu_data.dcache.ways; j++) { in sh3__flush_wback_region()
50 addr = addrstart | (v & current_cpu_data.dcache.entry_mask); in sh3__flush_wback_region()
62 addrstart += current_cpu_data.dcache.way_incr; in sh3__flush_wback_region()
87 (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; in sh3__flush_purge_region()
Dcache-shx3.c27 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { in shx3_cache_init()
31 boot_cpu_data.dcache.n_aliases = 0; in shx3_cache_init()
Dcache-sh2a.c60 nr_ways = current_cpu_data.dcache.ways; in sh2a__flush_wback_region()
68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); in sh2a__flush_wback_region()
107 int nr_ways = current_cpu_data.dcache.ways; in sh2a__flush_purge_region()
Dcache-debugfs.c49 cache = &current_cpu_data.dcache; in cache_seq_show()
/arch/sh/kernel/cpu/sh4/
Dprobe.c44 boot_cpu_data.dcache.way_incr = (1 << 14); in cpu_probe()
45 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
46 boot_cpu_data.dcache.sets = 512; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
48 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache.ways = 2; in cpu_probe()
210 if (boot_cpu_data.dcache.ways > 1) { in cpu_probe()
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/arch/mips/include/asm/
Dr4kcache.h571 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
574 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
578 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
581 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
585 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
586 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
604 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
607 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
610 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
633 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
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/arch/sh/kernel/cpu/sh5/
Dprobe.c59 boot_cpu_data.dcache = boot_cpu_data.icache; in cpu_probe()
65 set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags)); in cpu_probe()
67 set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); in cpu_probe()
/arch/mips/kernel/
Dcacheinfo.c30 if (c->dcache.waysize) in init_cache_level()
81 populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); in populate_cache_leaves()
85 populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); in populate_cache_leaves()
/arch/powerpc/perf/
Dpower8-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
Dpower9-pmu.c163 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
164 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
165 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
166 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
/arch/microblaze/boot/dts/
Dsystem.dts54 xlnx,allow-dcache-wr = <0x1>;
62 xlnx,dcache-addr-tag = <0xf>;
63 xlnx,dcache-always-used = <0x1>;
64 xlnx,dcache-byte-size = <0x2000>;
65 xlnx,dcache-line-len = <0x4>;
66 xlnx,dcache-use-fsl = <0x1>;
104 xlnx,use-dcache = <0x1>;
/arch/powerpc/kernel/
Dcacheinfo.c363 struct cache *dcache, *icache; in cache_do_one_devnode_split() local
368 dcache = new_cache(CACHE_TYPE_DATA, level, node); in cache_do_one_devnode_split()
371 if (!dcache || !icache) in cache_do_one_devnode_split()
374 dcache->next_local = icache; in cache_do_one_devnode_split()
376 return dcache; in cache_do_one_devnode_split()
378 release_cache(dcache); in cache_do_one_devnode_split()
/arch/unicore32/boot/compressed/
Dhead.S89 mov r0, #0x1c @ en icache and wb dcache
140 movc p0.c5, r0, #14 @ flush dcache
/arch/nios2/boot/dts/
D3c120_devboard.dts27 dcache-line-size = <32>;
29 dcache-size = <32768>;

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