| /arch/powerpc/platforms/cell/spufs/ |
| D | spu_restore.c | 145 unsigned int event_mask; in restore_event_mask() local
150 offset = LSCSA_QW_OFFSET(event_mask); in restore_event_mask()
151 event_mask = regs_spill[offset].slot[0]; in restore_event_mask()
152 spu_writech(SPU_WrEventMask, event_mask); in restore_event_mask()
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| D | spu_utils.h | 56 unsigned int event_mask = 0; in set_event_mask() local
63 spu_writech(SPU_WrEventMask, event_mask); in set_event_mask()
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| D | spu_save.c | 32 offset = LSCSA_QW_OFFSET(event_mask); in save_event_mask()
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| D | file.c | 1844 lscsa->event_mask.slot[0] = (u32) val; in spufs_event_mask_set()
1853 return lscsa->event_mask.slot[0]; in spufs_event_mask_get()
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| /arch/x86/events/intel/ |
| D | uncore_snbep.c | 805 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
961 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1071 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1152 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
1184 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
1420 .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \
1533 .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK,
1663 .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1686 .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1774 .event_mask = IVBEP_PMON_RAW_EVENT_MASK,
[all …]
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| D | uncore_snb.c | 205 .event_mask = SNB_UNC_RAW_EVENT_MASK,
219 .event_mask = SNB_UNC_RAW_EVENT_MASK,
283 .event_mask = SNB_UNC_RAW_EVENT_MASK,
316 .event_mask = SNB_UNC_RAW_EVENT_MASK,
345 .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
358 .event_mask = SNB_UNC_RAW_EVENT_MASK,
1025 .event_mask = NHM_UNC_RAW_EVENT_MASK,
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| D | uncore_nhmex.c | 251 else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0) in nhmex_uncore_msr_enable_event()
288 .event_mask = NHMEX_U_PMON_RAW_EVENT_MASK,
320 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
342 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
431 .event_mask = NHMEX_B_PMON_RAW_EVENT_MASK,
508 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
934 .event_mask = NHMEX_M_PMON_RAW_EVENT_MASK,
1197 .event_mask = NHMEX_R_PMON_RAW_EVENT_MASK,
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| D | uncore.h | 55 unsigned event_mask; member
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| D | uncore.c | 761 (pmu->type->event_mask | ((u64)pmu->type->event_mask_ext << 32)); in uncore_pmu_event_init()
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| /arch/sh/kernel/ |
| D | hw_breakpoint.c | 298 unsigned long event_mask = (1 << i); in hw_breakpoint_handler() local
300 if (likely(!(cmf & event_mask))) in hw_breakpoint_handler()
319 sh_ubc->clear_triggered_mask(event_mask); in hw_breakpoint_handler()
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| /arch/x86/oprofile/ |
| D | op_x86_model.h | 41 u16 event_mask; member
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| D | nmi_int.c | 56 event &= model->event_mask ? model->event_mask : 0xFF; in op_x86_get_ctrl()
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| D | op_model_amd.c | 531 .event_mask = OP_EVENT_MASK,
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| /arch/sparc/kernel/ |
| D | ldc.c | 779 static void send_events(struct ldc_channel *lp, unsigned int event_mask) in send_events() argument
781 if (event_mask & LDC_EVENT_RESET) in send_events()
783 if (event_mask & LDC_EVENT_UP) in send_events()
785 if (event_mask & LDC_EVENT_DATA_READY) in send_events()
793 unsigned int event_mask; in ldc_rx() local
810 event_mask = 0; in ldc_rx()
822 event_mask |= LDC_EVENT_UP; in ldc_rx()
847 event_mask |= event; in ldc_rx()
850 event_mask |= LDC_EVENT_DATA_READY; in ldc_rx()
869 event_mask |= err; in ldc_rx()
[all …]
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| D | perf_event.c | 165 int event_mask; member
329 .event_mask = 0x3f,
467 .event_mask = 0x7,
602 .event_mask = 0xfff,
759 .event_mask = 0x7ff,
789 .event_mask = 0x7ff,
817 return event_encoding(sparc_pmu->event_mask, idx); in mask_for_index()
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| /arch/powerpc/include/asm/ |
| D | spu_csa.h | 79 struct spu_reg128 event_mask; member
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| /arch/powerpc/platforms/ps3/ |
| D | device-init.c | 684 u64 event_mask; /* OR of 1UL << enum ps3_notify_type */ member
824 notify_cmd->event_mask = 1UL << notify_region_probe; in ps3_probe_thread()
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