Searched refs:fclk (Results 1 – 11 of 11) sorted by relevance
| /arch/h8300/boot/dts/ |
| D | edosk2674.dts | 38 fclk: fclk { label
75 clocks = <&fclk>;
83 clocks = <&fclk>;
91 clocks = <&fclk>;
98 clocks = <&fclk>;
105 clocks = <&fclk>;
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| D | h8300h_sim.dts | 31 fclk: fclk { label
69 clocks = <&fclk>;
78 clocks = <&fclk>;
86 clocks = <&fclk>;
94 clocks = <&fclk>;
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| D | h8s_sim.dts | 37 fclk: fclk { label
74 clocks = <&fclk>;
82 clocks = <&fclk>;
90 clocks = <&fclk>;
97 clocks = <&fclk>;
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| /arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 131 clock-names = "fclk";
144 clock-names = "fclk";
157 clock-names = "fclk";
170 clock-names = "fclk";
183 clock-names = "fclk";
196 clock-names = "fclk";
209 clock-names = "fclk";
222 clock-names = "fclk";
235 clock-names = "fclk";
248 clock-names = "fclk";
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| D | k3-j721e-mcu-wakeup.dtsi | 64 clock-names = "fclk";
77 clock-names = "fclk";
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| /arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 25 struct clk *fclk, phy_clk; member
222 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
223 if (IS_ERR(port->fclk)) { in pcie_clk_init()
224 ret = PTR_ERR(port->fclk); in pcie_clk_init()
228 clk_enable(port->fclk); in pcie_clk_init()
248 clk_disable(port->fclk); in pcie_clk_init()
249 clk_put(port->fclk); in pcie_clk_init()
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| /arch/arm/mach-omap2/ |
| D | timer.c | 318 timer->fclk = of_clk_get_by_name(np, "fck"); in omap_dm_timer_init_one()
334 if (IS_ERR_OR_NULL(timer->fclk)) in omap_dm_timer_init_one()
335 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in omap_dm_timer_init_one()
336 if (IS_ERR(timer->fclk)) in omap_dm_timer_init_one()
337 return PTR_ERR(timer->fclk); in omap_dm_timer_init_one()
343 WARN(clk_set_parent(timer->fclk, src) < 0, in omap_dm_timer_init_one()
358 timer->rate = clk_get_rate(timer->fclk); in omap_dm_timer_init_one()
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| D | prm3xxx.c | 229 u32 wkst, fclk, iclk, clken; in omap3xxx_prm_clear_mod_irqs() local
242 fclk = omap2_cm_read_mod_reg(module, fclk_off); in omap3xxx_prm_clear_mod_irqs()
259 omap2_cm_write_mod_reg(fclk, module, fclk_off); in omap3xxx_prm_clear_mod_irqs()
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| /arch/arm/plat-samsung/include/plat/ |
| D | cpu-freq.h | 32 unsigned long fclk; member
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| /arch/arm/boot/dts/ |
| D | zynq-parallella.dts | 35 fclk-enable = <0xf>;
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| D | zynq-7000.dtsi | 251 fclk-enable = <0>;
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